drivers: cache: Cache driver for NXP XCACHE controller

drivers/cache/CMakeLists.txt

@@ -9,3 +9,4 @@ zephyr_library_sources_ifdef(CONFIG_CACHE_ASPEED	cache_aspeed.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_ANDES 	cache_andes.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE		cache_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_NRF_CACHE	cache_nrf.c)
+zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_XCACHE	cache_nxp_xcache.c)

drivers/cache/Kconfig

@@ -21,5 +21,6 @@ comment "Device Drivers"
 source "drivers/cache/Kconfig.aspeed"
 source "drivers/cache/Kconfig.nrf"
 source "drivers/cache/Kconfig.andes"
+source "drivers/cache/Kconfig.nxp_xcache"
 
 endif # CACHE

drivers/cache/Kconfig.nxp_xcache

@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config CACHE_NXP_XCACHE
+	bool "NXP external cache driver for xcache controller"
+	default y
+	select CACHE_HAS_DRIVER
+	depends on HAS_MCUX_XCACHE
+	help
+	  This option enables the XCACHE driver for NXP SOC's.

drivers/cache/cache_nxp_xcache.c

@@ -0,0 +1,125 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/cache.h>
+#include <zephyr/logging/log.h>
+#include <soc.h>
+#include <fsl_cache.h>
+
+LOG_MODULE_REGISTER(cache_nxp_xcache, CONFIG_CACHE_LOG_LEVEL);
+
+#if !defined(NXP_XCACHE_INSTR)
+#define NXP_XCACHE_INSTR XCACHE_PC
+#endif
+
+#if !defined(NXP_XCACHE_DATA)
+#define NXP_XCACHE_DATA XCACHE_PS
+#endif
+
+void cache_data_enable(void)
+{
+	XCACHE_EnableCache(NXP_XCACHE_DATA);
+}
+
+void cache_data_disable(void)
+{
+	XCACHE_DisableCache(NXP_XCACHE_DATA);
+}
+
+int cache_data_flush_all(void)
+{
+	XCACHE_CleanCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_invd_all(void)
+{
+	XCACHE_InvalidateCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_flush_and_invd_all(void)
+{
+	XCACHE_CleanInvalidateCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_flush_range(void *addr, size_t size)
+{
+	XCACHE_CleanCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_data_invd_range(void *addr, size_t size)
+{
+	XCACHE_InvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_data_flush_and_invd_range(void *addr, size_t size)
+{
+	XCACHE_CleanInvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+void cache_instr_enable(void)
+{
+	XCACHE_EnableCache(NXP_XCACHE_INSTR);
+}
+
+void cache_instr_disable(void)
+{
+	XCACHE_DisableCache(NXP_XCACHE_INSTR);
+}
+
+int cache_instr_flush_all(void)
+{
+	XCACHE_CleanCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_invd_all(void)
+{
+	XCACHE_InvalidateCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_flush_and_invd_all(void)
+{
+	XCACHE_CleanInvalidateCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_flush_range(void *addr, size_t size)
+{
+	XCACHE_CleanCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_instr_invd_range(void *addr, size_t size)
+{
+	XCACHE_InvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_instr_flush_and_invd_range(void *addr, size_t size)
+{
+	XCACHE_CleanInvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}

modules/Kconfig.mcux

@@ -364,6 +364,11 @@ config HAS_MCUX_XBARA
 	help
 	  Set if the XBARA module is present on the SoC.
 
+config HAS_MCUX_XCACHE
+	bool
+	help
+	  Set if the XCACHE module is present on the SoC.
+
 config HAS_NXP_MONOLITHIC_NBU
 	bool
 	help

soc/nxp/imxrt/imxrt118x/Kconfig

@@ -28,6 +28,8 @@ config SOC_SERIES_IMXRT118X
 
 config SOC_MIMXRT1189_CM33
 	select CPU_CORTEX_M33
+	select HAS_MCUX_XCACHE
+	select CACHE_MANAGEMENT
 
 config SOC_MIMXRT1189_CM7
 	select CPU_CORTEX_M7
@@ -66,12 +68,4 @@ config S3MU_MCUX_S3MU
 	default y
 	bool "Use S3MU MCUX Driver"
 
-config IMXRT118X_CM33_XCACHE_PS
-	bool "Use CM33 XCACHE_PS"
-	default y if SOC_MIMXRT1189_CM33
-	help
-	  Use CM33 XCACHE_PS at boot. Please note XCACHE_PC have been
-	  enabled in SystemInit function. If this Kconfig is cleared,
-	  the XCACHE controller won't be enabled during SOC init
-
 endif # SOC_SERIES_IMXRT118X

soc/nxp/imxrt/imxrt118x/Kconfig.defconfig

@@ -34,4 +34,8 @@ config NXP_IMXRT_BOOT_HEADER
 
 endif # SECOND_CORE_MCUX
 
+choice CACHE_TYPE
+	default EXTERNAL_CACHE if SOC_MIMXRT1189_CM33
+endchoice
+
 endif # SOC_SERIES_IMXRT118X

soc/nxp/imxrt/imxrt118x/soc.c

@@ -10,11 +10,7 @@
 #include <soc.h>
 #include <zephyr/linker/sections.h>
 #include <zephyr/linker/linker-defs.h>
-#if defined(CONFIG_SOC_MIMXRT1189_CM7)
 #include <zephyr/cache.h>
-#elif defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
-#include <fsl_cache.h>
-#endif
 #include <fsl_clock.h>
 #include <fsl_gpc.h>
 #include <fsl_pmu.h>
@@ -631,13 +627,8 @@ void soc_early_init_hook(void)
 	trdc_enable_all_access();
 
 	/* Enable data cache */
-#if defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
-	XCACHE_EnableCache(XCACHE_PC);
-	XCACHE_EnableCache(XCACHE_PS);
-#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
-	sys_cache_instr_enable();
 	sys_cache_data_enable();
-#endif
+
 	__ISB();
 	__DSB();
 }

west.yml

@@ -203,7 +203,7 @@ manifest:
       groups:
         - hal
     - name: hal_nxp
-      revision: 7d1c7954df3c7fe758ae6f7482bffde0d910921f
+      revision: c15dd51d7af27593e38b65b1443a350e9d2de64f
       path: modules/hal/nxp
       groups:
         - hal