From e7db2faefeb56051872153521876ac04b4699ba2 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 10 Jan 2025 11:00:57 -0600 Subject: [PATCH 1/3] drivers: cache: Cache driver for NXP XCACHE controller Some NXP SoC's have External cache that is managed by the XCACHE cache controller. Signed-off-by: Mahesh Mahadevan --- drivers/cache/CMakeLists.txt | 1 + drivers/cache/Kconfig | 1 + drivers/cache/Kconfig.nxp_xcache | 10 +++ drivers/cache/cache_nxp_xcache.c | 125 +++++++++++++++++++++++++++++++ modules/Kconfig.mcux | 5 ++ 5 files changed, 142 insertions(+) create mode 100644 drivers/cache/Kconfig.nxp_xcache create mode 100644 drivers/cache/cache_nxp_xcache.c diff --git a/drivers/cache/CMakeLists.txt b/drivers/cache/CMakeLists.txt index a10d98ce68fe..74c3b983026f 100644 --- a/drivers/cache/CMakeLists.txt +++ b/drivers/cache/CMakeLists.txt @@ -9,3 +9,4 @@ zephyr_library_sources_ifdef(CONFIG_CACHE_ASPEED cache_aspeed.c) zephyr_library_sources_ifdef(CONFIG_CACHE_ANDES cache_andes.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE cache_handlers.c) zephyr_library_sources_ifdef(CONFIG_CACHE_NRF_CACHE cache_nrf.c) +zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_XCACHE cache_nxp_xcache.c) diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index be3fc2ce1936..8bae7f352024 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -21,5 +21,6 @@ comment "Device Drivers" source "drivers/cache/Kconfig.aspeed" source "drivers/cache/Kconfig.nrf" source "drivers/cache/Kconfig.andes" +source "drivers/cache/Kconfig.nxp_xcache" endif # CACHE diff --git a/drivers/cache/Kconfig.nxp_xcache b/drivers/cache/Kconfig.nxp_xcache new file mode 100644 index 000000000000..f9844793e307 --- /dev/null +++ b/drivers/cache/Kconfig.nxp_xcache @@ -0,0 +1,10 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config CACHE_NXP_XCACHE + bool "NXP external cache driver for xcache controller" + default y + select CACHE_HAS_DRIVER + depends on HAS_MCUX_XCACHE + help + This option enables the XCACHE driver for NXP SOC's. diff --git a/drivers/cache/cache_nxp_xcache.c b/drivers/cache/cache_nxp_xcache.c new file mode 100644 index 000000000000..59dd7ce2af6b --- /dev/null +++ b/drivers/cache/cache_nxp_xcache.c @@ -0,0 +1,125 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(cache_nxp_xcache, CONFIG_CACHE_LOG_LEVEL); + +#if !defined(NXP_XCACHE_INSTR) +#define NXP_XCACHE_INSTR XCACHE_PC +#endif + +#if !defined(NXP_XCACHE_DATA) +#define NXP_XCACHE_DATA XCACHE_PS +#endif + +void cache_data_enable(void) +{ + XCACHE_EnableCache(NXP_XCACHE_DATA); +} + +void cache_data_disable(void) +{ + XCACHE_DisableCache(NXP_XCACHE_DATA); +} + +int cache_data_flush_all(void) +{ + XCACHE_CleanCache(NXP_XCACHE_DATA); + + return 0; +} + +int cache_data_invd_all(void) +{ + XCACHE_InvalidateCache(NXP_XCACHE_DATA); + + return 0; +} + +int cache_data_flush_and_invd_all(void) +{ + XCACHE_CleanInvalidateCache(NXP_XCACHE_DATA); + + return 0; +} + +int cache_data_flush_range(void *addr, size_t size) +{ + XCACHE_CleanCacheByRange((uint32_t)addr, size); + + return 0; +} + +int cache_data_invd_range(void *addr, size_t size) +{ + XCACHE_InvalidateCacheByRange((uint32_t)addr, size); + + return 0; +} + +int cache_data_flush_and_invd_range(void *addr, size_t size) +{ + XCACHE_CleanInvalidateCacheByRange((uint32_t)addr, size); + + return 0; +} + +void cache_instr_enable(void) +{ + XCACHE_EnableCache(NXP_XCACHE_INSTR); +} + +void cache_instr_disable(void) +{ + XCACHE_DisableCache(NXP_XCACHE_INSTR); +} + +int cache_instr_flush_all(void) +{ + XCACHE_CleanCache(NXP_XCACHE_INSTR); + + return 0; +} + +int cache_instr_invd_all(void) +{ + XCACHE_InvalidateCache(NXP_XCACHE_INSTR); + + return 0; +} + +int cache_instr_flush_and_invd_all(void) +{ + XCACHE_CleanInvalidateCache(NXP_XCACHE_INSTR); + + return 0; +} + +int cache_instr_flush_range(void *addr, size_t size) +{ + XCACHE_CleanCacheByRange((uint32_t)addr, size); + + return 0; +} + +int cache_instr_invd_range(void *addr, size_t size) +{ + XCACHE_InvalidateCacheByRange((uint32_t)addr, size); + + return 0; +} + +int cache_instr_flush_and_invd_range(void *addr, size_t size) +{ + XCACHE_CleanInvalidateCacheByRange((uint32_t)addr, size); + + return 0; +} diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index 47cb9743eb81..d7416b08925f 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -364,6 +364,11 @@ config HAS_MCUX_XBARA help Set if the XBARA module is present on the SoC. +config HAS_MCUX_XCACHE + bool + help + Set if the XCACHE module is present on the SoC. + config HAS_NXP_MONOLITHIC_NBU bool help From 579deb8d24687d0f1eb7d9bb9dd692a50113005a Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 10 Jan 2025 11:27:39 -0600 Subject: [PATCH 2/3] west.yml: Update NXP HAL to use the new XCACHE Kconfig This Kconfig is used to pull in the XCACHE SDK driver Signed-off-by: Mahesh Mahadevan --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index b8def9e4aa0d..2317ec1313bf 100644 --- a/west.yml +++ b/west.yml @@ -203,7 +203,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 7d1c7954df3c7fe758ae6f7482bffde0d910921f + revision: c15dd51d7af27593e38b65b1443a350e9d2de64f path: modules/hal/nxp groups: - hal From d4c3cd1362a884441a90f4f559ca07d64ba2cc0f Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 10 Jan 2025 11:04:17 -0600 Subject: [PATCH 3/3] soc: imxrt118x: Use the External Cache driver for CM33 The CM33 has a XCACHE controller to manage the External cache. Remove unused Kconfigs as we can use Zephyr API's to manage the CM33 cache, Signed-off-by: Mahesh Mahadevan --- soc/nxp/imxrt/imxrt118x/Kconfig | 10 ++-------- soc/nxp/imxrt/imxrt118x/Kconfig.defconfig | 4 ++++ soc/nxp/imxrt/imxrt118x/soc.c | 11 +---------- 3 files changed, 7 insertions(+), 18 deletions(-) diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig b/soc/nxp/imxrt/imxrt118x/Kconfig index 02ba54e0754a..deafbe55ab8d 100644 --- a/soc/nxp/imxrt/imxrt118x/Kconfig +++ b/soc/nxp/imxrt/imxrt118x/Kconfig @@ -28,6 +28,8 @@ config SOC_SERIES_IMXRT118X config SOC_MIMXRT1189_CM33 select CPU_CORTEX_M33 + select HAS_MCUX_XCACHE + select CACHE_MANAGEMENT config SOC_MIMXRT1189_CM7 select CPU_CORTEX_M7 @@ -66,12 +68,4 @@ config S3MU_MCUX_S3MU default y bool "Use S3MU MCUX Driver" -config IMXRT118X_CM33_XCACHE_PS - bool "Use CM33 XCACHE_PS" - default y if SOC_MIMXRT1189_CM33 - help - Use CM33 XCACHE_PS at boot. Please note XCACHE_PC have been - enabled in SystemInit function. If this Kconfig is cleared, - the XCACHE controller won't be enabled during SOC init - endif # SOC_SERIES_IMXRT118X diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig b/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig index ee930543c9b1..74f22955c68d 100644 --- a/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig +++ b/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig @@ -34,4 +34,8 @@ config NXP_IMXRT_BOOT_HEADER endif # SECOND_CORE_MCUX +choice CACHE_TYPE + default EXTERNAL_CACHE if SOC_MIMXRT1189_CM33 +endchoice + endif # SOC_SERIES_IMXRT118X diff --git a/soc/nxp/imxrt/imxrt118x/soc.c b/soc/nxp/imxrt/imxrt118x/soc.c index cdcc8306e41e..4705c54795a1 100644 --- a/soc/nxp/imxrt/imxrt118x/soc.c +++ b/soc/nxp/imxrt/imxrt118x/soc.c @@ -10,11 +10,7 @@ #include #include #include -#if defined(CONFIG_SOC_MIMXRT1189_CM7) #include -#elif defined(CONFIG_IMXRT118X_CM33_XCACHE_PS) -#include -#endif #include #include #include @@ -631,13 +627,8 @@ void soc_early_init_hook(void) trdc_enable_all_access(); /* Enable data cache */ -#if defined(CONFIG_IMXRT118X_CM33_XCACHE_PS) - XCACHE_EnableCache(XCACHE_PC); - XCACHE_EnableCache(XCACHE_PS); -#elif defined(CONFIG_SOC_MIMXRT1189_CM7) - sys_cache_instr_enable(); sys_cache_data_enable(); -#endif + __ISB(); __DSB(); }