Add SPI driver support for Renesas RZ/G3S

boards/renesas/rzg3s_smarc/doc/index.rst

@@ -67,6 +67,8 @@ and the following hardware features:
 +-----------+------------+-------------------------------------+
 | UART      | on-chip    | serial                              |
 +-----------+------------+-------------------------------------+
+| SPI       | on-chip    | spi                                 |
++-----------+------------+-------------------------------------+
 
 Other hardware features are currently not supported by the port.
 

boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi

@@ -35,4 +35,13 @@
 				 <RZG_PINMUX(PORT_15, 2, 6)>; /* TXD */
 		};
 	};
+
+	/omit-if-no-ref/ spi0_pins: spi0 {
+		spi0-pinmux {
+			pinmux = <RZG_PINMUX(PORT_15, 0, 1)>, /* CK */
+				 <RZG_PINMUX(PORT_15, 1, 1)>, /* MOSI */
+				 <RZG_PINMUX(PORT_15, 2, 1)>, /* MISO */
+				 <RZG_PINMUX(PORT_15, 3, 1)>; /* SSL */
+		};
+	};
 };

boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts

@@ -90,3 +90,9 @@
 &gpio18{
 	status = "okay";
 };
+
+&spi0{
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};

boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml

@@ -8,3 +8,4 @@ toolchain:
 supported:
   - uart
   - gpio
+  - spi

drivers/spi/CMakeLists.txt

@@ -50,6 +50,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_PW spi_pw.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_RENESAS_RA spi_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_RENESAS_RA8 spi_b_renesas_ra8.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_RENESAS_RZ_RSPI spi_renesas_rz_rspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_RPI_PICO_PIO spi_rpi_pico_pio.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_RV32M1_LPSPI spi_rv32m1_lpspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_SAM spi_sam.c)

drivers/spi/Kconfig

@@ -109,6 +109,7 @@ source "drivers/spi/Kconfig.psoc6"
 source "drivers/spi/Kconfig.pw"
 source "drivers/spi/Kconfig.renesas_ra"
 source "drivers/spi/Kconfig.renesas_ra8"
+source "drivers/spi/Kconfig.renesas_rz"
 source "drivers/spi/Kconfig.rpi_pico"
 source "drivers/spi/Kconfig.rv32m1_lpspi"
 source "drivers/spi/Kconfig.sam"

drivers/spi/Kconfig.renesas_rz

@@ -0,0 +1,30 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SPI_RENESAS_RZ_RSPI
+	bool "Renesas RZ RSPI SPI"
+	default y
+	depends on DT_HAS_RENESAS_RZ_RSPI_SPI_ENABLED
+	select USE_RZ_FSP_RSPI_SPI
+	select PINCTRL
+	select USE_RZ_FSP_DMA if SPI_ASYNC
+	help
+	  Enable Renesas RZ RSPI SPI Driver.
+
+if SPI_RTIO
+config SPI_RENESAS_RZ_RTIO_SQ_SIZE
+	int "Number of available submission queue entries"
+	default 8 # Sensible default that covers most common spi transactions
+	help
+	  When RTIO is use with SPI each driver holds a context with which blocking
+	  API calls use to perform SPI transactions. This queue needs to be as deep
+	  as the longest set of spi_buf_sets used, where normal SPI operations are
+	  used (equal length buffers). It may need to be slightly deeper where the
+	  spi buffer sets for transmit/receive are not always matched equally in
+	  length as these are transformed into normal transceives.
+
+config SPI_RENESAS_RZ_RTIO_CQ_SIZE
+	int "Number of available completion queue entries"
+	default 8 # Sensible default that covers most common spi transactions
+
+endif # SPI_RTIO