boards:khadas: adding support for the edge2

boards/khadas/edge2/Kconfig.khadas_edge2

@@ -0,0 +1,5 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_KHADAS_EDGE2
+	select SOC_RK3588S

boards/khadas/edge2/board.yml

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+board:
+  name: khadas_edge2
+  full_name: Edge2
+  vendor: khadas
+  socs:
+  - name: rk3588s

boards/khadas/edge2/doc/index.rst

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+.. zephyr:board:: khadas_edge2
+
+Overview
+********
+
+See `Product page`_
+
+.. _Product page: https://www.khadas.com/edge2
+
+Hardware
+********
+
+See `Hardware details`_
+
+.. _Hardware details: https://docs.khadas.com/products/sbc/edge2/hardware/start
+
+Supported Features
+==================
+
+The ``khadas_edge2`` board target supports the following
+hardware features:
+
++-----------+------------+--------------------------------------+
+| Interface | Controller | Driver/Component                     |
++===========+============+======================================+
+| GIC-600   | on-chip    | GICv3 interrupt controller           |
++-----------+------------+--------------------------------------+
+| ARM TIMER | on-chip    | System Clock                         |
++-----------+------------+--------------------------------------+
+| UART      | on-chip    | Synopsys DesignWare 8250 serial port |
++-----------+------------+--------------------------------------+
+
+Other hardware features have not been enabled yet for this board.
+
+The default configuration can be found in (NON-SMP)
+:zephyr_file:`boards/khadas/edge2/khadas_edge2_defconfig`
+
+There are multiple serial ports on the board: Zephyr is using
+uart2 as serial console.
+
+Programming and Debugging
+*************************
+
+Use the following configuration to run basic Zephyr applications and
+kernel tests on Khadas Edge2 board. For example, with the :zephyr:code-sample:`hello_world`:
+
+1. Non-SMP mode
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :host-os: unix
+   :board: khadas_edge2
+   :goals: build
+
+This will build an image with the hello world sample app.
+
+Build the zephyr image:
+
+.. code-block:: console
+
+   mkimage -C none -A arm64 -O linux -a 0x10000000 -e 0x10000000 -d build/zephyr/zephyr.bin build/zephyr/zephyr.img
+
+Burn the image on the board (we choose to use Rockchip burning tool `rkdeveloptool <https://github.com/rockchip-linux/rkdeveloptool.git>`_, you will need a `SPL <http://dl.khadas.com/products/edge2/firmware/boot/>`_ which is provided by khadas:
+
+.. code-block:: console
+
+   rkdeveloptool db rk3588_spl_loader_*; rkdeveloptool wl 0x100000 zephyr.img; rkdeveloptool rd
+
+The sector 0x100000 was chosen arbitrarily (far away from U-Boot image)
+
+Use U-Boot to load and run Zephyr:
+
+.. code-block:: console
+
+   mmc read ${pxefile_addr_r} 0x100000 0x1000; bootm start ${pxefile_addr_r}; bootm loados; bootm go
+
+0x1000 is the size (in number of sectors) or your image. Increase it if needed.
+
+It will display the following console output:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build XXXXXXXXXXXX  ***
+   Hello World! khadas_edge2
+
+Flashing
+========
+
+Zephyr image can be loaded in DDR memory at address 0x10000000 from SD Card,
+EMMC, QSPI Flash or downloaded from network in uboot.
+
+References
+==========
+
+`Edge2 Documentation`_
+
+.. _Edge2 Documentation: https://docs.khadas.com/products/sbc/edge2/start

boards/khadas/edge2/khadas_edge2.dts

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+/*
+ * Copyright 2024 Université Gustave Eiffel
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <rockchip/rk3588s.dtsi>
+
+/ {
+	model = "Khadas Edge2";
+	compatible = "khadas,edge2";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+	};
+
+	cpus {
+		/delete-node/ cpu@1;
+		/delete-node/ cpu@2;
+		/delete-node/ cpu@3;
+		/delete-node/ cpu@4;
+		/delete-node/ cpu@5;
+		/delete-node/ cpu@6;
+		/delete-node/ cpu@7;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};

boards/khadas/edge2/khadas_edge2.yaml

@@ -0,0 +1,9 @@
+identifier: khadas_edge2
+name: Khadas Edge2 (single core, non SMP)
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 8192
+vendor: khadas

boards/khadas/edge2/khadas_edge2_defconfig

@@ -0,0 +1,17 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_ARM64_VA_BITS_40=y
+CONFIG_ARM64_PA_BITS_40=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=24000000
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_ARMV8_A_NS=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

dts/arm64/rockchip/rk3588s.dtsi

@@ -0,0 +1,96 @@
+/*
+ * Copyright 2024 Université Gustave Eiffel
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <mem.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+		};
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+		};
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+		};
+		cpu@4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x400>;
+		};
+		cpu@5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x500>;
+		};
+		cpu@6 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x600>;
+		};
+		cpu@7 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x700>;
+		};
+	};
+
+	gic: interrupt-controller@fe600000  {
+		#address-cells = <1>;
+		compatible = "arm,gic-v3", "arm,gic";
+		reg = <0xfe600000 0x10000>, /* GICD */
+		      <0xfe680000 0x100000>; /* GICR */
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		status = "okay";
+	};
+
+	sram0: memory@10000000 {
+		reg = <0x10000000 DT_SIZE_M(128)>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+	};
+
+	uart2: serial@feb50000  {
+		compatible = "rockchip,rk3588s-uart", "ns16550";
+		reg = <0xfeb50000 0x1000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		status = "disabled";
+		reg-shift = <2>;
+		clock-frequency = <350000000>;
+	};
+};

soc/rockchip/rk35/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_RK3568)
+  add_subdirectory(rk3568)
+elseif(CONFIG_SOC_RK3588S)
+  add_subdirectory(rk3588s)
+endif()

soc/rockchip/rk35/Kconfig

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+#
+# Copyright 2021 Huawei France Technologies SASU
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_FAMILY_ROCKCHIP
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_ROCKCHIP

soc/rockchip/rk35/Kconfig.defconfig

@@ -0,0 +1,11 @@
+#
+# Copyright 2021 Huawei France Technologies SASU
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_FAMILY_ROCKCHIP
+
+rsource "*/Kconfig.defconfig"
+
+endif

soc/rockchip/rk35/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RK35
+	bool
+	select SOC_FAMILY_ROCKCHIP
+
+config SOC_SERIES
+	default "rk35" if SOC_SERIES_RK35
+
+rsource "*/Kconfig.soc"

soc/rockchip/rk3568/Kconfig → soc/rockchip/rk35/rk3568/Kconfig

@@ -2,10 +2,10 @@
 # Copyright 2022 openEuler SIG-Zephyr
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_RK3568
+config SOC_RK3568
 	select ARM64
 	select CPU_CORTEX_A55
 	select ARM_ARCH_TIMER
 
 config SOC_PART_NUMBER
-	default "RK3568" if SOC_SERIES_RK3568
+	default "RK3568" if SOC_RK3568

soc/rockchip/rk3568/Kconfig.defconfig → soc/rockchip/rk35/rk3568/Kconfig.defconfig

@@ -2,7 +2,7 @@
 # Copyright 2022 openEuler SIG-Zephyr
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_RK3568
+if SOC_RK3568
 
 rsource "Kconfig.defconfig.rk3568"
 

soc/rockchip/rk3568/Kconfig.soc → soc/rockchip/rk35/rk3568/Kconfig.soc

@@ -2,16 +2,9 @@
 # Copyright 2022 openEuler SIG-Zephyr
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_RK3568
-	bool
-	select SOC_FAMILY_ROCKCHIP
-
 config SOC_RK3568
 	bool
-	select SOC_SERIES_RK3568
+	select SOC_SERIES_RK35
 
 config SOC
 	default "rk3568" if SOC_RK3568
-
-config SOC_SERIES
-	default "rk3568" if SOC_RK3568

soc/rockchip/rk35/rk3588s/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/rockchip/rk35/rk3588s/Kconfig

@@ -0,0 +1,10 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RK3588S
+	select ARM64
+	select CPU_CORTEX_A55
+	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
+
+config SOC_PART_NUMBER
+	default "RK3588S" if SOC_RK3588S

soc/rockchip/rk35/rk3588s/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_RK3588S
+
+rsource "Kconfig.defconfig.rk3588s"
+
+endif # SOC_RK3588S