diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig b/soc/nxp/imxrt/imxrt118x/Kconfig
index 02ba54e0754a..deafbe55ab8d 100644
--- a/soc/nxp/imxrt/imxrt118x/Kconfig
+++ b/soc/nxp/imxrt/imxrt118x/Kconfig
@@ -28,6 +28,8 @@ config SOC_SERIES_IMXRT118X
 
 config SOC_MIMXRT1189_CM33
 	select CPU_CORTEX_M33
+	select HAS_MCUX_XCACHE
+	select CACHE_MANAGEMENT
 
 config SOC_MIMXRT1189_CM7
 	select CPU_CORTEX_M7
@@ -66,12 +68,4 @@ config S3MU_MCUX_S3MU
 	default y
 	bool "Use S3MU MCUX Driver"
 
-config IMXRT118X_CM33_XCACHE_PS
-	bool "Use CM33 XCACHE_PS"
-	default y if SOC_MIMXRT1189_CM33
-	help
-	  Use CM33 XCACHE_PS at boot. Please note XCACHE_PC have been
-	  enabled in SystemInit function. If this Kconfig is cleared,
-	  the XCACHE controller won't be enabled during SOC init
-
 endif # SOC_SERIES_IMXRT118X
diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig b/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig
index ee930543c9b1..74f22955c68d 100644
--- a/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig
+++ b/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig
@@ -34,4 +34,8 @@ config NXP_IMXRT_BOOT_HEADER
 
 endif # SECOND_CORE_MCUX
 
+choice CACHE_TYPE
+	default EXTERNAL_CACHE if SOC_MIMXRT1189_CM33
+endchoice
+
 endif # SOC_SERIES_IMXRT118X
diff --git a/soc/nxp/imxrt/imxrt118x/soc.c b/soc/nxp/imxrt/imxrt118x/soc.c
index cdcc8306e41e..4705c54795a1 100644
--- a/soc/nxp/imxrt/imxrt118x/soc.c
+++ b/soc/nxp/imxrt/imxrt118x/soc.c
@@ -10,11 +10,7 @@
 #include <soc.h>
 #include <zephyr/linker/sections.h>
 #include <zephyr/linker/linker-defs.h>
-#if defined(CONFIG_SOC_MIMXRT1189_CM7)
 #include <zephyr/cache.h>
-#elif defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
-#include <fsl_cache.h>
-#endif
 #include <fsl_clock.h>
 #include <fsl_gpc.h>
 #include <fsl_pmu.h>
@@ -631,13 +627,8 @@ void soc_early_init_hook(void)
 	trdc_enable_all_access();
 
 	/* Enable data cache */
-#if defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
-	XCACHE_EnableCache(XCACHE_PC);
-	XCACHE_EnableCache(XCACHE_PS);
-#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
-	sys_cache_instr_enable();
 	sys_cache_data_enable();
-#endif
+
 	__ISB();
 	__DSB();
 }