From 9bfe6efbb5ad7c1d7a7567660c0ba7caaf3ff972 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Tue, 21 Nov 2023 15:51:42 +0800 Subject: [PATCH] arch: common: multilevel irq: verify interrupt level bits configuration Add `BUILD_ASSERT`s to make sure that the interrupt bits allocated to each levels are enough to cover the number of IRQs in each respective level. Signed-off-by: Yong Cong Sin --- arch/common/multilevel_irq.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/common/multilevel_irq.c b/arch/common/multilevel_irq.c index c55362cfa1fa..53f8e03a4d84 100644 --- a/arch/common/multilevel_irq.c +++ b/arch/common/multilevel_irq.c @@ -11,6 +11,10 @@ #include #include +BUILD_ASSERT((CONFIG_NUM_2ND_LEVEL_AGGREGATORS * CONFIG_MAX_IRQ_PER_AGGREGATOR) <= + BIT(CONFIG_2ND_LEVEL_INTERRUPT_BITS), + "L2 bits not enough to cover the number of L2 IRQs"); + /* * Insert code if the node_id is an interrupt controller */ @@ -58,6 +62,10 @@ const struct _irq_parent_entry _lvl2_irq_list[CONFIG_NUM_2ND_LEVEL_AGGREGATORS] #ifdef CONFIG_3RD_LEVEL_INTERRUPTS +BUILD_ASSERT((CONFIG_NUM_3RD_LEVEL_AGGREGATORS * CONFIG_MAX_IRQ_PER_AGGREGATOR) <= + BIT(CONFIG_3RD_LEVEL_INTERRUPT_BITS), + "L3 bits not enough to cover the number of L3 IRQs"); + #define CAT_3RD_LVL_LIST(i, base) \ INIT_IRQ_PARENT_OFFSET(INTC_DT_IRQN_GET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET), \ CONFIG_3RD_LVL_INTR_0##i##_OFFSET, IRQ_INDEX_TO_OFFSET(i, base))