Documentation: Update documenation for Infineon boards

-Update formatting and contents of index.rst for cy8ckit_062s4 -Update formatting and contents of index.rst for cy8ckit_064s0s2_4343w -Update formatting and contents of index.rst for cy8cproto_062_4343w -Update formatting and contents of index.rst for cy8cproto_063_ble -Update formatting and contents of index.rst for xmc45_relax_kit -Update formatting and contents of index.rst for xmc47_relax_kit -Change all instances of "PSoC" to "PSOC" for infineon platforms Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
zephyrproject-rtos · Nov 15, 2024 · 2fe4a37 · 2fe4a37
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diff --git a/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble b/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble
@@ -1,4 +1,4 @@
-# PSoC6 BLE Pioneer Kit configuration
+# PSOC 6 BLE Pioneer Kit configuration
 
 # Copyright (c) 2018 Cypress
 # Copyright (c) 2020 ATL Electronics

diff --git a/boards/cypress/cy8ckit_062_ble/board.yml b/boards/cypress/cy8ckit_062_ble/board.yml
@@ -1,6 +1,6 @@
 board:
   name: cy8ckit_062_ble
-  full_name: PSoC63 BLE Pioneer Kit
+  full_name: PSOC 63 BLE Pioneer Kit
   vendor: cypress
   revision:
     format: "major.minor.patch"

diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts
@@ -11,7 +11,7 @@
 #include "cy8ckit_062_ble_common.dtsi"
 
 / {
-	model = "Cypress PSoC6 BLE Pioneer Kit";
+	model = "Cypress PSOC 6 BLE Pioneer Kit";
 	compatible = "cypress,cy8c6xx7_cm0p", "cypress,psoc6";
 
 	chosen {

diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml
@@ -6,7 +6,7 @@
 #
 
 identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m0
-name: Cypress PSoC6 BLE Pioneer Kit (M0, rev. 0.0.0)
+name: Cypress PSOC 6 BLE Pioneer Kit (M0, rev. 0.0.0)
 type: mcu
 arch: arm
 ram: 288

diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml
@@ -6,7 +6,7 @@
 #
 
 identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m0
-name: Cypress PSoC6 BLE Pioneer Kit (M0, rev. 1.0.0)
+name: Cypress PSOC 6 BLE Pioneer Kit (M0, rev. 1.0.0)
 type: mcu
 arch: arm
 ram: 288

diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts
@@ -12,7 +12,7 @@
 #include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi"
 
 / {
-	model = "Cypress PSoC6 BLE Pioneer Kit";
+	model = "Cypress PSOC 6 BLE Pioneer Kit";
 	compatible = "cypress,cy8c6xx7_cm4", "cypress,psoc6";
 
 	aliases {

diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml
@@ -6,7 +6,7 @@
 #
 
 identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m4
-name: Cypress PSoC6 BLE Pioneer Kit (M4, rev. 0.0.0)
+name: Cypress PSOC 6 BLE Pioneer Kit (M4, rev. 0.0.0)
 type: mcu
 arch: arm
 ram: 288

diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml
@@ -6,7 +6,7 @@
 #
 
 identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m4
-name: Cypress PSoC6 BLE Pioneer Kit (M4, rev. 1.0.0)
+name: Cypress PSOC 6 BLE Pioneer Kit (M4, rev. 1.0.0)
 type: mcu
 arch: arm
 ram: 288

diff --git a/boards/cypress/cy8ckit_062_ble/doc/index.rst b/boards/cypress/cy8ckit_062_ble/doc/index.rst
@@ -1,21 +1,21 @@
 .. _cy8ckit_062_ble:
 
-INFINEON PSoC63 BLE Pioneer Kit
-###############################
+INFINEON PSOC 63 BLE Pioneer Kit
+################################
 
 Overview
 ********
 
-The PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that
-enables design and debug of the Cypress PSoC 63 BLE MCU.
+The PSOC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that
+enables design and debug of the Cypress PSOC 63 BLE MCU.
 
-The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-core MCU, with a
+The PSOC 6 BLE Pioneer Kit features the PSOC 63 MCU: a dual-core MCU, with a
 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm
 Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM,
 an integrated BLE 4.2 radio, 78 GPIO, 7 programmable analog blocks, 12
 programmable digital blocks, and capacitive-sensing with CapSense.
 
-The PSoC 6 BLE Pioneer board offers compatibility with Arduino shields, a
+The PSOC 6 BLE Pioneer board offers compatibility with Arduino shields, a
 512-Mb NOR flash, onboard programmer/debugger (KitProg2), USB Type-C power
 delivery system (EZ-PD™ CCG3), 5-segment CapSense slider, two CapSense
 buttons, one CapSense proximity sensing header, an RGB LED, two user LEDs,
@@ -42,45 +42,45 @@ enables the CM4 core.
 6. KitProg2 I/O header (J6)1
 7. KitProg2 programming/custom application header (J7)1
 8. External power supply connector (J9)
-9. PSoC 6 BLE user button (SW2)
+9. PSOC 6 BLE user button (SW2)
 10. KitProg2 application selection button (SW4)
 11. Digilent® Pmod™ compatible I/O header (J14)1
 12. Power LED (LED4)
 13. KitProg2 status LEDs (LED1, LED2, and LED3)
-14. PSoC 6 reset button (SW1)
-15. PSoC 6 I/O header (J18, J19 and J20)
+14. PSOC 6 reset button (SW1)
+15. PSOC 6 I/O header (J18, J19 and J20)
 16. Arduino™ Uno R3 compatible power header (J1)
-17. PSoC 6 debug and trace header (J12)
-18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4)
-19. PSoC 6 program and debug header (J11)
+17. PSOC 6 debug and trace header (J12)
+18. Arduino Uno R3 compatible PSOC 6 I/O header (J2, J3 and J4)
+19. PSOC 6 program and debug header (J11)
 20. KitProg2 programming target selection switch (SW6)
 21. CapSense slider and buttons
 22. CapSense proximity header (J13)
-23. PSoC 6 BLE VDD selection switch (SW5)
-24. PSoC 6 BLE power monitoring jumper (J8)2
+23. PSOC 6 BLE VDD selection switch (SW5)
+24. PSOC 6 BLE power monitoring jumper (J8)2
 25. Arduino Uno R3 compatible ICSP header (J5)1
-26. PSoC 6 user LEDs (LED8 and LED9)
+26. PSOC 6 user LEDs (LED8 and LED9)
 27. RGB LED (LED5)
 28. Cypress  512-Mbit  serial  NOR  Flash  memory  (S25FL512S, U4)
 29. Cypress serial Ferroelectric RAM (U5)1
 30. VBACKUP and PMIC control selection switch (SW7)2
-31. Cypress PSoC 6 BLE (CY8C6347BZI-BLD53, U1)
+31. Cypress PSOC 6 BLE (CY8C6347BZI-BLD53, U1)
 32. BLE Antenna
 33. U.FL connector for external antenna (J17)1
 34. Cypress main voltage regulator (MB39C022G, U6)
-35. KitProg2  (PSoC  5LP)  programmer  and  debugger(CY8C5868LTI-LP039, U2)
+35. KitProg2  (PSOC  5LP)  programmer  and  debugger(CY8C5868LTI-LP039, U2)
 36. Battery connector (J15)1,2
 37. USB PD output voltage (9V/12V) connector (J16)
 
 Hardware
 ********
 
-For more information about the PSoC 63 BLE MCU SoC and CY8CKIT-062-BLE board:
+For more information about the PSOC 63 BLE MCU SoC and CY8CKIT-062-BLE board:
 
-- `PSoC 63 BLE MCU SoC Website`_
-- `PSoC 63 BLE MCU Datasheet`_
-- `PSoC 63 BLE MCU Architecture Reference Manual`_
-- `PSoC 63 BLE MCU Register Reference Manual`_
+- `PSOC 63 BLE MCU SoC Website`_
+- `PSOC 63 BLE MCU Datasheet`_
+- `PSOC 63 BLE MCU Architecture Reference Manual`_
+- `PSOC 63 BLE MCU Register Reference Manual`_
 - `CY8CKIT-062-BLE Website`_
 - `CY8CKIT-062-BLE User Guide`_
 - `CY8CKIT-062-BLE Schematics`_
@@ -118,18 +118,18 @@ Cortex-M4
 System Clock
 ============
 
-The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for
+The PSOC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for
 the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the
 system clock are provided in the SOC, depending on your system requirements.
 
 Serial Port
 ===========
 
-The PSoC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as
+The PSOC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as
 UART/SPI/I2C interfaces for serial communication. At the moment UART5 on SCB5
 and UART6 on SCB6 are configured. SCB5 is connected to the onboard KitProg2's
 USB-UART Bridge working as a serial console interface. SCB6 to P13_0, P13_1
-pins on the J3 of the Arduino Uno R3 compatible PSoC6 I/O header for general
+pins on the J3 of the Arduino Uno R3 compatible PSOC 6 I/O header for general
 purposes.
 
 OpenOCD Installation
@@ -149,7 +149,7 @@ Programming and Debugging
 
 The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with
 mass storage programming to provide debugging, flash programming, and serial
-communication over USB. There are also PSoC 6 program and debug headers J11
+communication over USB. There are also PSOC 6 program and debug headers J11
 and J12 that can be used with Segger J-Link [default].
 A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and
 Cy_WDT_Disable().
@@ -285,16 +285,16 @@ References
 
 .. target-notes::
 
-.. _PSoC 63 BLE MCU SoC Website:
+.. _PSOC 63 BLE MCU SoC Website:
 	https://www.cypress.com/products/32-bit-arm-cortex-m4-cortex-m0-psoc-63-connectivity-line
 
-.. _PSoC 63 BLE MCU Datasheet:
+.. _PSOC 63 BLE MCU Datasheet:
 	https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-63-ble-datasheet-programmable-system-chip-psoc
 
-.. _PSoC 63 BLE MCU Architecture Reference Manual:
+.. _PSOC 63 BLE MCU Architecture Reference Manual:
 	https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architecture-technical-reference
 
-.. _PSoC 63 BLE MCU Register Reference Manual:
+.. _PSOC 63 BLE MCU Register Reference Manual:
 	https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-cy8c63x6-cy8c63x7-cy8c63x6-cy8c63x7-registers
 
 .. _CY8CKIT-062-BLE Website:

diff --git a/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt b/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt
@@ -1,4 +1,4 @@
-# PSoC6 WiFi-BT Pioneer Kit configuration
+# PSOC 6 WiFi-BT Pioneer Kit configuration
 
 # Copyright (c) 2018 Cypress
 # Copyright (c) 2020 ATL Electronics

diff --git a/boards/cypress/cy8ckit_062_wifi_bt/board.yml b/boards/cypress/cy8ckit_062_wifi_bt/board.yml
@@ -1,6 +1,6 @@
 board:
   name: cy8ckit_062_wifi_bt
-  full_name: PSoC6 WiFi-BT Pioneer Kit
+  full_name: PSOC 6 WiFi-BT Pioneer Kit
   vendor: cypress
   socs:
   - name: cy8c6247
diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts
@@ -12,8 +12,8 @@
 #include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi"
 
 / {
-	model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSoC6 SoC";
-	compatible = "cypress,cy8ckit_062_wifi_bt_m0", "cypress,PSoC6";
+	model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSOC 6 SoC";
+	compatible = "cypress,cy8ckit_062_wifi_bt_m0", "cypress,PSOC6";
 
 	aliases {
 		sw0 = &user_bt;

diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml
@@ -5,7 +5,7 @@
 #
 
 identifier: cy8ckit_062_wifi_bt/cy8c6247/m0
-name: Cypress PSoC6 WiFi-BT Pioneer Kit (M0)
+name: Cypress PSOC 6 WiFi-BT Pioneer Kit (M0)
 type: mcu
 arch: arm
 ram: 288

diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts
@@ -10,8 +10,8 @@
 #include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi"
 
 / {
-	model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSoC6 SoC";
-	compatible = "cypress,cy8ckit_062_wifi_bt_m4", "cypress,PSoC6";
+	model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSOC 6 SoC";
+	compatible = "cypress,cy8ckit_062_wifi_bt_m4", "cypress,PSOC6";
 
 	aliases {
 		uart-5 = &uart5;

diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml
@@ -5,7 +5,7 @@
 #
 
 identifier: cy8ckit_062_wifi_bt/cy8c6247/m4
-name: Cypress PSoC6 WiFi-BT Pioneer Kit (M4)
+name: Cypress PSOC 6 WiFi-BT Pioneer Kit (M4)
 type: mcu
 arch: arm
 ram: 288