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boards: nxp: imx95_evk_mimx9596_m7: enable SPI1 interface
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Enabled SPI1 interface for imx95_evk_mimx9596_m7.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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yangbolu1991 committed Jan 7, 2025
1 parent ac17978 commit 1c3744f
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8 changes: 8 additions & 0 deletions boards/nxp/imx95_evk/doc/index.rst
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Expand Up @@ -92,6 +92,8 @@ The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardwar
+-----------+------------+-------------------------------------+
| TPM | on-chip | tpm |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+

The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support
the following hardware features:
Expand Down Expand Up @@ -131,6 +133,12 @@ oscilloscope.
Channel 2 signal routed to resistance R881.
Channel 3 signal routed to resistance R882.

SPI
---

SPI1 on J35 is enabled for M7.
R1217/R1218/R1219/R1220 should be soldered with 0R resistances.


Programming and Debugging (A55)
*******************************
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6 changes: 6 additions & 0 deletions boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts
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Expand Up @@ -35,6 +35,12 @@
status = "okay";
};

&lpspi1 {
pinctrl-0 = <&lpspi1_default>;
pinctrl-names = "default";
status = "okay";
};

&lpuart3 {
status = "okay";
current-speed = <115200>;
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1 change: 1 addition & 0 deletions boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml
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Expand Up @@ -18,4 +18,5 @@ supported:
- uart
- i2c
- pwm
- spi
vendor: nxp
1 change: 1 addition & 0 deletions boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_defconfig
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Expand Up @@ -13,3 +13,4 @@ CONFIG_XIP=y
CONFIG_MBOX=y
CONFIG_MBOX_INIT_PRIORITY=0
CONFIG_ARM_SCMI=y
CONFIG_SPI=y

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