Add i.MX95 NETC support

mcux/hal_nxp.cmake

@@ -272,9 +272,14 @@ endif()
 if (${MCUX_DEVICE} MATCHES "MIMXRT1189")
   include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	netc/socs/imxrt1180	driver_netc_soc_imxrt1180)
   include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	msgintr			driver_msgintr)
+elseif (${MCUX_DEVICE} MATCHES "MIMX9596")
+  include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	netc/socs/imx95		driver_netc_soc_imx95)
+  include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	msgintr			driver_msgintr)
+  include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	irqsteer		driver_irqsteer)
 endif()
 
-if ((${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") AND (NOT (CONFIG_SOC_MIMXRT1166_CM4 OR CONFIG_SOC_MIMXRT1176_CM4 OR CONFIG_SOC_MIMXRT1189_CM33)))
+if (((${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") AND (NOT (CONFIG_SOC_MIMXRT1166_CM4 OR CONFIG_SOC_MIMXRT1176_CM4 OR CONFIG_SOC_MIMXRT1189_CM33))) OR
+    ((${MCUX_DEVICE} MATCHES "MIMX9596") AND CONFIG_SOC_MIMX9596_M7))
   include_driver_ifdef(CONFIG_HAS_MCUX_CACHE		cache/armv7-m7	driver_cache_armv7_m7)
 elseif((${MCUX_DEVICE} MATCHES "MIMXRT(5|6)") OR (${MCUX_DEVICE} MATCHES "RW61") OR (${MCUX_DEVICE} MATCHES "MCXN.4."))
   include_driver_ifdef(CONFIG_HAS_MCUX_CACHE		cache/cache64	driver_cache_cache64)

mcux/mcux-sdk/devices/MIMX9596/MIMX9596_cm7.h

@@ -88890,7 +88890,6 @@ typedef struct {
 
 /** ENETC_PF_TMR - Register Layout Typedef */
 typedef struct {
-  struct {                                         /* offset: 0x0, array step: 0xFC */
     __I  uint32_t TMR_ID;                            /**< Module ID, array offset: 0x0, array step: 0xFC */
          uint8_t RESERVED_0[4];
     __I  uint32_t TMR_CAPR;                          /**< Timer Capability, array offset: 0x8, array step: 0xFC */
@@ -88931,7 +88930,6 @@ typedef struct {
     __I  uint32_t TMR_CUR_TIME_L;                    /**< Timer Current Time Low, array offset: 0xF0, array step: 0xFC */
     __I  uint32_t TMR_CUR_TIME_H;                    /**< Timer Current Time High, array offset: 0xF4, array step: 0xFC */
     __IO uint32_t TMR_PARAM;                         /**< Timer Parameter, array offset: 0xF8, array step: 0xFC */
-  } ALL_REG_ARRAYS[1];
 } ENETC_PF_TMR_Type;
 
 /* ----------------------------------------------------------------------------

mcux/mcux-sdk/devices/MIMX9596/MIMX9596_cm7_features.h

@@ -619,7 +619,7 @@
 /* @brief After one or more late collision or excessive collision events, counters PMa_TOCTn and PMa_TFRMn will be higher than expected. */
 #define FSL_FEATURE_NETC_HAS_ERRATA_051710 (1)
 /* @brief MAC statistic counters TEOCT and TOCT are inaccurate after Pause frames are transmitted with flexible preamble enabled and flexible preamble count set to less than 7. */
-#define FSL_FEATURE_NETC_HAS_ERRATA_051711 (1)
+#define FSL_FEATURE_NETC_HAS_ERRATA_051711 (0)
 /* @brief Number of Switch ports. */
 #define FSL_FEATURE_NETC_SWITCH_MAX_PORT_NUMBER (5)
 /* @brief Number of Switch Ethernet MAC ports. */

mcux/mcux-sdk/devices/MIMX9596/drivers/fsl_memory.h

@@ -0,0 +1,116 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_MEMORY_H_
+#define _FSL_MEMORY_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.memory"
+#endif
+
+#if (__CORTEX_M == 33U)
+/* The CM33 subsystem local TCM start address, refer to Reference Manual for detailed information */
+#define FSL_MEM_M33_TCM_BEGIN 0x20000000U
+/* The CM33 subsystem local TCM end address, refer to Reference Manual for detailed information */
+#define FSL_MEM_M33_TCM_END 0x2003FFFFU
+
+#define FSL_MEM_M33_TCM_OFFSET 0x200000U
+#elif (__CORTEX_M == 7U)
+/* The CM7 subsystem local TCM start address, refer to Reference Manual for detailed information */
+#define FSL_MEM_M7_TCM_BEGIN 0x2000000U
+/* The CM7 subsystem local TCM end address, refer to Reference Manual for detailed information */
+#define FSL_MEM_M7_TCM_END 0x2007FFFFU
+
+#define FSL_MEM_M7_TCM_OFFSET 0x400000U
+#else
+#error "Device is not supported by this driver!"
+#endif
+
+typedef enum _mem_direction
+{
+    kMEMORY_Local2DMA = 0,
+    kMEMORY_DMA2Local,
+} mem_direction_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*!
+ * @brief Convert the memory map address.
+ *
+ * This function convert the address between system mapped address and native mapped address.
+ * There maybe offset between subsystem native address and system address for some memory,
+ * this funciton convert the address to different memory map.
+ * @param addr address need to be converted.
+ * @param direction convert direction.
+ * @return the converted address
+ */
+static inline uint32_t MEMORY_ConvertMemoryMapAddress(uint32_t addr, mem_direction_t direction)
+{
+    uint32_t dest;
+
+    switch (direction)
+    {
+        case kMEMORY_Local2DMA:
+        {
+#if (__CORTEX_M == 33U)
+            if ((addr >= FSL_MEM_M33_TCM_BEGIN) && (addr <= FSL_MEM_M33_TCM_END))
+            {
+                dest = addr + FSL_MEM_M33_TCM_OFFSET;
+            }
+#elif (__CORTEX_M == 7U)
+            if ((addr > FSL_MEM_M7_TCM_BEGIN) && (addr <= FSL_MEM_M7_TCM_END))
+            {
+                dest = addr + FSL_MEM_M7_TCM_OFFSET;
+            }
+#endif
+            else
+            {
+                dest = addr;
+            }
+            break;
+        }
+        case kMEMORY_DMA2Local:
+        {
+#if (__CORTEX_M == 33U)
+            if ((addr >= (FSL_MEM_M33_TCM_BEGIN + FSL_MEM_M33_TCM_OFFSET)) &&
+                (addr <= (FSL_MEM_M33_TCM_END + FSL_MEM_M33_TCM_OFFSET)))
+            {
+                dest = addr - FSL_MEM_M33_TCM_OFFSET;
+            }
+#elif (__CORTEX_M == 7U)
+            if ((addr >= (FSL_MEM_M7_TCM_BEGIN + FSL_MEM_M7_TCM_OFFSET)) &&
+                (addr <= (FSL_MEM_M7_TCM_END + FSL_MEM_M7_TCM_OFFSET)))
+            {
+                dest = addr - FSL_MEM_M7_TCM_OFFSET;
+            }
+#endif
+            else
+            {
+                dest = addr;
+            }
+            break;
+        }
+        default:
+            dest = addr;
+            break;
+    }
+
+    return dest;
+}
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _FSL_MEMORY_H_ */

mcux/mcux-sdk/drivers/irqsteer/fsl_irqsteer.c

@@ -21,21 +21,23 @@
  * Prototypes
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*!
  * @brief Get instance number for IRQSTEER.
  *
  * @param base IRQSTEER peripheral base address.
  */
 static uint32_t IRQSTEER_GetInstance(IRQSTEER_Type *base);
+#endif
 
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Array to map IRQSTEER instance number to base pointer. */
 static IRQSTEER_Type *const s_irqsteerBases[] = IRQSTEER_BASE_PTRS;
 
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Array to map IRQSTEER instance number to clock name. */
 static const clock_ip_name_t s_irqsteerClockName[] = IRQSTEER_CLOCKS;
 #endif
@@ -48,7 +50,7 @@ static const IRQn_Type s_irqsteerIRQNumber[] = IRQSTEER_IRQS;
 /*******************************************************************************
  * Code
  ******************************************************************************/
-
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 static uint32_t IRQSTEER_GetInstance(IRQSTEER_Type *base)
 {
     uint32_t instance;
@@ -66,6 +68,7 @@ static uint32_t IRQSTEER_GetInstance(IRQSTEER_Type *base)
 
     return instance;
 }
+#endif
 
 /*!
  * brief Initializes the IRQSTEER module.

mcux/mcux-sdk/drivers/netc/socs/imx95/fsl_netc_soc.h

@@ -36,6 +36,15 @@ typedef enum _netc_hw_eth_port_idx
     kNETC_ENETC2EthPort   = 2U, /*!< Ethernet MAC port for ENETC2 */
 } netc_hw_eth_port_idx_t;
 
+/*!
+ * @brief Enumeration for NETC timer external trigger index
+ */
+typedef enum _netc_timer_exttrig_index
+{
+    kNETC_TimerExtTrig1 = 0,
+    kNETC_TimerExtTrig2,
+} netc_timer_exttrig_index_t;
+
 /*!
  * @brief Get register map resource
  *