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add RT700 files from sdk github main branch Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,10 @@ | ||
| # Copyright 2024 NXP | ||
| # | ||
| # SPDX-License-Identifier: BSD-3-Clause | ||
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| # driver_flash_config_mimxrt700evk | ||
| config MCUX_USE_driver_flash_config_mimxrt700evk | ||
| bool "Flash config" | ||
| select MCUX_USE_driver_iap | ||
| help | ||
| flash config block |
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mcux/mcux-sdk/boards/mimxrt700evk/flash_config/driver_flash_config.cmake
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| #Description: Flash config; user_visible: True | ||
| include_guard(GLOBAL) | ||
| message("driver_flash_config component is included.") | ||
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| target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE | ||
| ${CMAKE_CURRENT_LIST_DIR}/flash_config.c | ||
| ) | ||
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| target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC | ||
| ${CMAKE_CURRENT_LIST_DIR}/. | ||
| ) | ||
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| include(driver_iap) |
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mcux/mcux-sdk/boards/mimxrt700evk/flash_config/driver_flash_config_mimxrt700evk.cmake
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,14 @@ | ||
| #Description: Flash config; user_visible: True | ||
| include_guard(GLOBAL) | ||
| message("driver_flash_config_mimxrt700evk component is included.") | ||
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| target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE | ||
| ${CMAKE_CURRENT_LIST_DIR}/flash_config.c | ||
| ) | ||
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| target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC | ||
| ${CMAKE_CURRENT_LIST_DIR}/. | ||
| ) | ||
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| include(driver_iap) |
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mcux/mcux-sdk/boards/mimxrt700evk/flash_config/flash_config.c
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| /* | ||
| * Copyright 2023 NXP | ||
| * All rights reserved. | ||
| * | ||
| * SPDXLicense-Identifier: BSD-3-Clause | ||
| */ | ||
| #include "flash_config.h" | ||
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| /* Component ID definition, used by tools. */ | ||
| #ifndef FSL_COMPONENT_ID | ||
| #define FSL_COMPONENT_ID "platform.drivers.flash_config" | ||
| #endif | ||
|
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| /******************************************************************************* | ||
| * Code | ||
| ******************************************************************************/ | ||
| #if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) | ||
| #if defined(__ARMCC_VERSION) || defined(__GNUC__) | ||
| __attribute__((section(".flash_conf"), used)) | ||
| #elif defined(__ICCARM__) | ||
| #pragma location = ".flash_conf" | ||
| #endif | ||
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| const fc_static_platform_config_t flash_config = { | ||
| .xspi_fcb_block = { | ||
| .memConfig = | ||
| { | ||
| .tag = FC_XSPI_CFG_BLK_TAG, | ||
| .version = FC_XSPI_CFG_BLK_VERSION, | ||
| .readSampleClkSrc = kXSPIReadSampleClk_ExternalInputFromDqsPad, | ||
| .csHoldTime = 3, | ||
| .csSetupTime = 3, | ||
| .deviceModeCfgEnable = 1, | ||
| .deviceModeType = 2, | ||
| .waitTimeCfgCommands = 1, | ||
| .deviceModeSeq = | ||
| { | ||
| .seqNum = 1, | ||
| .seqId = 6, /* See Lookup table for more details */ | ||
| .reserved = 0, | ||
| }, | ||
| .deviceModeArg = 2, /* Enable OPI DDR mode */ | ||
| .controllerMiscOption = | ||
| (1u << Fc_XspiMiscOffset_SafeConfigFreqEnable) | (1u << Fc_XspiMiscOffset_DdrModeEnable), | ||
| .deviceType = 1, | ||
| .sflashPadType = 8, | ||
| .serialClkFreq = Fc_XspiSerialClk_200MHz, | ||
| .sflashA1Size = 64ul * 1024u * 1024u, | ||
| .busyOffset = 0u, | ||
| .busyBitPolarity = 0u, | ||
| .lookupTable = | ||
| { | ||
| /*Read*/ | ||
| [0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0xEE, FC_CMD_DDR, FC_XSPI_8PAD, 0x11), | ||
| [1] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x12), | ||
| [2] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x2, FC_CMD_READ_DDR, FC_XSPI_8PAD, 0x4), | ||
| [3] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_STOP, FC_XSPI_8PAD, 0x0, 0, 0, 0), | ||
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| /*Read status SPI*/ | ||
| [5 * 1 + 0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x05, FC_CMD_READ_SDR, FC_XSPI_1PAD, 0x04), | ||
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| /* Read Status OPI */ | ||
| [5 * 2 + 0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x05, FC_CMD_DDR, FC_XSPI_8PAD, 0xFA), | ||
| [5 * 2 + 1] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x12), | ||
| [5 * 2 + 2] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x2, FC_CMD_READ_DDR, FC_XSPI_8PAD, 0x4), | ||
| [5 * 2 + 3] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_STOP, FC_XSPI_8PAD, 0x0, 0, 0, 0), | ||
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| /*Write enable*/ | ||
| [5 * 3 + 0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x06, FC_CMD_STOP, FC_XSPI_1PAD, 0x04), | ||
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| /* Write Enable - OPI */ | ||
| [5 * 4 + 0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x06, FC_CMD_DDR, FC_XSPI_8PAD, 0xF9), | ||
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| /* Erase Sector */ | ||
| [5 * 5 + 0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x21, FC_CMD_DDR, FC_XSPI_8PAD, 0xDE), | ||
| [5 * 5 + 1] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_STOP, FC_XSPI_8PAD, 0x0), | ||
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| /* Enable OPI DDR mode */ | ||
| [5 * 6 + 0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x72, FC_CMD_SDR, FC_XSPI_1PAD, 0x00), | ||
| [5 * 6 + 1] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x00, FC_CMD_SDR, FC_XSPI_1PAD, 0x00), | ||
| [5 * 6 + 2] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_SDR, FC_XSPI_1PAD, 0x00, FC_CMD_WRITE_SDR, FC_XSPI_1PAD, 0x01), | ||
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| /* Page program */ | ||
| [5 * 9 + 0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x12, FC_CMD_DDR, FC_XSPI_8PAD, 0xED), | ||
| [5 * 9 + 1] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_WRITE_DDR, FC_XSPI_8PAD, 0x4), | ||
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| /* Erase Chip */ | ||
| [5 * 11 + 0] = | ||
| FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x60, FC_CMD_DDR, FC_XSPI_8PAD, 0x9F), | ||
| }, | ||
| }, | ||
| .pageSize = 256u, | ||
| .sectorSize = 4u * 1024u, | ||
| .ipcmdSerialClkFreq = 1u, | ||
| .serialNorType = 2u, | ||
| .blockSize = 64u * 1024u, | ||
| .flashStateCtx = 0x07008200u, | ||
| }, | ||
| #ifdef BOOT_ENABLE_XSPI1_PSRAM | ||
| .psram_config_block = { | ||
| .xmcdHeader = 0xC0010008, | ||
| .xmcdOpt0 = 0xC0000700, | ||
| }, | ||
| #endif | ||
| }; | ||
|
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| #endif /* BOOT_HEADER_ENABLE */ |
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