diff --git a/docs/content/docs/design/flex_pcb.md b/docs/content/docs/design/flex_pcb.md index f2a6342..d8c1604 100644 --- a/docs/content/docs/design/flex_pcb.md +++ b/docs/content/docs/design/flex_pcb.md @@ -60,7 +60,7 @@ Flex PCB polyimide material comes in several varieties. Flex pcb requires handling transition of transmission line from FR4 stackup to flex PCB stackup. - Requires careful design to avoid impedance discontinuities at flex PCB connection. - Involves designing transmission line tapers to maintain impedance target across connector transition. -- [Transmission line design]({{< abs_url link="/docs/design/transmission_line" >}}) +- [Transmission line design]({{< abs_url link="docs/design/transmission_line" >}}) ### Transmission line design on flex pcb Flex pcb has a very thin dielectric core for easy bending. @@ -68,7 +68,7 @@ Flex pcb has a very thin dielectric core for easy bending. - Calculations with a solid ground plane puts trace width at < 0.05mm which is not manufacturable. - Requires using a hatched ground plane to achieve target impedance at manufacturable 0.1mm trace width. - Hatched ground plane needs very careful design considerations and is not trivial to design. -- [Hatched ground plane design]({{< abs_url link="/docs/design/hatched_ground_plane" >}}) +- [Hatched ground plane design]({{< abs_url link="docs/design/hatched_ground_plane" >}}) ### Design and manufacturing complexity Additional complexity due to multiple boards. diff --git a/docs/content/docs/design/transmission_line/flex_connection.md b/docs/content/docs/design/transmission_line/flex_connection.md index d373100..ae4c419 100644 --- a/docs/content/docs/design/transmission_line/flex_connection.md +++ b/docs/content/docs/design/transmission_line/flex_connection.md @@ -108,8 +108,8 @@ Transitioning our transmission line from an FR4 stackup to a flexible PCB stacku ### Hatched ground plane If the transmission line signal traces have the same width, using a suitably designed hatched ground plane will increase the impedance to meet our impedance target. -- See [designing hatched ground plane](/docs/design/transmission_line/hatched_ground_plane) for more details. -- See [simulating hatched ground plane](/docs/design/open_ems/hatched_ground) for more details. +- See [designing hatched ground plane]({{< abs_url link=docs/design/transmission_line/hatched_ground_plane >}}) for more details. +- See [simulating hatched ground plane]({{< abs_url link=docs/design/open_ems/hatched_ground >}}) for more details. ## Vertical transmission line connection {{< responsive_image key="jlcpcb_stackup_connection" >}} @@ -121,7 +121,7 @@ Transition from FR4 stackup to flexible PCB involves a vertical solder connectio - The E-fields between the signal traces and ground planes have to switch layers. - Broadside coupling means stronger E-fields and more energy being carried compared to the coplanar ground traces which use edge coupling. - Capacitive coupling is greater through a broadside connection since the traces are 0.1mm wide, compared to the edge side coupling which occurs over a 0.012mm or 0.035mm - - This was verified through an [open EMS simulation]({{< abs_url link="/docs/design/open_ems/" >}}). + - This was verified through an [open EMS simulation]({{< abs_url link="docs/design/open_ems/" >}}). ### Tapered connection {{< responsive_image key="flex_pcb_transmission_line_taper" >}} @@ -134,7 +134,7 @@ A taper is a gradual change in the geometry of a transmission line that attempts - Linear taper just requires the polyline tool in KiCAD. ### Parametric optimisation of taper -To verify the performance of the taper [openEMS]({{< abs_url link="/docs/design/open_ems/taper" >}}) was used. +To verify the performance of the taper [openEMS]({{< abs_url link="docs/design/open_ems/taper" >}}) was used. - Simulated stackup with flex PCB connected to FR4 transmission line as a 3 layer board. - Layers were: ```[FR4 ground, signal traces, flex PCB ground]```. - The soldered signal traces were approximated as an ideal single trace on a single layer. diff --git a/docs/content/docs/design/transmission_line/hatched_ground_plane.md b/docs/content/docs/design/transmission_line/hatched_ground_plane.md index ab07a61..fce24d3 100644 --- a/docs/content/docs/design/transmission_line/hatched_ground_plane.md +++ b/docs/content/docs/design/transmission_line/hatched_ground_plane.md @@ -18,7 +18,7 @@ params: - No easy equation to get impedance measurement (fill factor approximation does not model this adequately). - Design of hatched ground plane must meet manufacturing capabilities of JLCPCB. - Requires parametric search with simulation software. -- Refer to this section about simulating circuits with [openEMS]({{< abs_url link="/docs/design/open_ems/hatched_ground" >}}). +- Refer to this section about simulating circuits with [openEMS]({{< abs_url link="docs/design/open_ems/hatched_ground" >}}). ## Determining parameters There are three major parameters to consider: @@ -28,8 +28,8 @@ There are three major parameters to consider: Since we need to be above the minimum trace width for JLCPCB to manufacture it, we should select a fixed trace width of 0.1mm. - This is similar the trace width of 0.13mm for our transmission line on the FR4 substrate for both the M.2 cad and Oculink port board. -- This means we will have an easier time designing a taper geometry when connecting the flex connector to our boards (discussed [here]({{< abs_url link="/docs/design/transmission_line/flex_connection" >}})). +- This means we will have an easier time designing a taper geometry when connecting the flex connector to our boards (discussed [here]({{< abs_url link="docs/design/transmission_line/flex_connection" >}})). - Means we only need to perform a parametric search with two variables (the hatch width and gap) which is less time consuming. ## Additional design considerations -Refer to minimising [intra-pair skew]({{< abs_url link="/docs/design/transmission_line/skew_requirements#hatched-ground-plane" >}}) for hatched ground planes and differential pairs. +Refer to minimising [intra-pair skew]({{< abs_url link="docs/design/transmission_line/skew_requirements#hatched-ground-plane" >}}) for hatched ground planes and differential pairs. diff --git a/docs/content/docs/design/transmission_line/skew_requirements.md b/docs/content/docs/design/transmission_line/skew_requirements.md index 7fbd9f0..84c7dbe 100644 --- a/docs/content/docs/design/transmission_line/skew_requirements.md +++ b/docs/content/docs/design/transmission_line/skew_requirements.md @@ -47,7 +47,7 @@ The following are phenomena that can contribute to intra-pair skew and methods t - Here is a pdf from Isola group who are a copper clad laminate and prepreg materials manufacturer. - {{< pdf_link key="isola_group_fibre_weave_patterns" >}} - It contains various high quality images of fibre weave patterns and their fill factor measurements. - - They also include treatment processes for bonding the prepreg and core to copper layers and how that effects the copper smoothness which is relevant for [skin effect]({{< abs_url link="/docs/design/transmission_line/skin_effect" >}}). + - They also include treatment processes for bonding the prepreg and core to copper layers and how that effects the copper smoothness which is relevant for [skin effect]({{< abs_url link="docs/design/transmission_line/skin_effect" >}}). #### JLCPCB controlled impedance stackup diff --git a/docs/content/docs/design/transmission_line/structures.md b/docs/content/docs/design/transmission_line/structures.md index 063396a..14663e2 100644 --- a/docs/content/docs/design/transmission_line/structures.md +++ b/docs/content/docs/design/transmission_line/structures.md @@ -24,7 +24,7 @@ Given our tight routing requirements our PCIe lanes would be extremely close tog - Adding a ground plane to confine the electric field generated by the differential pair (almost always helps). - Adding coplanar guard traces to separate adjacent lanes and add additional E-field confinement. - Sometimes can worsen crosstalk if guard trace is high impedance and functions closer to a resonant tank than a ground trace. - - Can be improved by turning coplanar guard traces into a [via fence]({{< abs_url link="/docs/design/via_fence" >}}) by stitching them to a ground plane + - Can be improved by turning coplanar guard traces into a [via fence]({{< abs_url link="docs/design/via_fence" >}}) by stitching them to a ground plane - This guarantees coplanar guard trace is low impedance. - Also adds additional grounding with vias which further improves E-field confinement and prevents inter-lane crosstalk. diff --git a/docs/content/docs/design/transmission_line/via_jumps.md b/docs/content/docs/design/transmission_line/via_jumps.md index 9e3871b..10e0d58 100644 --- a/docs/content/docs/design/transmission_line/via_jumps.md +++ b/docs/content/docs/design/transmission_line/via_jumps.md @@ -35,7 +35,7 @@ params: - There is no closed form equation for the impedance of a coaxial via with a teardrop taper. - This means running a parametric search through a simulation to determine the optimal parameter values. - Very difficult to do given the number of parameters for the coaxial via and teardrop taper which all impact performance. -- Refer to this section about simulating circuits with [openEMS]({{< abs_url link="/docs/design/openEMS" >}}). +- Refer to this section about simulating circuits with [openEMS]({{< abs_url link="docs/design/openEMS" >}}). ## Via stubs {{< responsive_image key="sierra_express_via_stub_back_drilling" >}} diff --git a/docs/content/docs/manufacturing/electrical_testing.md b/docs/content/docs/manufacturing/electrical_testing.md index bcd1c53..fefe756 100644 --- a/docs/content/docs/manufacturing/electrical_testing.md +++ b/docs/content/docs/manufacturing/electrical_testing.md @@ -10,7 +10,7 @@ params: ## Single board validation - Oculink port has a small pitch of 0.2mm which can easily create solder bridges. - Validate this by connecting the Oculink port to the unpowered PCIe eGPU board. -- Refer to [M.2 pinout]({{< abs_url link="/docs/specifications/components/" >}}) and [PCIe pinout]({{< abs_url link="/docs/specifications/pcie_specification/" >}}) for the electrical connections to test for. +- Refer to [M.2 pinout]({{< abs_url link="docs/specifications/components/" >}}) and [PCIe pinout]({{< abs_url link="docs/specifications/pcie_specification/" >}}) for the electrical connections to test for. - Depending on the design the PCIe lanes may be connected in opposite polarity and/or in opposite orders. - Check for short circuits and bad connections. - Use a magnifying glass to position multimeter probes onto the exposed electrical contacts. diff --git a/docs/content/docs/manufacturing/reflow_soldering.md b/docs/content/docs/manufacturing/reflow_soldering.md index 304f4e4..e2596d0 100644 --- a/docs/content/docs/manufacturing/reflow_soldering.md +++ b/docs/content/docs/manufacturing/reflow_soldering.md @@ -34,7 +34,7 @@ The Mechanic IX5 can be used to follow an arbitrary reflow profile (including th 3. Place oculink port carefully onto SMD pads as to align them correctly. 4. Follow reflow profile with a target temperature of 220°C and keep it there for 60 seconds before ramping it down. 5. Visually confirm that there are no solder bridges on visible connections. -6. Validate that there are no shorts or bad connections following [electrical testing]({{< abs_url link="/docs/manufacturing/electrical_testing" >}}). +6. Validate that there are no shorts or bad connections following [electrical testing]({{< abs_url link="docs/manufacturing/electrical_testing" >}}). - Due to simple design of circuit the complications should only occur with the Oculink port itself. - Here excessive or insufficient solder paste can result in short circuits or a missing electrical connection. - Repeat steps 1 to 5 until the Oculink port is soldered correctly. @@ -71,7 +71,7 @@ This process is only required for the two part board which is connected over the - Since there are no spring contacts, the z-height tolerance of the connection is very low. - To guarantee a good electrical connection the reflow process has to occur while the pads are under compressive pressure. - Be careful not to disturb the existing connections such as the Oculink port and capacitors. -10. Perform electrical tests as described in [electrical testing]({{< abs_url link="/docs/manufacturing/electrical_testing" >}}). +10. Perform electrical tests as described in [electrical testing]({{< abs_url link="docs/manufacturing/electrical_testing" >}}). - This is done to make sure shorts don't occur due at the flexible PCB connection with the Oculink port board. - If shorts do occur at this step repeat steps 1 to 10 with less solder on the pads. - If these is a missing electrical connection make sure that sufficient pressure has been applied during reflow. diff --git a/docs/content/docs/results/discussion.md b/docs/content/docs/results/discussion.md index 8751481..281e339 100644 --- a/docs/content/docs/results/discussion.md +++ b/docs/content/docs/results/discussion.md @@ -26,12 +26,12 @@ sequenceDiagram; {{< carousel key="custom_adapters" >}}
- +
- +
{{< /carousel >}} @@ -45,12 +45,12 @@ sequenceDiagram; {{< carousel key="aliexpress_adapters" >}}
- +
- +
{{< /carousel >}} diff --git a/docs/data/images.yaml b/docs/data/images.yaml index d606d2b..ba6536c 100644 --- a/docs/data/images.yaml +++ b/docs/data/images.yaml @@ -1,206 +1,206 @@ pcie_x4_pinout: - path: "/images/diagrams/pcie_x4_pinout.png" + path: "images/diagrams/pcie_x4_pinout.png" description: "Diagram 1. PCIe x4 connector pinout" source: "https://www.adt.link/download/ADT-Cable-R42SF-specification.html" m2_connector_pinout_table: - path: "/images/diagrams/m2_connector_pinout_table.png" + path: "images/diagrams/m2_connector_pinout_table.png" description: "Table 1. M.2 connector pinout" source: "https://www.anandtech.com/show/13609/pcisig-warns-of-incompatibilities-between-m2-and-samsungs-ngsff" m2_card_size: - path: "/images/diagrams/m2_card_size.png" + path: "images/diagrams/m2_card_size.png" description: "Diagram 2. M.2 card size standards" source: "https://www.unitek-products.com/products/usb3-1-gen2-type-c-to-m-2-ssd-pcie-nvme-enclosure" amphenol_oculink_port_pinout_table: - path: "/images/diagrams/amphenol_oculink_port_pinout_table.png" + path: "images/diagrams/amphenol_oculink_port_pinout_table.png" description: "Table 2. Amphenol Oculink connector pinout" source: "https://electronics.stackexchange.com/questions/675174/oculink-connector-pin-configuration-for-root-port-and-endpoint" amphenol_oculink_port: - path: "/images/diagrams/amphenol_oculink_port.jpg" + path: "images/diagrams/amphenol_oculink_port.jpg" description: "Image 1. Amphenol oculink port" source: "https://www.amphenol-cs.com/product-series/oculink.html" adtlink_m2_to_pcie4_adapter_schematic: - path: "/images/diagrams/adtlink_m2_to_pcie4_adapter_schematic.png" + path: "images/diagrams/adtlink_m2_to_pcie4_adapter_schematic.png" description: "Image 2. Adtlink M.2 to PCIe 4.0 adapter" source: "https://www.adt.link/download/ADT-Cable-R42SF-specification.html" gpdwin1_m2_to_oculink_adapter_schematic: - path: "/images/diagrams/gpdwin1_m2_to_oculink_adapter_schematic.png" + path: "images/diagrams/gpdwin1_m2_to_oculink_adapter_schematic.png" description: "Image 3. GPD win 1 M.2 to Oculink adapter card" source: "https://gpd.hk/gpdg1firmwaredriver" adtlink_f4c_m2_to_oculink_adapter: - path: "/images/diagrams/adtlink_f4c_m2_to_oculink_adapter.png" + path: "images/diagrams/adtlink_f4c_m2_to_oculink_adapter.png" description: "Image 4. Adtlink F4C M.2 to Oculink adapter card" source: "https://www.adt.link/product/F9GV4.html" adtlink_f4c_m2_to_oculink_adapter_photo: - path: "/images/diagrams/adtlink_f4c_m2_to_oculink_adapter_photo.png" + path: "images/diagrams/adtlink_f4c_m2_to_oculink_adapter_photo.png" description: "Image 5. Purchased Adtlink F4C M.2 to Oculink adapter card with modifications" lenovo_16arp8_dimensions: - path: "/images/pictures/lenovo_16arp8_adapter_layout_prototype.png" + path: "images/pictures/lenovo_16arp8_adapter_layout_prototype.png" description: "Image 6. Measurements and prototype layout for M.2 to Oculink adapter" lenovo_16arp8_3d_model: - path: "/images/diagrams/lenovo_16arp8_3d_model.png" + path: "images/diagrams/lenovo_16arp8_3d_model.png" description: "Image 7. 3D modelling of Lenovo 16arp8 based on measurements" nfhk_vertical_m2_to_oculink_adapter: - path: "/images/diagrams/nfhk_vertical_m2_to_oculink_adapter.png" + path: "images/diagrams/nfhk_vertical_m2_to_oculink_adapter.png" description: "Image 8. NFHK vertical M.2 to Oculink adapter card" source: "https://www.aliexpress.com/item/1005007302462841.html" kicad_single_board_pcb: - path: "/images/diagrams/kicad_single_board_pcb.png" + path: "images/diagrams/kicad_single_board_pcb.png" description: "Image 9. Custom single board M.2 to Oculink adapter PCB" kicad_single_board_render: - path: "/images/diagrams/kicad_single_board_render.png" + path: "images/diagrams/kicad_single_board_render.png" description: "Image 10. Custom single board M.2 to Oculink adapter 3D render" kicad_flex_connector_pcb: - path: "/images/diagrams/kicad_flex_connector_pcb.png" + path: "images/diagrams/kicad_flex_connector_pcb.png" description: "Image 11. Custom M.2 to Oculink adapter with flex connector PCBs" kicad_flex_connector_render: - path: "/images/diagrams/kicad_flex_connector_render.png" + path: "images/diagrams/kicad_flex_connector_render.png" description: "Image 12. Custom M.2 to Oculink adapter with flex connector 3D renders" sierra_express_differential_pair_topologies: - path: "/images/diagrams/sierra_express_differential_pair_topologies.png" + path: "images/diagrams/sierra_express_differential_pair_topologies.png" description: "Diagram 3. Differential pair topologies" source: "https://impedance.app.protoexpress.com/" altium_eye_diagram: - path: "/images/diagrams/altium_eye_diagram.png" + path: "images/diagrams/altium_eye_diagram.png" description: "Diagram 4. Eye diagram" source: "https://resources.altium.com/p/what-eye-diagram" via_fence_diagram: - path: "/images/diagrams/via_fence_diagram.png" + path: "images/diagrams/via_fence_diagram.png" description: "Diagram 5. Via fence" via_jump_diagram: - path: "/images/diagrams/via_jump_diagram.png" + path: "images/diagrams/via_jump_diagram.png" description: "Diagram 6. Via jump with current path (red/blue) and E-field (yellow)" via_jump_pcb: - path: "/images/diagrams/via_jump_pcb.png" + path: "images/diagrams/via_jump_pcb.png" description: "Diagram 7. Via jump design with teardrop taper" sierra_express_via_stub_back_drilling: - path: "/images/diagrams/sierra_express_via_stub_back_drilling.png" + path: "images/diagrams/sierra_express_via_stub_back_drilling.png" description: "Diagram 8. Via stub back drilling" source: "https://www.protoexpress.com/blog/back-drilling-pcb-design-and-manufacturing/" jlcpcb_what_is_pcb_via: - path: "/images/diagrams/jlcpcb_what_is_pcb_via.png" + path: "images/diagrams/jlcpcb_what_is_pcb_via.png" description: "Diagram 9. Buried, blind and through hole vias" source: "https://jlcpcb.com/blog/what-is-pcb-via" copper_roughness_skin_effect: - path: "/images/diagrams/copper_roughness_skin_effect.png" + path: "images/diagrams/copper_roughness_skin_effect.png" description: "Diagram 10. Visualisation of skin effect on rough conductive surfaces" source: "https://industrial.evidentscientific.com.cn/en/applications/copper-foil-surface-roughness-for-5g-printed-circuit-boards/" sierra_express_length_matching: - path: "/images/diagrams/sierra_express_length_matching.jpg" + path: "images/diagrams/sierra_express_length_matching.jpg" description: "Diagram 11. Techniques to length match differential pair" source: "https://www.protoexpress.com/blog/signal-propagation-delay-pcb/" fibre_weave_skew_time_domain: description: "Diagram 12. Asymmetric routing over fibre-weave can produce intra-pair skew" - path: "/images/diagrams/fibre_weave_skew_time_domain.jpg" + path: "images/diagrams/fibre_weave_skew_time_domain.jpg" source: "https://www.signalintegrityjournal.com/articles/2459-beware-of-the-skew-budget-how-fiber-weave-effect-can-affect-your-high-speed-design" fibre_weave_skew_eye_opening: description: "Diagram 13. Asymmetric routing over fibre-weave will degrade eye opening" - path: "/images/diagrams/fibre_weave_skew_eye_diagram.jpg" + path: "images/diagrams/fibre_weave_skew_eye_diagram.jpg" source: "https://www.signalintegrityjournal.com/articles/2459-beware-of-the-skew-budget-how-fiber-weave-effect-can-affect-your-high-speed-design" fibre_weave_patterns: description: "Image 13. Fibre weave patterns that are available from manufacturers" - path: "/images/diagrams/fibre_weave_patterns.png" + path: "images/diagrams/fibre_weave_patterns.png" source: "https://resources.pcb.cadence.com/blog/2019-the-fiber-weave-effect-skew-losses-and-resonance" altium_fibre_weave_flattened: description: "Image 14. Mechnically compressed fibre glass with flattened weave pattern" - path: "/images/diagrams/altium_fibre_weave_flattened.png" + path: "images/diagrams/altium_fibre_weave_flattened.png" source: "https://resources.altium.com/p/how-the-fiber-weave-effect-influences-high-frequency-signal-integrity" jlcpcb_controlled_impedance_stackup_weave_patterns: description: "Image 15. JLCPCB fibre glass weave patterns for controlled impedance stackups" - path: "/images/diagrams/jlcpcb_controlled_impedance_stackup_weave_patterns.png" + path: "images/diagrams/jlcpcb_controlled_impedance_stackup_weave_patterns.png" source: "https://jlcpcb.com/impedance" hatched_ground_plane_unbalanced: description: "Diagram 14. Balanced and unbalanced routing of differential pair over hatched ground plane" - path: "/images/diagrams/hatched_ground_plane_unbalanced.png" + path: "images/diagrams/hatched_ground_plane_unbalanced.png" hatched_ground_plane_manual_differential_bend: description: "Image 16. Manually warped hatched ground plane with differential pair bend" - path: "/images/diagrams/hatched_ground_plane_manual_differential_bend.png" + path: "images/diagrams/hatched_ground_plane_manual_differential_bend.png" molex_ffc_fpc_connector: description: "Image 17. Molex FFC/FPC connector" - path: "/images/diagrams/molex_ffc_fpc_connector.png" + path: "images/diagrams/molex_ffc_fpc_connector.png" source: "https://www.molex.com/en-us/products/connectors/ffc-fpc-connectors" sierra_express_coplanar_ground_plane_via_fence_transmission_line: description: "Diagram 15. Differential pair with coplanar ground plane stitched with via fence" - path: "/images/diagrams/sierra_express_coplanar_ground_plane_via_fence_transmission_line.png" + path: "images/diagrams/sierra_express_coplanar_ground_plane_via_fence_transmission_line.png" parallel_plate_capacitor: description: "Diagram 16. Parallel plate capacitor" - path: "/images/diagrams/parallel_plate_capacitor.png" + path: "images/diagrams/parallel_plate_capacitor.png" source: "https://byjus.com/physics/parallel-plate-capacitor/" wire_plane_inductance: description: "Diagram 17. Solid wire over ground plane" - path: "/images/diagrams/wire_over_plane.png" + path: "images/diagrams/wire_over_plane.png" source: "https://www.allaboutcircuits.com/tools/wire-over-plane-inductance-calculator/" jlcpcb_stackup_diagram: description: "Diagram 18. JLCPCB FR4 stackup vs flexible PCB stackup" - path: "/images/diagrams/jlcpcb_stackup_diagram.png" + path: "images/diagrams/jlcpcb_stackup_diagram.png" source: "https://jlcpcb.com/impedance" jlcpcb_stackup_connection: description: "Diagram 19. JLCPCB transmission line connection between FR4 stackup and flexible PCB" - path: "/images/diagrams/jlcpcb_stackup_connection.png" + path: "images/diagrams/jlcpcb_stackup_connection.png" flex_pcb_transmission_line_taper: description: "Image 18. Flexible PCB transmission line taper" - path: "/images/diagrams/flex_pcb_transmission_line_taper.png" + path: "images/diagrams/flex_pcb_transmission_line_taper.png" openems_hatched_debug: description: "Image 19. Automatically generated hatched ground plane for openEMS simulation" - path: "/images/diagrams/openems_hatched_debug.png" + path: "images/diagrams/openems_hatched_debug.png" openems_hatched_3d: description: "Image 20. Automatically generated hatched ground plane 3D model" - path: "/images/diagrams/openems_hatched_3d.png" + path: "images/diagrams/openems_hatched_3d.png" openems_hatched_s_params: description: "Figure 1. S-parameter results of parameterised search of hatched ground plane with a hatch width of 150um" - path: "/images/diagrams/openems_hatched_s_params.png" + path: "images/diagrams/openems_hatched_s_params.png" openems_hatched_reflectance: description: "Figure 2. Reflectance results of parameterised search of hatched ground plane with a hatch width of 150um" - path: "/images/diagrams/openems_hatched_reflectance.png" + path: "images/diagrams/openems_hatched_reflectance.png" openems_hatched_reflectance_overall: description: "Figure 3. Reflectance results of parameterised search of hatched ground plane across all parameters" - path: "/images/diagrams/openems_hatched_reflectance_overall.png" + path: "images/diagrams/openems_hatched_reflectance_overall.png" openems_hatched_s_params_overall: description: "Figure 4. S-parameter results of parameterised search of hatched ground plane across all parameters" - path: "/images/diagrams/openems_hatched_s_params_overall.png" + path: "images/diagrams/openems_hatched_s_params_overall.png" openems_taper_debug: description: "Image 21. Automatically generated taper ground plane for openEMS simulation" - path: "/images/diagrams/openems_taper_debug.png" + path: "images/diagrams/openems_taper_debug.png" openems_taper_3d: description: "Image 22. Automatically generated taper ground plane 3D model" - path: "/images/diagrams/openems_taper_3d.png" + path: "images/diagrams/openems_taper_3d.png" openems_taper_reflectance: description: "Figure 5. Reflectance results of parameterised search of taper ground plane with a hatch width of 150um" - path: "/images/diagrams/openems_taper_reflectance.png" + path: "images/diagrams/openems_taper_reflectance.png" openems_taper_s_params: description: "Figure 6. S-parameter results of parameterised search of taper ground plane with a hatch width of 150um" - path: "/images/diagrams/openems_taper_s_params.png" + path: "images/diagrams/openems_taper_s_params.png" openems_taper_reflectance_overall: description: "Figure 7. Reflectance results of parameterised search of taper ground plane across all parameters" - path: "/images/diagrams/openems_taper_reflectance_overall.png" + path: "images/diagrams/openems_taper_reflectance_overall.png" openems_taper_s_params_overall: description: "Figure 8. S-parameter results of parameterised search of taper ground plane across all parameters" - path: "/images/diagrams/openems_taper_s_params_overall.png" + path: "images/diagrams/openems_taper_s_params_overall.png" mechanic_ix5_reflow: description: "Image 23. Mechanic IX5 reflow heating plate" - path: "/images/pictures/mechanic_ix5_reflow.png" + path: "images/pictures/mechanic_ix5_reflow.png" ts100_soldering_iron: description: "Image 24. TS-100 soldering iron" - path: "/images/diagrams/ts100_soldering_iron.png" + path: "images/diagrams/ts100_soldering_iron.png" reflow_profile: description: "Figure 9. Different reflow profiles for lead free solder" - path: "/images/diagrams/reflow_profile.png" + path: "images/diagrams/reflow_profile.png" source: "https://www.7pcb.com/blog/lead-free-reflow-profile" aliexpress_m2_oculink_pcie4_extension: description: "Image 25. Aliexpress M.2 Oculink PCIe 4.0 silver plated extension cable" - path: "/images/diagrams/aliexpress_m2_oculink_pcie4_extension.png" + path: "images/diagrams/aliexpress_m2_oculink_pcie4_extension.png" source: "https://www.aliexpress.com/item/1005007486714630.html" laptop_photo_flex_pcb: description: "Image 26. Flexible PCB multi-board Oculink adapter installed in laptop" - path: "/images/pictures/laptop_photo_flex_pcb.jpg" + path: "images/pictures/laptop_photo_flex_pcb.jpg" laptop_photo_flex_pcb_with_m2: description: "Image 27. Flexible PCB multi-board Oculink adapter and M.2 SSD installed in laptop" - path: "/images/pictures/laptop_photo_flex_pcb_with_m2.jpg" + path: "images/pictures/laptop_photo_flex_pcb_with_m2.jpg" laptop_photo_single_board: description: "Image 28. Single board Oculink adapter installed in laptop" - path: "/images/pictures/laptop_photo_single_board.jpg" + path: "images/pictures/laptop_photo_single_board.jpg" laptop_photo_side_port: description: "Image 29. Oculink port exposed on laptop" - path: "/images/pictures/laptop_photo_side_port.jpg" + path: "images/pictures/laptop_photo_side_port.jpg" laptop_photo_aliexpress: description: "Image 30. Aliexpress PCIe 4.0 Oculink adapter installed in laptop" - path: "/images/pictures/laptop_photo_aliexpress.jpg" + path: "images/pictures/laptop_photo_aliexpress.jpg" diff --git a/docs/data/pdfs.yaml b/docs/data/pdfs.yaml index faf8ade..edb6e24 100644 --- a/docs/data/pdfs.yaml +++ b/docs/data/pdfs.yaml @@ -1,44 +1,44 @@ texas_instrument_pcie4_layout_guidelines: - path: "/pdfs/texas_instrument_pcie4_layout_guidelines.pdf" + path: "pdfs/texas_instrument_pcie4_layout_guidelines.pdf" title: "Layout guidelines for PCIe Gen 4.0" source: "https://www.ti.com/lit/an/slaae45/slaae45.pdf" adtlink_m2_pcie_x4_extension: - path: "/pdfs/adtlink_m2_pcie_x4_extension.pdf" + path: "pdfs/adtlink_m2_pcie_x4_extension.pdf" title: "Adtlink M.2 PCIe x4 extension cable schematic" source: "https://www.adt.link/download/ADT-Cable-R42SF-specification.html" amphenol_oculink_port_datasheet: - path: "/pdfs/amphenol_oculink_port_datasheet.pdf" + path: "pdfs/amphenol_oculink_port_datasheet.pdf" title: "Amphenol Oculink port datasheet" source: "https://cdn.amphenol-cs.com/media/wysiwyg/files/documentation/ps-7545.pdf" sff_9402_specification: - path: "/pdfs/sff_9402_specification.pdf" + path: "pdfs/sff_9402_specification.pdf" title: "SFF-9402 specification" source: "https://members.snia.org/document/dl/27380" gpdwin1_schematic: - path: "/pdfs/gpdwin1_schematic.pdf" + path: "pdfs/gpdwin1_schematic.pdf" title: "Gpdwin1 M.2 to Oculink adapter schematic" source: "https://gpd.hk/gpdg1firmwaredriver" jlcpcb_flex_pcb_datasheet: - path: "/pdfs/jlcpcb_flex_pcb_datasheet.pdf" + path: "pdfs/jlcpcb_flex_pcb_datasheet.pdf" title: "JLCPCB flex pcb materials datasheet" source: "https://jlcpcb.com/resources/flexible-pcb" jlcpcb_kicad_7_generate_gerber_and_drill_files: - path: "/pdfs/jlcpcb_kicad_7_generate_gerber_and_drill_files.pdf" + path: "pdfs/jlcpcb_kicad_7_generate_gerber_and_drill_files.pdf" title: "JLCPCB instructions to generate KiCAD 7 gerber and drill files" source: "https://jlcpcb.com/help/article/how-to-generate-gerber-and-drill-files-in-kicad-7" lenovo_ideapad_pro_5_16arp8_specification: - path: "/pdfs/lenovo_ideapad_pro_5_16arp8_specification.pdf" + path: "pdfs/lenovo_ideapad_pro_5_16arp8_specification.pdf" title: "Lenovo IdeaPad Pro 5 16arp8 specifications" source: "https://psref.lenovo.com/WDProduct/IdeaPad/IdeaPad_Pro_5_16ARP8?tab=spec" north_dakota_university_via_fencing: - path: "/pdfs/north_dakota_university_via_fencing.pdf" + path: "pdfs/north_dakota_university_via_fencing.pdf" title: "Effectiveness of PCB perimeter via fencing" source: "https://www.ndsu.edu/pubweb/~braaten/EMC_2016_1.pdf" isola_group_fibre_weave_patterns: - path: "/pdfs/isola_group_fibre_weave_patterns.pdf" + path: "pdfs/isola_group_fibre_weave_patterns.pdf" title: "Isola group: Fibre weave patterns" source: "https://www.isola-group.com/wp-content/uploads/Understanding-Laminate-Prepreg-Manufacturing.pdf" molex_ffc_fpc_datasheet: - path: "/pdfs/molex_ffc_fpc_datasheet.pdf" + path: "pdfs/molex_ffc_fpc_datasheet.pdf" title: "Molex: FFC/FPC connector maximum usable frequency and compatability with high speed USB" source: "https://www.content.molex.com/dxdam/2f/2f35250f-5aa9-4ce8-a8be-a251f68293e0/987652-0193.pdf" diff --git a/docs/layouts/shortcodes/aida64_table.html b/docs/layouts/shortcodes/aida64_table.html index d9fb59f..f694dfd 100644 --- a/docs/layouts/shortcodes/aida64_table.html +++ b/docs/layouts/shortcodes/aida64_table.html @@ -1,6 +1,6 @@ {{- $benchmarks := .Site.Data.benchmarks -}} {{- $rows := index $benchmarks "aida64" }} -{{- $baseurl := absURL "/images/benchmarks" -}} +{{- $baseurl := absURL "images/benchmarks" -}} diff --git a/docs/layouts/shortcodes/benchmark_carousel.html b/docs/layouts/shortcodes/benchmark_carousel.html index d3da6eb..d9906d2 100644 --- a/docs/layouts/shortcodes/benchmark_carousel.html +++ b/docs/layouts/shortcodes/benchmark_carousel.html @@ -1,7 +1,7 @@ {{- $key := .Get "key" -}} {{- $benchmarks := .Site.Data.benchmarks -}} {{- $rows := index $benchmarks $key }} -{{- $baseurl := absURL "/images/benchmarks" -}} +{{- $baseurl := absURL "images/benchmarks" -}}
{{ range $rows }} diff --git a/docs/layouts/shortcodes/gpuz_images.html b/docs/layouts/shortcodes/gpuz_images.html index 60b7f03..efa014d 100644 --- a/docs/layouts/shortcodes/gpuz_images.html +++ b/docs/layouts/shortcodes/gpuz_images.html @@ -1,6 +1,6 @@ {{- $benchmarks := .Site.Data.benchmarks -}} {{- $rows := index $benchmarks "gpuz" }} -{{- $baseurl := absURL "/images/benchmarks" -}} +{{- $baseurl := absURL "images/benchmarks" -}}