From 396f35447b79e76ef7969caddc72e201bb8ff0fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 30 Jul 2024 07:51:41 +0200 Subject: [PATCH] sky130ram: delete log files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I think these are log files, the Python syntax is invalid(fails with black .) Signed-off-by: Øyvind Harboe --- .../sky130_sram_1rw1r_128x256_8.log | 160 ----------------- .../sky130_sram_1rw1r_128x256_8_extended.py | 88 ---------- .../sky130_sram_1rw1r_44x64_8.log | 158 ----------------- .../sky130_sram_1rw1r_44x64_8_extended.py | 88 ---------- .../sky130_sram_1rw1r_64x256_8.log | 163 ------------------ .../sky130_sram_1rw1r_64x256_8_extended.py | 88 ---------- .../sky130_sram_1rw1r_80x64_8.log | 158 ----------------- .../sky130_sram_1rw1r_80x64_8_extended.py | 88 ---------- 8 files changed, 991 deletions(-) delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log delete mode 100644 flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log b/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log deleted file mode 100644 index 2fdf89c9c8..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log +++ /dev/null @@ -1,160 +0,0 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /tmp/openram_wbduan_23636_temp/ -[globals/read_config]: Configuration file is /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_128x256_8.py -[globals/read_config]: Output saved in /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/ -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/third_party/OpenRAM/technology -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology -[globals/init_paths]: Creating temp directory: /tmp/openram_wbduan_23636_temp/ -[globals/setup_bitcell]: Using bitcell: bitcell_2port -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. -[globals/setup_bitcell]: Using bitcell: bitcell_2port -|==============================================================================| -|========= OpenRAM v1.1.6 =========| -|========= =========| -|========= VLSI Design and Automation Lab =========| -|========= Computer Science and Engineering Department =========| -|========= University of California Santa Cruz =========| -|========= =========| -|========= Usage help: openram-user-group@ucsc.edu =========| -|========= Development help: openram-dev-group@ucsc.edu =========| -|========= Temp dir: /tmp/openram_wbduan_23636_temp/ =========| -|========= See LICENSE for license info =========| -|==============================================================================| -** Start: 11/25/2020 16:57:40 -Technology: sky130 -Total size: 32768 bits -WARNING: file globals.py: line 571: Requesting such a large memory size (32768) will have a large run-time. Consider using multiple smaller banks. - -Word size: 128 -Words: 256 -Banks: 1 -Write size: 8 -RW ports: 1 -R-only ports: 1 -W-only ports: 0 -Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). -DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). -DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). -Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). -Only generating nominal corner timing. -[sram_config/recompute_sizes]: Recomputing with words per row: 1 -[sram_config/recompute_sizes]: Rows: 256 Cols: 128 -[sram_config/recompute_sizes]: Row addr size: 8 Col addr size: 0 Bank addr size: 8 -Words per row: 1 -Output files are: -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lvs -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.sp -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.v -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lib -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.py -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.html -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.log -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lef -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.gds -[sram/__init__]: Changed OPTS wpr=1 -[sram/__init__]: OPTS wpr=1 -[dff_array/__init__]: Creating row_addr_dff rows=8 cols=1 -[dff_array/__init__]: Creating data_dff rows=1 cols=128 -[dff_array/__init__]: Creating wmask_dff rows=1 cols=16 -[and2_dec/__init__]: Creating and2_dec and2_dec -[and3_dec/__init__]: Creating and3_dec and3_dec -[and4_dec/__init__]: Creating and4_dec and4_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pbuf_dec/__init__]: creating pbuf_dec with size of 8 -[bitcell_base_array/__init__]: Creating global_bitcell_array 256 x 128 -[bitcell_base_array/__init__]: Creating local_bitcell_array 256 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array 256 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 256 x 16 rbls: [1, 1] left_rbl: [0] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array 256 x 16 -[bitcell_array/__init__]: Creating bitcell_array 256 x 16 -[bitcell_base_array/__init__]: Creating replica_column 258 x 1 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 258 x 1 -[bitcell_base_array/__init__]: Creating row_cap_array_0 258 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array -[bitcell_base_array/__init__]: Creating local_bitcell_array_0 256 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_0 256 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 256 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array_0 256 x 16 -[bitcell_array/__init__]: Creating bitcell_array_0 256 x 16 -[bitcell_base_array/__init__]: Creating dummy_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_1 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_2 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array_1 258 x 1 -[bitcell_base_array/__init__]: Creating local_bitcell_array_1 256 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_1 256 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_1 256 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [1] -[bitcell_base_array/__init__]: Creating replica_column_0 258 x 1 -[precharge_array/__init__]: Creating precharge_array -[sense_amp_array/__init__]: Creating sense_amp_array -[write_driver_array/__init__]: Creating write_driver_array -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pdriver/__init__]: creating pdriver pdriver -[precharge_array/__init__]: Creating precharge_array_0 -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pdriver/__init__]: creating pdriver pdriver_0 -[pbuf/__init__]: creating pbuf with size of 128 -[pdriver/__init__]: creating pdriver pdriver_1 -[pdriver/__init__]: creating pdriver pdriver_2 -[pand3/__init__]: Creating pand3 pand3 -[pdriver/__init__]: creating pdriver pdriver_3 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[pdriver/__init__]: creating pdriver pdriver_5 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_6 -** Submodules: 10.6 seconds -** Placement: 0.7 seconds -** Routing: 0.4 seconds -** Verification: 0.0 seconds -** SRAM creation: 11.8 seconds -GDS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.gds -** GDS: 6.9 seconds -LEF: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lef -** LEF: 166.0 seconds -SP: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.sp -** Spice writing: 1.3 seconds -LVS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.lvs.sp -** LVS writing: 0.1 seconds -LIB: Characterizing... -[characterizer.lib/prepare_tables]: Loads: [ 1.7225 6.89 27.56 ] -[characterizer.lib/prepare_tables]: Slews: [0.00125 0.005 0.04 ] -[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 1.8, 25)] -[characterizer.lib/characterize_corners]: Corner: ('TT', 1.8, 25) -[characterizer.lib/characterize_corners]: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_TT_1p8V_25C.lib -[characterizer.delay/analytical_power]: Dynamic Power: 89.54866314460835 mW -[characterizer.delay/analytical_power]: Leakage Power: 0.039892 mW -[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) -[characterizer.delay/analytical_delay]: 0.00125, 1.7225, 0.36550338539740557, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.00125, 6.89, 0.39457057289740555, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.00125, 27.56, 0.5108393228974055, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.005, 1.7225, 0.36550338539740557, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.005, 6.89, 0.39457057289740555, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.005, 27.56, 0.5108393228974055, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.04, 1.7225, 0.36550338539740557, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.04, 6.89, 0.39457057289740555, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.04, 27.56, 0.5108393228974055, 0.016211249999999996 -** Characterization: 0.8 seconds -Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.py -** Config: 0.0 seconds -Datasheet: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.html -** Datasheet: 0.0 seconds -Verilog: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8.v -** Verilog: 0.0 seconds -Extended Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py -** Extended Config: 0.0 seconds -[globals/cleanup_paths]: Purging temp directory: /tmp/openram_wbduan_23636_temp/ -** End: 187.0 seconds diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py b/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py deleted file mode 100644 index ecd722f38c..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_128x256_8/sky130_sram_1rw1r_128x256_8_extended.py +++ /dev/null @@ -1,88 +0,0 @@ -accuracy_requirement = 0.75 -analytical_delay = True -auto_delay_chain_sizing = False -bank_select = "bank_select" -bitcell = "bitcell_2port" -bitcell_array = "bitcell_array" -buf_dec = "pbuf" -check_lvsdrc = False -col_cap = "col_cap" -col_cap_array = "col_cap_array" -column_mux_array = "column_mux_array" -config_file = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_128x256_8.py" -control_logic = "control_logic" -coverage = 1 -debug = False -decoder = "hierarchical_decoder" -delay_chain = "delay_chain" -delay_chain_fanout_per_stage = 4 -delay_chain_stages = 9 -dff = "dff" -dff_array = "dff_array" -drc_exe = None -drc_name = "" -dummy_bitcell = "dummy_bitcell_2port" -human_byte_size = "4kbytes" -inline_lvsdrc = False -inv_dec = "pinv" -is_unit_test = False -keep_temp = False -load_scales = [0.25, 1, 4] -local_array_size = 16 -lvs_exe = None -lvs_name = "" -magic_exe = None -nand2_dec = "pnand2" -nand3_dec = "pnand3" -nand4_dec = "pnand4" -netlist_only = False -nominal_corner_only = True -num_banks = 1 -num_r_ports = 1 -num_rw_ports = 1 -num_spare_cols = 0 -num_spare_rows = 0 -num_threads = 2 -num_w_ports = 0 -num_words = 256 -openram_tech = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology/sky130/" -openram_temp = "/tmp/openram_wbduan_23636_temp/" -os = -output_extended_config = True -output_name = "sky130_sram_1rw1r_128x256_8" -output_path = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_128x256_8/" -overridden = {'__name__': True, '__doc__': True, '__package__': True, '__loader__': True, '__spec__': True, '__file__': True, '__cached__': True, '__builtins__': True, 'word_size': True, 'num_words': True, 'human_byte_size': True, 'write_size': True, 'num_rw_ports': True, 'num_r_ports': True, 'num_w_ports': True, 'ports_human': True, 'os': True, '__warningregistry__': True, 'tech_name': True, 'nominal_corner_only': True, 'local_array_size': True, 'route_supplies': True, 'perimeter_pins': True} -perimeter_pins = False -pex_exe = None -pex_name = "" -ports_human = "1rw1r" -precharge_array = "precharge_array" -print_banner = True -process_corners = ['TT'] -ptx = "ptx" -rbl_delay_percentage = 0.5 -replica_bitcell = "replica_bitcell_2port" -replica_bitline = "replica_bitline" -route_supplies = False -row_cap = "row_cap" -row_cap_array = "row_cap_array" -sense_amp = "sense_amp" -sense_amp_array = "sense_amp_array" -slew_scales = [0.25, 1, 8] -spice_exe = "" -spice_name = "" -supply_voltages = [1.8] -tech_name = "sky130" -temperatures = [25] -tri_gate = "tri_gate" -tri_gate_array = "tri_gate_array" -trim_netlist = False -use_pex = False -verbose_level = 1 -word_size = 128 -wordline_driver = "wordline_driver" -words_per_row = 1 -write_driver = "write_driver" -write_driver_array = "write_driver_array" -write_mask_and_array = "write_mask_and_array" -write_size = 8 diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log b/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log deleted file mode 100644 index 95ab3df97d..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log +++ /dev/null @@ -1,158 +0,0 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /tmp/openram_wbduan_3846_temp/ -[globals/read_config]: Configuration file is /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_44x64_8.py -[globals/read_config]: Output saved in /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/ -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/third_party/OpenRAM/technology -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology -[globals/init_paths]: Creating temp directory: /tmp/openram_wbduan_3846_temp/ -[globals/setup_bitcell]: Using bitcell: bitcell_2port -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. -[globals/setup_bitcell]: Using bitcell: bitcell_2port -|==============================================================================| -|========= OpenRAM v1.1.6 =========| -|========= =========| -|========= VLSI Design and Automation Lab =========| -|========= Computer Science and Engineering Department =========| -|========= University of California Santa Cruz =========| -|========= =========| -|========= Usage help: openram-user-group@ucsc.edu =========| -|========= Development help: openram-dev-group@ucsc.edu =========| -|========= Temp dir: /tmp/openram_wbduan_3846_temp/ =========| -|========= See LICENSE for license info =========| -|==============================================================================| -** Start: 11/23/2020 21:22:46 -ERROR: file globals.py: line 557: Write size needs to be an integer multiple of word size. - -Technology: sky130 -Total size: 2816 bits -Word size: 44 -Words: 64 -Banks: 1 -Write size: 8 -RW ports: 1 -R-only ports: 1 -W-only ports: 0 -Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). -DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). -DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). -Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). -Only generating nominal corner timing. -[sram_config/recompute_sizes]: Recomputing with words per row: 1 -[sram_config/recompute_sizes]: Rows: 64 Cols: 44 -[sram_config/recompute_sizes]: Row addr size: 6 Col addr size: 0 Bank addr size: 6 -Words per row: 1 -Output files are: -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lvs -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.sp -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.v -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lib -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.py -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.html -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.log -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lef -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.gds -[sram/__init__]: Changed OPTS wpr=1 -[sram/__init__]: OPTS wpr=1 -[dff_array/__init__]: Creating row_addr_dff rows=6 cols=1 -[dff_array/__init__]: Creating data_dff rows=1 cols=44 -[dff_array/__init__]: Creating wmask_dff rows=1 cols=6 -[and2_dec/__init__]: Creating and2_dec and2_dec -[and3_dec/__init__]: Creating and3_dec and3_dec -[and4_dec/__init__]: Creating and4_dec and4_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pbuf_dec/__init__]: creating pbuf_dec with size of 2 -[bitcell_base_array/__init__]: Creating global_bitcell_array 64 x 44 -[bitcell_base_array/__init__]: Creating local_bitcell_array 64 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array 64 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 64 x 16 rbls: [1, 1] left_rbl: [0] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array 64 x 16 -[bitcell_array/__init__]: Creating bitcell_array 64 x 16 -[bitcell_base_array/__init__]: Creating replica_column 66 x 1 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 66 x 1 -[bitcell_base_array/__init__]: Creating row_cap_array_0 66 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array -[bitcell_base_array/__init__]: Creating local_bitcell_array_0 64 x 28 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_0 64 x 28 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 64 x 28 rbls: [1, 1] left_rbl: [] right_rbl: [1] -[bitcell_base_array/__init__]: Creating bitcell_array_0 64 x 28 -[bitcell_array/__init__]: Creating bitcell_array_0 64 x 28 -[bitcell_base_array/__init__]: Creating replica_column_0 66 x 1 -[bitcell_base_array/__init__]: Creating dummy_array_0 1 x 28 -[bitcell_base_array/__init__]: Creating col_cap_array_1 1 x 28 -[bitcell_base_array/__init__]: Creating col_cap_array_2 1 x 28 -[bitcell_base_array/__init__]: Creating row_cap_array_1 66 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array_0 -[precharge_array/__init__]: Creating precharge_array -[sense_amp_array/__init__]: Creating sense_amp_array -[write_driver_array/__init__]: Creating write_driver_array -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pdriver/__init__]: creating pdriver pdriver -[precharge_array/__init__]: Creating precharge_array_0 -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pdriver/__init__]: creating pdriver pdriver_0 -[pbuf/__init__]: creating pbuf with size of 44 -[pdriver/__init__]: creating pdriver pdriver_1 -[pdriver/__init__]: creating pdriver pdriver_2 -[pand3/__init__]: Creating pand3 pand3 -[pdriver/__init__]: creating pdriver pdriver_3 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[pdriver/__init__]: creating pdriver pdriver_5 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_6 -** Submodules: 3.4 seconds -** Placement: 0.1 seconds -** Routing: 0.1 seconds -** Verification: 0.0 seconds -** SRAM creation: 3.6 seconds -GDS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.gds -** GDS: 2.2 seconds -LEF: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lef -** LEF: 15.4 seconds -SP: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.sp -** Spice writing: 0.3 seconds -LVS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.lvs.sp -** LVS writing: 0.0 seconds -LIB: Characterizing... -[characterizer.lib/prepare_tables]: Loads: [ 1.7225 6.89 27.56 ] -[characterizer.lib/prepare_tables]: Slews: [0.00125 0.005 0.04 ] -[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 1.8, 25)] -[characterizer.lib/characterize_corners]: Corner: ('TT', 1.8, 25) -[characterizer.lib/characterize_corners]: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_TT_1p8V_25C.lib -[characterizer.delay/analytical_power]: Dynamic Power: 10.353463918847996 mW -[characterizer.delay/analytical_power]: Leakage Power: 0.003998 mW -[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) -[characterizer.delay/analytical_delay]: 0.00125, 1.7225, 0.31694700077670185, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.00125, 6.89, 0.34601418827670183, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.00125, 27.56, 0.46228293827670175, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.005, 1.7225, 0.31694700077670185, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.005, 6.89, 0.34601418827670183, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.005, 27.56, 0.46228293827670175, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.04, 1.7225, 0.31694700077670185, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.04, 6.89, 0.34601418827670183, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.04, 27.56, 0.46228293827670175, 0.016211249999999996 -** Characterization: 0.2 seconds -Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.py -** Config: 0.0 seconds -Datasheet: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.html -** Datasheet: 0.0 seconds -Verilog: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8.v -** Verilog: 0.0 seconds -Extended Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py -** Extended Config: 0.0 seconds -[globals/cleanup_paths]: Purging temp directory: /tmp/openram_wbduan_3846_temp/ -** End: 21.9 seconds diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py b/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py deleted file mode 100644 index ddc8cfa39c..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_44x64_8/sky130_sram_1rw1r_44x64_8_extended.py +++ /dev/null @@ -1,88 +0,0 @@ -accuracy_requirement = 0.75 -analytical_delay = True -auto_delay_chain_sizing = False -bank_select = "bank_select" -bitcell = "bitcell_2port" -bitcell_array = "bitcell_array" -buf_dec = "pbuf" -check_lvsdrc = False -col_cap = "col_cap" -col_cap_array = "col_cap_array" -column_mux_array = "column_mux_array" -config_file = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_44x64_8.py" -control_logic = "control_logic" -coverage = 1 -debug = False -decoder = "hierarchical_decoder" -delay_chain = "delay_chain" -delay_chain_fanout_per_stage = 4 -delay_chain_stages = 9 -dff = "dff" -dff_array = "dff_array" -drc_exe = None -drc_name = "" -dummy_bitcell = "dummy_bitcell_2port" -human_byte_size = "0kbytes" -inline_lvsdrc = False -inv_dec = "pinv" -is_unit_test = False -keep_temp = False -load_scales = [0.25, 1, 4] -local_array_size = 16 -lvs_exe = None -lvs_name = "" -magic_exe = None -nand2_dec = "pnand2" -nand3_dec = "pnand3" -nand4_dec = "pnand4" -netlist_only = False -nominal_corner_only = True -num_banks = 1 -num_r_ports = 1 -num_rw_ports = 1 -num_spare_cols = 0 -num_spare_rows = 0 -num_threads = 2 -num_w_ports = 0 -num_words = 64 -openram_tech = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology/sky130/" -openram_temp = "/tmp/openram_wbduan_3846_temp/" -os = -output_extended_config = True -output_name = "sky130_sram_1rw1r_44x64_8" -output_path = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_44x64_8/" -overridden = {'__name__': True, '__doc__': True, '__package__': True, '__loader__': True, '__spec__': True, '__file__': True, '__cached__': True, '__builtins__': True, 'word_size': True, 'num_words': True, 'human_byte_size': True, 'write_size': True, 'num_rw_ports': True, 'num_r_ports': True, 'num_w_ports': True, 'ports_human': True, 'os': True, '__warningregistry__': True, 'tech_name': True, 'nominal_corner_only': True, 'local_array_size': True, 'route_supplies': True, 'perimeter_pins': True} -perimeter_pins = False -pex_exe = None -pex_name = "" -ports_human = "1rw1r" -precharge_array = "precharge_array" -print_banner = True -process_corners = ['TT'] -ptx = "ptx" -rbl_delay_percentage = 0.5 -replica_bitcell = "replica_bitcell_2port" -replica_bitline = "replica_bitline" -route_supplies = False -row_cap = "row_cap" -row_cap_array = "row_cap_array" -sense_amp = "sense_amp" -sense_amp_array = "sense_amp_array" -slew_scales = [0.25, 1, 8] -spice_exe = "" -spice_name = "" -supply_voltages = [1.8] -tech_name = "sky130" -temperatures = [25] -tri_gate = "tri_gate" -tri_gate_array = "tri_gate_array" -trim_netlist = False -use_pex = False -verbose_level = 1 -word_size = 44 -wordline_driver = "wordline_driver" -words_per_row = 1 -write_driver = "write_driver" -write_driver_array = "write_driver_array" -write_mask_and_array = "write_mask_and_array" -write_size = 8 diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log b/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log deleted file mode 100644 index e897157892..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log +++ /dev/null @@ -1,163 +0,0 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /tmp/openram_wbduan_3328_temp/ -[globals/read_config]: Configuration file is /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_64x256_8.py -[globals/read_config]: Output saved in /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/ -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/third_party/OpenRAM/technology -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology -[globals/init_paths]: Creating temp directory: /tmp/openram_wbduan_3328_temp/ -[globals/setup_bitcell]: Using bitcell: bitcell_2port -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. -[globals/setup_bitcell]: Using bitcell: bitcell_2port -|==============================================================================| -|========= OpenRAM v1.1.6 =========| -|========= =========| -|========= VLSI Design and Automation Lab =========| -|========= Computer Science and Engineering Department =========| -|========= University of California Santa Cruz =========| -|========= =========| -|========= Usage help: openram-user-group@ucsc.edu =========| -|========= Development help: openram-dev-group@ucsc.edu =========| -|========= Temp dir: /tmp/openram_wbduan_3328_temp/ =========| -|========= See LICENSE for license info =========| -|==============================================================================| -** Start: 11/23/2020 21:16:39 -Technology: sky130 -Total size: 16384 bits -WARNING: file globals.py: line 571: Requesting such a large memory size (16384) will have a large run-time. Consider using multiple smaller banks. - -Word size: 64 -Words: 256 -Banks: 1 -Write size: 8 -RW ports: 1 -R-only ports: 1 -W-only ports: 0 -Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). -DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). -DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). -Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). -Only generating nominal corner timing. -[sram_config/recompute_sizes]: Recomputing with words per row: 2 -[sram_config/recompute_sizes]: Rows: 128 Cols: 128 -[sram_config/recompute_sizes]: Row addr size: 7 Col addr size: 1 Bank addr size: 8 -Words per row: 2 -Output files are: -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lvs -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.sp -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.v -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lib -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.py -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.html -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.log -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lef -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.gds -[sram/__init__]: Changed OPTS wpr=2 -[sram/__init__]: OPTS wpr=2 -[dff_array/__init__]: Creating row_addr_dff rows=7 cols=1 -[dff_array/__init__]: Creating col_addr_dff rows=1 cols=1 -[dff_array/__init__]: Creating data_dff rows=1 cols=64 -[dff_array/__init__]: Creating wmask_dff rows=1 cols=8 -[and2_dec/__init__]: Creating and2_dec and2_dec -[and3_dec/__init__]: Creating and3_dec and3_dec -[and4_dec/__init__]: Creating and4_dec and4_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pbuf_dec/__init__]: creating pbuf_dec with size of 8 -[bitcell_base_array/__init__]: Creating global_bitcell_array 128 x 128 -[bitcell_base_array/__init__]: Creating local_bitcell_array 128 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array 128 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 128 x 16 rbls: [1, 1] left_rbl: [0] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array 128 x 16 -[bitcell_array/__init__]: Creating bitcell_array 128 x 16 -[bitcell_base_array/__init__]: Creating replica_column 130 x 1 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 130 x 1 -[bitcell_base_array/__init__]: Creating row_cap_array_0 130 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array -[bitcell_base_array/__init__]: Creating local_bitcell_array_0 128 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_0 128 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 128 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array_0 128 x 16 -[bitcell_array/__init__]: Creating bitcell_array_0 128 x 16 -[bitcell_base_array/__init__]: Creating dummy_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_1 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_2 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array_1 130 x 1 -[bitcell_base_array/__init__]: Creating local_bitcell_array_1 128 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_1 128 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_1 128 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [1] -[bitcell_base_array/__init__]: Creating replica_column_0 130 x 1 -[precharge_array/__init__]: Creating precharge_array -[sense_amp_array/__init__]: Creating sense_amp_array -[column_mux_array/__init__]: Creating column_mux_array -[write_driver_array/__init__]: Creating write_driver_array -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pdriver/__init__]: creating pdriver pdriver -[precharge_array/__init__]: Creating precharge_array_0 -[column_mux_array/__init__]: Creating column_mux_array_0 -[pinvbuf/__init__]: creating pinvbuf pinvbuf -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pdriver/__init__]: creating pdriver pdriver_0 -[pbuf/__init__]: creating pbuf with size of 128 -[pdriver/__init__]: creating pdriver pdriver_1 -[pdriver/__init__]: creating pdriver pdriver_2 -[pand3/__init__]: Creating pand3 pand3 -[pdriver/__init__]: creating pdriver pdriver_3 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_5 -** Submodules: 6.0 seconds -** Placement: 0.4 seconds -** Routing: 0.2 seconds -** Verification: 0.0 seconds -** SRAM creation: 6.6 seconds -GDS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.gds -** GDS: 3.7 seconds -LEF: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lef -** LEF: 84.6 seconds -SP: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.sp -** Spice writing: 0.7 seconds -LVS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.lvs.sp -** LVS writing: 0.1 seconds -LIB: Characterizing... -[characterizer.lib/prepare_tables]: Loads: [ 1.7225 6.89 27.56 ] -[characterizer.lib/prepare_tables]: Slews: [0.00125 0.005 0.04 ] -[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 1.8, 25)] -[characterizer.lib/characterize_corners]: Corner: ('TT', 1.8, 25) -[characterizer.lib/characterize_corners]: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_TT_1p8V_25C.lib -[characterizer.delay/analytical_power]: Dynamic Power: 45.61833593692795 mW -[characterizer.delay/analytical_power]: Leakage Power: 0.020078 mW -[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) -[characterizer.delay/analytical_delay]: 0.00125, 1.7225, 0.3799116424684287, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.00125, 6.89, 0.40897882996842866, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.00125, 27.56, 0.5252475799684286, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.005, 1.7225, 0.3799116424684287, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.005, 6.89, 0.40897882996842866, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.005, 27.56, 0.5252475799684286, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.04, 1.7225, 0.3799116424684287, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.04, 6.89, 0.40897882996842866, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.04, 27.56, 0.5252475799684286, 0.016211249999999996 -** Characterization: 0.5 seconds -Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.py -** Config: 0.0 seconds -Datasheet: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.html -** Datasheet: 0.0 seconds -Verilog: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8.v -** Verilog: 0.0 seconds -Extended Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py -** Extended Config: 0.0 seconds -[globals/cleanup_paths]: Purging temp directory: /tmp/openram_wbduan_3328_temp/ -** End: 96.3 seconds diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py b/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py deleted file mode 100644 index 635f5ac42b..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_64x256_8/sky130_sram_1rw1r_64x256_8_extended.py +++ /dev/null @@ -1,88 +0,0 @@ -accuracy_requirement = 0.75 -analytical_delay = True -auto_delay_chain_sizing = False -bank_select = "bank_select" -bitcell = "bitcell_2port" -bitcell_array = "bitcell_array" -buf_dec = "pbuf" -check_lvsdrc = False -col_cap = "col_cap" -col_cap_array = "col_cap_array" -column_mux_array = "column_mux_array" -config_file = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_64x256_8.py" -control_logic = "control_logic" -coverage = 1 -debug = False -decoder = "hierarchical_decoder" -delay_chain = "delay_chain" -delay_chain_fanout_per_stage = 4 -delay_chain_stages = 9 -dff = "dff" -dff_array = "dff_array" -drc_exe = None -drc_name = "" -dummy_bitcell = "dummy_bitcell_2port" -human_byte_size = "2kbytes" -inline_lvsdrc = False -inv_dec = "pinv" -is_unit_test = False -keep_temp = False -load_scales = [0.25, 1, 4] -local_array_size = 16 -lvs_exe = None -lvs_name = "" -magic_exe = None -nand2_dec = "pnand2" -nand3_dec = "pnand3" -nand4_dec = "pnand4" -netlist_only = False -nominal_corner_only = True -num_banks = 1 -num_r_ports = 1 -num_rw_ports = 1 -num_spare_cols = 0 -num_spare_rows = 0 -num_threads = 2 -num_w_ports = 0 -num_words = 256 -openram_tech = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology/sky130/" -openram_temp = "/tmp/openram_wbduan_3328_temp/" -os = -output_extended_config = True -output_name = "sky130_sram_1rw1r_64x256_8" -output_path = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_64x256_8/" -overridden = {'__name__': True, '__doc__': True, '__package__': True, '__loader__': True, '__spec__': True, '__file__': True, '__cached__': True, '__builtins__': True, 'word_size': True, 'num_words': True, 'human_byte_size': True, 'write_size': True, 'num_rw_ports': True, 'num_r_ports': True, 'num_w_ports': True, 'ports_human': True, 'os': True, '__warningregistry__': True, 'tech_name': True, 'nominal_corner_only': True, 'local_array_size': True, 'route_supplies': True, 'perimeter_pins': True} -perimeter_pins = False -pex_exe = None -pex_name = "" -ports_human = "1rw1r" -precharge_array = "precharge_array" -print_banner = True -process_corners = ['TT'] -ptx = "ptx" -rbl_delay_percentage = 0.5 -replica_bitcell = "replica_bitcell_2port" -replica_bitline = "replica_bitline" -route_supplies = False -row_cap = "row_cap" -row_cap_array = "row_cap_array" -sense_amp = "sense_amp" -sense_amp_array = "sense_amp_array" -slew_scales = [0.25, 1, 8] -spice_exe = "" -spice_name = "" -supply_voltages = [1.8] -tech_name = "sky130" -temperatures = [25] -tri_gate = "tri_gate" -tri_gate_array = "tri_gate_array" -trim_netlist = False -use_pex = False -verbose_level = 1 -word_size = 64 -wordline_driver = "wordline_driver" -words_per_row = 2 -write_driver = "write_driver" -write_driver_array = "write_driver_array" -write_mask_and_array = "write_mask_and_array" -write_size = 8 diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log b/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log deleted file mode 100644 index 5881892e12..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log +++ /dev/null @@ -1,158 +0,0 @@ -[globals/init_openram]: Initializing OpenRAM... -[globals/setup_paths]: Temporary files saved in /tmp/openram_wbduan_24000_temp/ -[globals/read_config]: Configuration file is /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_80x64_8.py -[globals/read_config]: Output saved in /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/ -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/third_party/OpenRAM/technology -[globals/import_tech]: Adding technology path: /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology -[globals/init_paths]: Creating temp directory: /tmp/openram_wbduan_24000_temp/ -[globals/setup_bitcell]: Using bitcell: bitcell_2port -[characterizer/]: Initializing characterizer... -[characterizer/]: Analytical model enabled. -[verify/]: Initializing verify... -[verify/]: LVS/DRC/PEX disabled. -[globals/setup_bitcell]: Using bitcell: bitcell_2port -|==============================================================================| -|========= OpenRAM v1.1.6 =========| -|========= =========| -|========= VLSI Design and Automation Lab =========| -|========= Computer Science and Engineering Department =========| -|========= University of California Santa Cruz =========| -|========= =========| -|========= Usage help: openram-user-group@ucsc.edu =========| -|========= Development help: openram-dev-group@ucsc.edu =========| -|========= Temp dir: /tmp/openram_wbduan_24000_temp/ =========| -|========= See LICENSE for license info =========| -|==============================================================================| -** Start: 11/25/2020 17:04:12 -Technology: sky130 -Total size: 5120 bits -Word size: 80 -Words: 64 -Banks: 1 -Write size: 8 -RW ports: 1 -R-only ports: 1 -W-only ports: 0 -Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing). -DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). -DRC/LVS/PEX is disabled (check_lvsdrc=True to enable). -Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). -Only generating nominal corner timing. -[sram_config/recompute_sizes]: Recomputing with words per row: 1 -[sram_config/recompute_sizes]: Rows: 64 Cols: 80 -[sram_config/recompute_sizes]: Row addr size: 6 Col addr size: 0 Bank addr size: 6 -Words per row: 1 -Output files are: -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lvs -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.sp -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.v -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lib -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.py -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.html -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.log -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lef -/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.gds -[sram/__init__]: Changed OPTS wpr=1 -[sram/__init__]: OPTS wpr=1 -[dff_array/__init__]: Creating row_addr_dff rows=6 cols=1 -[dff_array/__init__]: Creating data_dff rows=1 cols=80 -[dff_array/__init__]: Creating wmask_dff rows=1 cols=10 -[and2_dec/__init__]: Creating and2_dec and2_dec -[and3_dec/__init__]: Creating and3_dec and3_dec -[and4_dec/__init__]: Creating and4_dec and4_dec -[wordline_driver_array/__init__]: Creating wordline_driver_array -[wordline_driver/__init__]: Creating wordline_driver wordline_driver -[pbuf_dec/__init__]: creating pbuf_dec with size of 5 -[bitcell_base_array/__init__]: Creating global_bitcell_array 64 x 80 -[bitcell_base_array/__init__]: Creating local_bitcell_array 64 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array 64 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array 64 x 16 rbls: [1, 1] left_rbl: [0] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array 64 x 16 -[bitcell_array/__init__]: Creating bitcell_array 64 x 16 -[bitcell_base_array/__init__]: Creating replica_column 66 x 1 -[bitcell_base_array/__init__]: Creating dummy_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array 66 x 1 -[bitcell_base_array/__init__]: Creating row_cap_array_0 66 x 1 -[wordline_buffer_array/__init__]: Creating wordline_buffer_array -[bitcell_base_array/__init__]: Creating local_bitcell_array_0 64 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_0 64 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_0 64 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [] -[bitcell_base_array/__init__]: Creating bitcell_array_0 64 x 16 -[bitcell_array/__init__]: Creating bitcell_array_0 64 x 16 -[bitcell_base_array/__init__]: Creating dummy_array_0 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_1 1 x 16 -[bitcell_base_array/__init__]: Creating col_cap_array_2 1 x 16 -[bitcell_base_array/__init__]: Creating row_cap_array_1 66 x 1 -[bitcell_base_array/__init__]: Creating local_bitcell_array_1 64 x 16 -[bitcell_base_array/__init__]: Creating replica_bitcell_array_1 64 x 16 -[replica_bitcell_array/__init__]: Creating replica_bitcell_array_1 64 x 16 rbls: [1, 1] left_rbl: [] right_rbl: [1] -[bitcell_base_array/__init__]: Creating replica_column_0 66 x 1 -[precharge_array/__init__]: Creating precharge_array -[sense_amp_array/__init__]: Creating sense_amp_array -[write_driver_array/__init__]: Creating write_driver_array -[write_mask_and_array/__init__]: Creating write_mask_and_array -[pand2/__init__]: Creating pand2 pand2 -[pdriver/__init__]: creating pdriver pdriver -[precharge_array/__init__]: Creating precharge_array_0 -[control_logic/__init__]: Creating control_logic_rw -[dff_buf/__init__]: Creating dff_buf -[dff_buf_array/__init__]: Creating dff_buf_array -[dff_buf/__init__]: Creating dff_buf_0 -[pand2/__init__]: Creating pand2 pand2_0 -[pdriver/__init__]: creating pdriver pdriver_0 -[pbuf/__init__]: creating pbuf with size of 80 -[pdriver/__init__]: creating pdriver pdriver_1 -[pdriver/__init__]: creating pdriver pdriver_2 -[pand3/__init__]: Creating pand3 pand3 -[pdriver/__init__]: creating pdriver pdriver_3 -[pand3/__init__]: Creating pand3 pand3_0 -[pdriver/__init__]: creating pdriver pdriver_4 -[pdriver/__init__]: creating pdriver pdriver_5 -[delay_chain/__init__]: creating delay chain [4, 4, 4, 4, 4, 4, 4, 4, 4] -[control_logic/__init__]: Creating control_logic_r -[dff_buf_array/__init__]: Creating dff_buf_array_0 -[pdriver/__init__]: creating pdriver pdriver_6 -** Submodules: 3.6 seconds -** Placement: 0.4 seconds -** Routing: 0.2 seconds -** Verification: 0.0 seconds -** SRAM creation: 4.2 seconds -GDS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.gds -** GDS: 2.5 seconds -LEF: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lef -** LEF: 28.9 seconds -SP: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.sp -** Spice writing: 0.4 seconds -LVS: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.lvs.sp -** LVS writing: 0.0 seconds -LIB: Characterizing... -[characterizer.lib/prepare_tables]: Loads: [ 1.7225 6.89 27.56 ] -[characterizer.lib/prepare_tables]: Slews: [0.00125 0.005 0.04 ] -[characterizer.lib/characterize_corners]: Characterizing corners: [('TT', 1.8, 25)] -[characterizer.lib/characterize_corners]: Corner: ('TT', 1.8, 25) -[characterizer.lib/characterize_corners]: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_TT_1p8V_25C.lib -[characterizer.delay/analytical_power]: Dynamic Power: 16.77798724780799 mW -[characterizer.delay/analytical_power]: Leakage Power: 0.006744 mW -[characterizer.delay/analytical_delay]: Slew, Load, Delay(ns), Slew(ns) -[characterizer.delay/analytical_delay]: 0.00125, 1.7225, 0.32695406418057094, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.00125, 6.89, 0.3560212516805709, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.00125, 27.56, 0.4722900016805709, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.005, 1.7225, 0.32695406418057094, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.005, 6.89, 0.3560212516805709, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.005, 27.56, 0.4722900016805709, 0.016211249999999996 -[characterizer.delay/analytical_delay]: 0.04, 1.7225, 0.32695406418057094, 0.00167765625 -[characterizer.delay/analytical_delay]: 0.04, 6.89, 0.3560212516805709, 0.004584374999999999 -[characterizer.delay/analytical_delay]: 0.04, 27.56, 0.4722900016805709, 0.016211249999999996 -** Characterization: 0.3 seconds -Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.py -** Config: 0.0 seconds -Datasheet: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.html -** Datasheet: 0.0 seconds -Verilog: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8.v -** Verilog: 0.0 seconds -Extended Config: Writing to /afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py -** Extended Config: 0.0 seconds -[globals/cleanup_paths]: Purging temp directory: /tmp/openram_wbduan_24000_temp/ -** End: 36.5 seconds diff --git a/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py b/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py deleted file mode 100644 index 0c05402d34..0000000000 --- a/flow/platforms/sky130ram/sky130_sram_1rw1r_80x64_8/sky130_sram_1rw1r_80x64_8_extended.py +++ /dev/null @@ -1,88 +0,0 @@ -accuracy_requirement = 0.75 -analytical_delay = True -auto_delay_chain_sizing = False -bank_select = "bank_select" -bitcell = "bitcell_2port" -bitcell_array = "bitcell_array" -buf_dec = "pbuf" -check_lvsdrc = False -col_cap = "col_cap" -col_cap_array = "col_cap_array" -column_mux_array = "column_mux_array" -config_file = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/configs/sky130_sram_1rw1r_80x64_8.py" -control_logic = "control_logic" -coverage = 1 -debug = False -decoder = "hierarchical_decoder" -delay_chain = "delay_chain" -delay_chain_fanout_per_stage = 4 -delay_chain_stages = 9 -dff = "dff" -dff_array = "dff_array" -drc_exe = None -drc_name = "" -dummy_bitcell = "dummy_bitcell_2port" -human_byte_size = "1kbytes" -inline_lvsdrc = False -inv_dec = "pinv" -is_unit_test = False -keep_temp = False -load_scales = [0.25, 1, 4] -local_array_size = 16 -lvs_exe = None -lvs_name = "" -magic_exe = None -nand2_dec = "pnand2" -nand3_dec = "pnand3" -nand4_dec = "pnand4" -netlist_only = False -nominal_corner_only = True -num_banks = 1 -num_r_ports = 1 -num_rw_ports = 1 -num_spare_cols = 0 -num_spare_rows = 0 -num_threads = 2 -num_w_ports = 0 -num_words = 64 -openram_tech = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/tools/openram/technology/sky130/" -openram_temp = "/tmp/openram_wbduan_24000_temp/" -os = -output_extended_config = True -output_name = "sky130_sram_1rw1r_80x64_8" -output_path = "/afs/eecs.umich.edu/vlsida/projects/restricted/google/sky130_fd_bd_sram/macros/sky130_sram_1rw1r_80x64_8/" -overridden = {'__name__': True, '__doc__': True, '__package__': True, '__loader__': True, '__spec__': True, '__file__': True, '__cached__': True, '__builtins__': True, 'word_size': True, 'num_words': True, 'human_byte_size': True, 'write_size': True, 'num_rw_ports': True, 'num_r_ports': True, 'num_w_ports': True, 'ports_human': True, 'os': True, '__warningregistry__': True, 'tech_name': True, 'nominal_corner_only': True, 'local_array_size': True, 'route_supplies': True, 'perimeter_pins': True} -perimeter_pins = False -pex_exe = None -pex_name = "" -ports_human = "1rw1r" -precharge_array = "precharge_array" -print_banner = True -process_corners = ['TT'] -ptx = "ptx" -rbl_delay_percentage = 0.5 -replica_bitcell = "replica_bitcell_2port" -replica_bitline = "replica_bitline" -route_supplies = False -row_cap = "row_cap" -row_cap_array = "row_cap_array" -sense_amp = "sense_amp" -sense_amp_array = "sense_amp_array" -slew_scales = [0.25, 1, 8] -spice_exe = "" -spice_name = "" -supply_voltages = [1.8] -tech_name = "sky130" -temperatures = [25] -tri_gate = "tri_gate" -tri_gate_array = "tri_gate_array" -trim_netlist = False -use_pex = False -verbose_level = 1 -word_size = 80 -wordline_driver = "wordline_driver" -words_per_row = 1 -write_driver = "write_driver" -write_driver_array = "write_driver_array" -write_mask_and_array = "write_mask_and_array" -write_size = 8