designs: async fifo test case (The-OpenROAD-Project#1770)

Tore and Tom worked on the constraints.sdc files, any mistakes
in constraints.sdc are Øyvind's.

Co-author: Tore Ramsland <tore.ramsland@firmwaredesign.no>
Co-author: Tom Spyrou <tspyrou@precisioninno.com>

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

flow/designs/asap7/mock-cpu/config.mk

@@ -0,0 +1,15 @@
+export PLATFORM               = asap7
+
+export DESIGN_NAME            = mock_cpu
+export DESIGN_NICKNAME        = mock-cpu
+
+export VERILOG_FILES = $(wildcard ./designs/src/fifo/*.v)
+export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export CORE_UTILIZATION         = 40
+export CORE_ASPECT_RATIO        = 1
+export CORE_MARGIN              = 2
+export PLACE_DENSITY            = 0.71
+export TNS_END_PERCENT          = 100
+
+export IO_CONSTRAINTS        = designs/asap7/mock-cpu/io.tcl

flow/designs/asap7/mock-cpu/constraint.sdc

@@ -0,0 +1,49 @@
+# https://gist.github.com/brabect1/7695ead3d79be47576890bbcd61fe426
+#
+# This fifo is from http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
+
+source designs/src/mock-array/util.tcl
+
+set sdc_version 2.0
+
+set clk_period 333
+set clk2_period 1000
+
+set clk1_name clk
+create_clock -name $clk1_name -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk1_name]
+set_clock_uncertainty 10 [get_clocks $clk1_name]
+
+set clk2_name clk_uncore
+create_clock -name $clk2_name -period $clk2_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk2_name]
+set_clock_uncertainty 10 [get_clocks $clk2_name]
+set_clock_groups -group $clk1_name -group $clk2_name -asynchronous -allow_paths
+
+set_false_path -from [get_ports *rst_n]
+set_false_path -to [get_ports *rst_n]
+
+# Give the world outside of the FIFO time to operate
+# on the cycle it is reading/writiing to the FIFO
+set min_percent 0.1
+set max_percent 0.5
+
+set_input_delay -clock $clk2_name -max [expr $clk2_period * $max_percent] [match_pins .* input 0]
+set_output_delay -clock $clk2_name -max [expr $clk2_period * $max_percent] [match_pins .* output 0]
+set_input_delay -clock $clk2_name -min [expr $clk2_period * $min_percent] [match_pins .* input 0]
+set_output_delay -clock $clk2_name -min [expr $clk2_period * $min_percent] [match_pins .* output 0]
+
+## Dual clock fifo timing constraints
+# Using fastest clock as constaint
+set cdc_max_delay $clk_period
+
+# rdata from fifo_out goes directly to I/O-pins so we need special handling of this case
+# to ignore timing path from wclk -> rdata for this special case
+# In normal cases fifo output (rdata) will most likely have a FF on I/O output signal
+set_false_path -from $clk1_name -to [match_pins rdata* output 0]
+
+# Set timing constraint between clock domains
+set_max_delay $cdc_max_delay -from $clk1_name -to $clk2_name -ignore_clock_latency
+set_max_delay $cdc_max_delay -from $clk2_name -to $clk1_name -ignore_clock_latency
+
+# Hold times between clock domain makes no sense, and should just be ignored
+set_false_path -hold -from $clk1_name -to $clk2_name
+set_false_path -hold -from $clk2_name -to $clk1_name

flow/designs/asap7/mock-cpu/io.tcl

@@ -0,0 +1,3 @@
+source designs/src/mock-array/util.tcl
+
+set_io_pin_constraint -order -group -region bottom:* -pin_names [concat [match_pins .*] [match_pins clk input 1]]

flow/designs/asap7/mock-cpu/rules-base.json

@@ -0,0 +1,58 @@
+{
+    "synth__design__instance__area__stdcell": {
+        "value": 7302.54,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 2,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 7995,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 46274,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 530,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 530,
+        "compare": "<="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 58965,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -4.01,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 8127,
+        "compare": "<="
+    },
+    "finish__timing__drv__setup_violation_count": {
+        "value": 265,
+        "compare": "<="
+    },
+    "finish__timing__drv__hold_violation_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__wns_percent_delay": {
+        "value": -10.0,
+        "compare": ">="
+    }
+}

flow/designs/src/fifo/.gitignore

@@ -0,0 +1,2 @@
+*.vcd
+*.vvp

flow/designs/src/fifo/LICENSE

@@ -0,0 +1,3 @@
+From http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf.
+
+No license or warranty is described in the paper.

flow/designs/src/fifo/fifo.v

@@ -0,0 +1,25 @@
+module fifo (
+    output [31:0] rdata,
+    output wfull,
+    output rempty,
+    input [31:0] wdata,
+    input winc, wclk, wrst_n,
+    input rinc, rclk, rrst_n
+);
+
+    fifo1 #(
+        .DSIZE(32),
+        .ASIZE(5)
+    ) fifo_instance (
+        .rdata(rdata),
+        .wfull(wfull),
+        .rempty(rempty),
+        .wdata(wdata),
+        .winc(winc),
+        .wclk(wclk),
+        .wrst_n(wrst_n),
+        .rinc(rinc),
+        .rclk(rclk),
+        .rrst_n(rrst_n)
+    );
+endmodule

flow/designs/src/fifo/fifo1.v

@@ -0,0 +1,57 @@
+module fifo1 #(
+    parameter DSIZE = 8,
+    parameter ASIZE = 4
+) (
+    output [DSIZE-1:0] rdata,
+    output wfull,
+    output rempty,
+    input [DSIZE-1:0] wdata,
+    input winc,
+    wclk,
+    wrst_n,
+    input rinc,
+    rclk,
+    rrst_n
+);
+  wire [ASIZE-1:0] waddr, raddr;
+  wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
+  sync_r2w #(ASIZE) sync_r2w (
+      .wq2_rptr(wq2_rptr),
+      .rptr(rptr),
+      .wclk(wclk),
+      .wrst_n(wrst_n)
+  );
+  sync_w2r #(ASIZE) sync_w2r (
+      .rq2_wptr(rq2_wptr),
+      .wptr(wptr),
+      .rclk(rclk),
+      .rrst_n(rrst_n)
+  );
+  fifomem #(DSIZE, ASIZE) fifomem (
+      .rdata (rdata),
+      .wdata (wdata),
+      .waddr (waddr),
+      .raddr (raddr),
+      .wclken(winc),
+      .wfull (wfull),
+      .wclk  (wclk)
+  );
+  rptr_empty #(ASIZE) rptr_empty (
+      .rempty(rempty),
+      .raddr(raddr),
+      .rptr(rptr),
+      .rq2_wptr(rq2_wptr),
+      .rinc(rinc),
+      .rclk(rclk),
+      .rrst_n(rrst_n)
+  );
+  wptr_full #(ASIZE) wptr_full (
+      .wfull(wfull),
+      .waddr(waddr),
+      .wptr(wptr),
+      .wq2_rptr(wq2_rptr),
+      .winc(winc),
+      .wclk(wclk),
+      .wrst_n(wrst_n)
+  );
+endmodule

flow/designs/src/fifo/fifomem.v

@@ -0,0 +1,32 @@
+module fifomem #(
+    parameter DATASIZE = 8,  // Memory data word width
+    parameter ADDRSIZE = 4
+)  // Number of mem address bits
+(
+    output [DATASIZE-1:0] rdata,
+    input [DATASIZE-1:0] wdata,
+    input [ADDRSIZE-1:0] waddr,
+    raddr,
+    input wclken,
+    wfull,
+    wclk
+);
+`ifdef VENDORRAM
+  // instantiation of a vendor's dual-port RAM
+  vendor_ram mem (
+      .dout(rdata),
+      .din(wdata),
+      .waddr(waddr),
+      .raddr(raddr),
+      .wclken(wclken),
+      .wclken_n(wfull),
+      .clk(wclk)
+  );
+`else
+  // RTL Verilog memory model
+  localparam DEPTH = 1 << ADDRSIZE;
+  reg [DATASIZE-1:0] mem[0:DEPTH-1];
+  assign rdata = mem[raddr];
+  always @(posedge wclk) if (wclken && !wfull) mem[waddr] <= wdata;
+`endif
+endmodule

flow/designs/src/fifo/mock_cpu.v

@@ -0,0 +1,71 @@
+// a mock CPU. The inputs and outputs are disconnected from the
+// outside world via FIFOs to deal with a large clock insertion
+// latency of the CPU core.
+//
+// One input FIFO and one output FIFO are used. The input FIFOs
+// upper and lower bits are multiplied with 4 pipeline stages
+// and output on the output FIFO.
+//
+// ASIZE 3 and DSIZE 32 are used for the FIFOs.
+module mock_cpu (
+    output [31:0] rdata,
+    output wfull,
+    output rempty,
+    input [31:0] wdata,
+    input winc, wrst_n,
+    input rinc, clk, clk_uncore, rrst_n
+);
+    parameter STAGES = 1024;
+
+    reg [31:0] mult_result [0:STAGES - 1];
+    reg winc_out [0:STAGES - 1];
+
+    wire [31:0] wdata_out;
+    wire [31:0] rdata_in;
+    wire rinc_in, rempty_in;
+    wire wfull_out;
+
+    fifo1 #(.ASIZE(1), .DSIZE(32)) fifo_in (
+        .wdata(wdata),
+        .winc(winc),
+        .wfull(wfull),
+        .rclk(clk),
+        .wclk(clk_uncore),
+        .wrst_n(wrst_n),
+        .rrst_n(rrst_n),
+        .rdata(rdata_in),
+        .rinc(rinc_in),
+        .rempty(rempty_in)
+    );
+
+    fifo1 #(.ASIZE(3), .DSIZE(32)) fifo_out (
+        .wdata(mult_result[STAGES - 1]),
+        .winc(winc_out[STAGES - 1]),
+        .wfull(wfull_out),
+        .rclk(clk_uncore),
+        .wclk(clk),
+        .wrst_n(wrst_n),
+        .rrst_n(rrst_n),
+        .rdata(rdata),
+        .rinc(rinc),
+        .rempty(rempty)
+    );
+
+    assign rinc_in = !rempty_in;
+
+    generate
+        genvar i;
+        for (i = 0; i < STAGES; i=i+1) begin : mult_pipeline
+            always @(posedge clk) begin
+                if (i == 0) begin
+                    mult_result[i] <= rdata_in[15:0] + rdata_in[31:16];
+                    winc_out[i] <= !rempty_in;
+                end else begin
+                    mult_result[i] <= mult_result[i-1];
+                    winc_out[i] <= winc_out[i-1];
+                end
+            end
+        end
+    endgenerate
+
+endmodule