.gitignore

#########################################################################################################
##	This is an example .gitignore file for Vivado, please treat it as an example as 
##	it might not be complete. In addition, XAPP 1165 should be followed.
#########################################################################################################

#############
# Exclude all
*
!*/
!.gitignore
################
## Source files:
# Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.sv
# !*.bd
# !*.edif
###########
## IP files
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
#.xci + .dcp: implementation possible but not re-synthesis
#*.xci(www.spiritconsortium.org)
!*.xci
#*.dcp(checkpoint files)
# !*.dcp
# !*.vds
# !*.pb
# All bd comments and layout coordinates are stored within .ui
# !*.ui
# !*.ooc
###################
## System Generator
# !*.mdl
# !*.slx
# !*.bxml
############################
## Simulation logic analyzer
# !*.wcfg
!*.coe
######
## MIG
# !*.prj
!*.mem
################
## Project files
# XPR  +  *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
# Do NOT ignore *.xpr files
# !*.xpr
# Include *.xml files for 2013.4 or earlier version
# !*.xml
###################
## Constraint files
# Do NOT ignore *.xdc files
!*.xdc
#############
# TCL - files
!*.tcl
##################
## Journal - files
# !*.jou
##########
## Reports
# !*.rpt
!*.txt
# !*.vdi
##########
## C-files
!*.c
!*.h
!*.elf
# !*.bmm
# !*.xmp
##########
## Python files
!*.py

# ignoring files provided by ARM DesignStart program
modules/cortex-m0/verilog/CORTEXM0INTEGRATION.v
modules/cortex-m0/verilog/cortexm0ds_logic.v