From 0e5c808d36ee25b0399d106ba39355080da647b6 Mon Sep 17 00:00:00 2001
From: Tropical <42101043+Tropix126@users.noreply.github.com>
Date: Sat, 31 Aug 2024 00:02:50 -0500
Subject: [PATCH] refactor: simplify interrupt enable asm

---
 packages/kernel/src/main.rs | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/packages/kernel/src/main.rs b/packages/kernel/src/main.rs
index e7da994..06623b4 100644
--- a/packages/kernel/src/main.rs
+++ b/packages/kernel/src/main.rs
@@ -18,6 +18,7 @@ pub mod xil;
 use log::LevelFilter;
 use logger::KernelLogger;
 use peripherals::{GIC, PRIVATE_TIMER, UART1, WATCHDOG_TIMER};
+use sdk::vexSystemTimeGet;
 use vex_v5_qemu_protocol::{code_signature::CodeSignature, HostBoundPacket};
 
 extern "C" {
@@ -59,12 +60,6 @@ pub extern "C" fn _start() -> ! {
         // `vectors` module.
         vectors::set_vbar(core::ptr::addr_of!(VECTORS_START) as u32);
 
-        // Enable IRQ and FIQ interrupts by masking CPSR with the IRQ and FIQ enable bits.
-        core::arch::asm!(
-            "mrs r1, cpsr
-             bic r1, r1, #0b11000000
-             msr cpsr_c, r1"
-            , options(nomem, nostack));
 
         // Register SDK exception handlers for data/prefetch/undefined aborts.
         vectors::register_sdk_exception_handlers();
@@ -75,6 +70,9 @@ pub extern "C" fn _start() -> ! {
         // Enable MMU
         hardware::mmu::enable_mmu();
 
+        // Enable IRQ and FIQ interrupts by masking CPSR with the IRQ and FIQ enable bits.
+        core::arch::asm!("cpsie if");
+
         // Initialize heap memory
         allocator::init_heap();
     }