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I was trying to test RepCut with RISCV-BOOM designs other than current artifacts from Zenodo.
The latest version of Chipyard which supports FIRRTL 1.4.3 is 1.4.0. However, Chipyard 1.4.0 has a lot of trouble producing the FIR files (ref1, ref2).
The text was updated successfully, but these errors were encountered:
Yes we do have plan to support higher FIRRTL version. In fact, the patch that bumps up FIRRTL on Essent (patch #21 ) should also works for repcut branch. This patch is not integrated into repcut branch yet but can be merged by:
This patch bumps FIRRTL to 1.5.6. You should be able to build by sbt assembly.
FIRRTL 1.5.6 is the last stable version of Scala FIRRTL compiler. Since Chisel 3.6.0 the backend moved to CIRCT, deprecating Scala compiler (See release note of FIRRTL: https://github.com/chipsalliance/firrtl). As the result, we won't be able to bump to higher FIRRTL. 1.5.6 is likely to be the version we will stay for long term.
If you wish to run Chipyard design please also modify the TestHarness or ChipTop module, remove analog pins and avoid multiple clock domain. They are not supported.
I noticed current RepCut only supports FIRRTL with 1.4.3
while Essent supports FIRRTL with FIRRTL 1.5.6
I was trying to test RepCut with RISCV-BOOM designs other than current artifacts from Zenodo.
The latest version of Chipyard which supports FIRRTL 1.4.3 is 1.4.0. However, Chipyard 1.4.0 has a lot of trouble producing the FIR files (ref1, ref2).
The text was updated successfully, but these errors were encountered: