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Add write queue valid check
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hansungk committed Nov 10, 2024
1 parent 2916cde commit dd8b74e
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions src/main/scala/gemmini/Scratchpad.scala
Original file line number Diff line number Diff line change
Expand Up @@ -542,8 +542,8 @@ class Scratchpad[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T,
bio.read.resp.ready := Mux(bio.read.resp.bits.fromDMA, dma_read_resp.ready, ex_read_resp.ready)

dma_read_pipe.io.deq.ready := writer.module.io.req.ready && spad_writer.module.io.req.ready &&
!write_issue_q.io.deq.bits.laddr.is_acc_addr && write_issue_q.io.deq.bits.laddr.sp_bank() === i.U && // I believe we don't need to check that write_issue_q is valid here, because if the SRAM's resp is valid, then that means that the write_issue_q's deq should also be valid
!write_issue_q.io.deq.bits.laddr.is_garbage()
(!write_issue_q.io.deq.bits.laddr.is_acc_addr && write_issue_q.io.deq.bits.laddr.sp_bank() === i.U && // I believe we don't need to check that write_issue_q is valid here, because if the SRAM's resp is valid, then that means that the write_issue_q's deq should also be valid
write_issue_q.io.deq.valid) && !write_issue_q.io.deq.bits.laddr.is_garbage()
when (dma_read_pipe.io.deq.fire) {
writeData.valid := true.B
writeData.bits := dma_read_pipe.io.deq.bits.data
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