TraceDoctor

.gitmodules

@@ -1,9 +1,9 @@
 [submodule "rocket-chip"]
 	path = generators/rocket-chip
-	url = https://github.com/chipsalliance/rocket-chip.git
+	url = https://github.com/EECS-NTNU/rocket-chip.git
 [submodule "testchipip"]
 	path = generators/testchipip
-	url = https://github.com/ucb-bar/testchipip.git
+	url = https://github.com/EECS-NTNU/testchipip.git
 [submodule "barstools"]
 	path = tools/barstools
 	url = https://github.com/ucb-bar/barstools.git
@@ -12,7 +12,7 @@
 	url = https://github.com/ucb-bar/riscv-torture.git
 [submodule "generators/boom"]
 	path = generators/boom
-	url = https://github.com/riscv-boom/riscv-boom.git
+	url = https://github.com/EECS-NTNU/riscv-boom.git
 [submodule "generators/sifive-blocks"]
 	path = generators/sifive-blocks
 	url = https://github.com/chipsalliance/rocket-chip-blocks.git
@@ -21,7 +21,7 @@
 	url = https://github.com/ucb-bar/hwacha.git
 [submodule "sims/firesim"]
 	path = sims/firesim
-	url = https://github.com/firesim/firesim.git
+	url = https://github.com/EECS-NTNU/firesim.git
 [submodule "generators/icenet"]
 	path = generators/icenet
 	url = https://github.com/firesim/icenet.git

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -16,6 +16,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
   with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register
   with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
+  with testchipip.CanHaveTraceDoctorIO // Enables optionally adding trace IO
   with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
   with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
   with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
@@ -40,6 +41,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
 
 class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
   with testchipip.CanHaveTraceIOModuleImp
+  with testchipip.CanHaveTraceDoctorIOModuleImp
   with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
   with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
   with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp

generators/chipyard/src/main/scala/IOBinders.scala

@@ -373,6 +373,17 @@ class WithTraceIOPunchthrough extends OverrideIOBinder({
   }
 })
 
+class WithTraceDoctorIOPunchthrough extends OverrideIOBinder({
+  (system: CanHaveTraceDoctorIOModuleImp) => {
+    val ports: Option[TraceDoctorOutputTop] = system.traceDoctorIO.map { t =>
+      val trace = IO(DataMirror.internal.chiselTypeClone[TraceDoctorOutputTop](t)).suggestName("tracedoctor")
+      trace <> t
+      trace
+    }
+    (ports.toSeq, Nil)
+  }
+})
+
 class WithCustomBootPin extends OverrideIOBinder({
   (system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p =>
     val sys = system.asInstanceOf[BaseSubsystem]

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -37,6 +37,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithGPIOCells ++
   new chipyard.iobinders.WithSPIIOCells ++
   new chipyard.iobinders.WithTraceIOPunchthrough ++
+  new chipyard.iobinders.WithTraceDoctorIOPunchthrough ++
   new chipyard.iobinders.WithExtInterruptIOCells ++
   new chipyard.iobinders.WithCustomBootPin ++
   new chipyard.iobinders.WithDividerOnlyClockGenerator ++

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -33,6 +33,17 @@ class WithTraceIO extends Config((site, here, up) => {
   case TracePortKey => Some(TracePortParams())
 })
 
+class WithTraceDoctorIO(traceWidth: Int = 512) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(setTraceDoctorWidth = traceWidth)))
+    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(setTraceDoctorWidth = traceWidth)))
+    case other => other
+  }
+  case TraceDoctorPortKey => Some(TraceDoctorPortParams())
+})
+
 class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -184,6 +184,14 @@ class WithTracerVBridge extends ComposeHarnessBinder({
   }
 })
 
+class WithTraceDoctorBridge extends ComposeHarnessBinder({
+  (system: CanHaveTraceDoctorIOModuleImp, th: FireSim, ports: Seq[TraceDoctorOutputTop]) => {
+    ports.map { p => p.tracedoctors.map(tileTrace => TraceDoctorBridge(tileTrace)(system.p)) }
+    Nil
+  }
+})
+
+
 class WithDromajoBridge extends ComposeHarnessBinder({
   (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) =>
     ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil
@@ -240,5 +248,6 @@ class WithDefaultFireSimBridges extends Config(
   new WithFireSimMultiCycleRegfile ++
   new WithFireSimFAME5 ++
   new WithTracerVBridge ++
+  new WithTraceDoctorBridge ++
   new WithFireSimIOCellModels
 )

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -1,26 +1,25 @@
 package firesim.firesim
 
 import java.io.File
-
 import chisel3._
-import chisel3.util.{log2Up}
-import freechips.rocketchip.config.{Parameters, Config}
+import chisel3.util.log2Up
+import freechips.rocketchip.config.{Config, Parameters}
 import freechips.rocketchip.groundtest.TraceGenParams
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
-import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
-import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
-import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams}
+import freechips.rocketchip.devices.debug.{DebugModuleKey, DebugModuleParams}
+import freechips.rocketchip.diplomacy.{AsynchronousCrossing, LazyModule}
+import testchipip.{BlockDeviceConfig, BlockDeviceKey, TracePortKey, TracePortParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
-import scala.math.{min, max}
 
-import chipyard.clocking.{ChipyardPRCIControlKey}
+import scala.math.{max, min}
+import chipyard.clocking.ChipyardPRCIControlKey
+import chipyard.config.WithTraceDoctorIO
 import icenet._
 import testchipip.WithRingSystemBus
-
 import firesim.bridges._
 import firesim.configs._
 
@@ -79,6 +78,7 @@ class WithFireSimDesignTweaks extends Config(
   new WithoutTLMonitors ++
   // Optional: Adds IO to attach tracerV bridges
   new chipyard.config.WithTraceIO ++
+  new chipyard.config.WithTraceDoctorIO ++
   // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
   new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
   // Optional: Removing this will require using an initramfs under linux
@@ -109,7 +109,7 @@ class WithFireSimHighPerfClocking extends Config(
 // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
 class WithFireSimConfigTweaks extends Config(
   // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)
-  // Using some other frequency will require runnings the FASED runtime configuration generator 
+  // Using some other frequency will require runnings the FASED runtime configuration generator
   // to generate faithful DDR3 timing values.
   new chipyard.config.WithSystemBusFrequency(1000.0) ++
   new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (1000 MHz)
@@ -175,6 +175,16 @@ class FireSimSmallSystemConfig extends Config(
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
   new chipyard.RocketConfig)
 
+
+//*****************************************************************
+// Boom config, base off chipyard's SmallBoomConfig
+//*****************************************************************
+class FireSimSmallBoomConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.SmallBoomConfig)
+
 //*****************************************************************
 // Boom config, base off chipyard's LargeBoomConfig
 //*****************************************************************