From c66243d32d39762794f847d999df2407c083f9bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= Date: Fri, 25 Nov 2022 13:22:22 +0100 Subject: [PATCH 1/7] * initial tracedoctor 1.15.1 commit --- .gitmodules | 8 ++--- generators/boom | 2 +- .../chipyard/src/main/scala/DigitalTop.scala | 2 ++ .../chipyard/src/main/scala/IOBinders.scala | 11 +++++++ .../main/scala/config/AbstractConfig.scala | 1 + .../config/fragments/TileFragments.scala | 11 +++++++ .../src/main/scala/BridgeBinders.scala | 11 ++++++- .../src/main/scala/TargetConfigs.scala | 32 ++++++++++++------- generators/rocket-chip | 2 +- generators/testchipip | 2 +- sims/firesim | 2 +- 11 files changed, 64 insertions(+), 20 deletions(-) diff --git a/.gitmodules b/.gitmodules index 45f0bc5058..302a7688fe 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,9 @@ [submodule "rocket-chip"] path = generators/rocket-chip - url = https://github.com/chipsalliance/rocket-chip.git + url = https://github.com/EECS-NTNU/rocket-chip.git [submodule "testchipip"] path = generators/testchipip - url = https://github.com/ucb-bar/testchipip.git + url = https://github.com/EECS-NTNU/testchipip.git [submodule "barstools"] path = tools/barstools url = https://github.com/ucb-bar/barstools.git @@ -12,7 +12,7 @@ url = https://github.com/ucb-bar/riscv-torture.git [submodule "generators/boom"] path = generators/boom - url = https://github.com/riscv-boom/riscv-boom.git + url = https://github.com/EECS-NTNU/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks url = https://github.com/chipsalliance/rocket-chip-blocks.git @@ -21,7 +21,7 @@ url = https://github.com/ucb-bar/hwacha.git [submodule "sims/firesim"] path = sims/firesim - url = https://github.com/firesim/firesim.git + url = https://github.com/EECS-NTNU/firesim.git [submodule "generators/icenet"] path = generators/icenet url = https://github.com/firesim/icenet.git diff --git a/generators/boom b/generators/boom index fac2c370c9..3c55e4c15c 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit fac2c370c9deae97ca52aca6b34857e9ac0f6e9d +Subproject commit 3c55e4c15c0be4661a5730c2c9f705fba3470a7c diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 2777ba3608..d8576c0a5d 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -16,6 +16,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHaveTraceIO // Enables optionally adding trace IO + with testchipip.CanHaveTraceDoctorIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter @@ -40,6 +41,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp + with testchipip.CanHaveTraceDoctorIOModuleImp with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 1903ddc355..167fb462c9 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -373,6 +373,17 @@ class WithTraceIOPunchthrough extends OverrideIOBinder({ } }) +class WithTraceDoctorIOPunchthrough extends OverrideIOBinder({ + (system: CanHaveTraceDoctorIOModuleImp) => { + val ports: Option[TraceDoctorOutputTop] = system.traceDoctorIO.map { t => + val trace = IO(DataMirror.internal.chiselTypeClone[TraceDoctorOutputTop](t)).suggestName("tracedoctor") + trace <> t + trace + } + (ports.toSeq, Nil) + } +}) + class WithCustomBootPin extends OverrideIOBinder({ (system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p => val sys = system.asInstanceOf[BaseSubsystem] diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 1f43dcbf2a..d729015aea 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -37,6 +37,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithGPIOCells ++ new chipyard.iobinders.WithSPIIOCells ++ new chipyard.iobinders.WithTraceIOPunchthrough ++ + new chipyard.iobinders.WithTraceDoctorIOPunchthrough ++ new chipyard.iobinders.WithExtInterruptIOCells ++ new chipyard.iobinders.WithCustomBootPin ++ new chipyard.iobinders.WithDividerOnlyClockGenerator ++ diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 906f2a9508..99f369745c 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -33,6 +33,17 @@ class WithTraceIO extends Config((site, here, up) => { case TracePortKey => Some(TracePortParams()) }) +class WithTraceDoctorIO(traceWidth: Int = 512) extends Config((site, here, up) => { + case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { + case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(setTraceDoctorWidth = traceWidth))) + case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( + core = tp.tileParams.core.copy(setTraceDoctorWidth = traceWidth))) + case other => other + } + case TraceDoctorPortKey => Some(TraceDoctorPortParams()) +}) + class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index bf1ff6805d..9663bbd883 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -184,6 +184,14 @@ class WithTracerVBridge extends ComposeHarnessBinder({ } }) +class WithTraceDoctorBridge extends ComposeHarnessBinder({ + (system: CanHaveTraceDoctorIOModuleImp, th: FireSim, ports: Seq[TraceDoctorOutputTop]) => { + ports.map { p => p.tracedoctors.map(tileTrace => TraceDoctorBridge(tileTrace)(system.p)) } + Nil + } +}) + + class WithDromajoBridge extends ComposeHarnessBinder({ (system: CanHaveTraceIOModuleImp, th: FireSim, ports: Seq[TraceOutputTop]) => ports.map { p => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil @@ -239,6 +247,7 @@ class WithDefaultFireSimBridges extends Config( new WithFASEDBridge ++ new WithFireSimMultiCycleRegfile ++ new WithFireSimFAME5 ++ - new WithTracerVBridge ++ +// new WithTracerVBridge ++ + new WithTraceDoctorBridge ++ new WithFireSimIOCellModels ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 76a2f11412..c1f3bccad5 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -1,26 +1,25 @@ package firesim.firesim import java.io.File - import chisel3._ -import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Parameters, Config} +import chisel3.util.log2Up +import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.groundtest.TraceGenParams import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} -import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} -import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing} -import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams} +import freechips.rocketchip.devices.debug.{DebugModuleKey, DebugModuleParams} +import freechips.rocketchip.diplomacy.{AsynchronousCrossing, LazyModule} +import testchipip.{BlockDeviceConfig, BlockDeviceKey, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} -import scala.math.{min, max} -import chipyard.clocking.{ChipyardPRCIControlKey} +import scala.math.{max, min} +import chipyard.clocking.ChipyardPRCIControlKey +import chipyard.config.WithTraceDoctorIO import icenet._ import testchipip.WithRingSystemBus - import firesim.bridges._ import firesim.configs._ @@ -78,7 +77,8 @@ class WithFireSimDesignTweaks extends Config( // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) new WithoutTLMonitors ++ // Optional: Adds IO to attach tracerV bridges - new chipyard.config.WithTraceIO ++ + // new chipyard.config.WithTraceIO ++ + new chipyard.config.WithTraceDoctorIO ++ // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1) new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // Optional: Removing this will require using an initramfs under linux @@ -109,7 +109,7 @@ class WithFireSimHighPerfClocking extends Config( // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz class WithFireSimConfigTweaks extends Config( // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency) - // Using some other frequency will require runnings the FASED runtime configuration generator + // Using some other frequency will require runnings the FASED runtime configuration generator // to generate faithful DDR3 timing values. new chipyard.config.WithSystemBusFrequency(1000.0) ++ new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (1000 MHz) @@ -175,6 +175,16 @@ class FireSimSmallSystemConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ new chipyard.RocketConfig) + +//***************************************************************** +// Boom config, base off chipyard's SmallBoomConfig +//***************************************************************** +class FireSimSmallBoomConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.SmallBoomConfig) + //***************************************************************** // Boom config, base off chipyard's LargeBoomConfig //***************************************************************** diff --git a/generators/rocket-chip b/generators/rocket-chip index 44b0b82492..0f830c53aa 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 44b0b8249279d25bd75ea693b725d9ff1b96e2ab +Subproject commit 0f830c53aa5ef7960a1a7e52095d55d0bb39830c diff --git a/generators/testchipip b/generators/testchipip index f99b1eb59a..7de2c945db 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit f99b1eb59a34d7934059904f03237d5bc8d4a680 +Subproject commit 7de2c945dbad989615befb7cf2ba446ecf870a05 diff --git a/sims/firesim b/sims/firesim index 8176b657ee..5e7268546c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 8176b657ee779ac4901b6b03aea0ac23a0b8874d +Subproject commit 5e7268546cfd1ca0a06adfe2484437e07ca0cb0a From 7fc6b841fd530a5589073da33c2f09a49ad0eb9c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= Date: Wed, 14 Dec 2022 14:37:45 +0100 Subject: [PATCH 2/7] * tracedoctor support for the TracerV trigger --- generators/firechip/src/main/scala/BridgeBinders.scala | 2 +- generators/firechip/src/main/scala/TargetConfigs.scala | 2 +- generators/rocket-chip | 2 +- generators/testchipip | 2 +- sims/firesim | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 9663bbd883..891a323b23 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -247,7 +247,7 @@ class WithDefaultFireSimBridges extends Config( new WithFASEDBridge ++ new WithFireSimMultiCycleRegfile ++ new WithFireSimFAME5 ++ -// new WithTracerVBridge ++ + new WithTracerVBridge ++ new WithTraceDoctorBridge ++ new WithFireSimIOCellModels ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index c1f3bccad5..8e983afb22 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -77,7 +77,7 @@ class WithFireSimDesignTweaks extends Config( // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) new WithoutTLMonitors ++ // Optional: Adds IO to attach tracerV bridges - // new chipyard.config.WithTraceIO ++ + new chipyard.config.WithTraceIO ++ new chipyard.config.WithTraceDoctorIO ++ // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1) new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ diff --git a/generators/rocket-chip b/generators/rocket-chip index 0f830c53aa..408122012e 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 0f830c53aa5ef7960a1a7e52095d55d0bb39830c +Subproject commit 408122012ea570c4edbd5048924276a78f7aa36f diff --git a/generators/testchipip b/generators/testchipip index 7de2c945db..425ac59f12 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 7de2c945dbad989615befb7cf2ba446ecf870a05 +Subproject commit 425ac59f126a5d9f822badc623ef3e232abc1ece diff --git a/sims/firesim b/sims/firesim index 5e7268546c..79db340c7c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 5e7268546cfd1ca0a06adfe2484437e07ca0cb0a +Subproject commit 79db340c7c93ba5d857840b58024df587da80cb3 From 6839f41a253be6fcc05cac4886fc592877048401 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= Date: Tue, 28 Feb 2023 16:21:05 +0100 Subject: [PATCH 3/7] * TraceDoctor update, default multithreading and updated example code supports FirePerf --- generators/boom | 2 +- generators/rocket-chip | 2 +- sims/firesim | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/boom b/generators/boom index 3c55e4c15c..bc365be0a3 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 3c55e4c15c0be4661a5730c2c9f705fba3470a7c +Subproject commit bc365be0a3f5ba70756d06c92db31c0307fb58f1 diff --git a/generators/rocket-chip b/generators/rocket-chip index 408122012e..2f8d0728dd 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 408122012ea570c4edbd5048924276a78f7aa36f +Subproject commit 2f8d0728dd49afbd0491f0ad0b16b33e4babf4e6 diff --git a/sims/firesim b/sims/firesim index 79db340c7c..ec9f6a3c0f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 79db340c7c93ba5d857840b58024df587da80cb3 +Subproject commit ec9f6a3c0fc171fa5ebe2f24c878451b4f1e4ab8 From e569fea02638bb930b5397034ed57519468d6979 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= Date: Wed, 12 Apr 2023 10:57:55 +0200 Subject: [PATCH 4/7] * cleanup --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index ec9f6a3c0f..e53cb0a246 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ec9f6a3c0fc171fa5ebe2f24c878451b4f1e4ab8 +Subproject commit e53cb0a246918fe11697465431e80c90a77f5ff0 From c6fd87d15820d89bbe8375aab471a1c2d872f46b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= Date: Mon, 17 Apr 2023 16:20:17 +0200 Subject: [PATCH 5/7] * TraceDoctor driver update --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index e53cb0a246..28ca0c65e5 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e53cb0a246918fe11697465431e80c90a77f5ff0 +Subproject commit 28ca0c65e589932bb7c29d0d518a18b6268a5bea From 3331c784e4884da817b904248a589559b1fabdf0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= Date: Tue, 18 Apr 2023 13:21:01 +0200 Subject: [PATCH 6/7] * pushed TraceDoctor driver --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 28ca0c65e5..e1708b5cb8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 28ca0c65e589932bb7c29d0d518a18b6268a5bea +Subproject commit e1708b5cb8df6bb1dbc5bf664e840877d7835ba2 From bd0473d37e9d1a9e0758be59fcde95ec4897b86d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Gottschall?= Date: Thu, 20 Apr 2023 16:34:31 +0200 Subject: [PATCH 7/7] * fixed compression command bug --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index e1708b5cb8..398e5bb572 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e1708b5cb8df6bb1dbc5bf664e840877d7835ba2 +Subproject commit 398e5bb572a4b81ff21bf9ed9c599f403eb6cde8