An example of how to use the Xilinx ISE toolchain from the command line
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Jun 30, 2019 - Makefile
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xilinx-ise
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This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
calculator vhdl matrix-multiplication verilog xilinx hardware-designs xilinx-fpga low-level-programming xilinx-ise xilinx-vivado ic-design
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Aug 12, 2017 - Verilog
My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)
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Jun 1, 2020 - VHDL
This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools
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Aug 5, 2023 - Verilog
FPGA Tetris written in Verilog
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Apr 26, 2018 - Verilog
A Verilog based Fractal Set Generator for the Xilinx Artix 7
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Dec 10, 2021 - Verilog
The Repository contains the code of various Digital Circuits
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Aug 7, 2023 - Verilog
Tiny 4-bit CPU using AMD2901 bit slice (https://github.com/Amrnasr/AM2901) and program memory initialized from a file
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Apr 2, 2017 - VHDL
Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo
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Dec 10, 2020 - C++
An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
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Jul 27, 2020 - Verilog
Digital System Design Project - Spring 2020
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Aug 7, 2020 - Verilog
Simple system built around VHDL implementation of Am9080 8-bit CPU based on 29XX bit-slice series of devices, as described here: https://en.wikichip.org/w/images/7/76/An_Emulation_of_the_Am9080A.pdf
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Mar 31, 2024 - VHDL
A single cycle CPU running MIPS instructions on Xilinx FPGA
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Aug 27, 2017 - Verilog
16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)
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Dec 30, 2019 - Verilog
This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.
fpga architecture vhdl xilinx vivado xilinx-fpga xilinx-ise basys3 lfsr xilinx-vivado hand-eye-coordination
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Nov 29, 2017 - VHDL
Simple Ping Pong game on Xilinx Spartan 3E
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Apr 29, 2022 - HTML
RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.
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Sep 3, 2020 - Verilog
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Jul 12, 2021 - Verilog
16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board
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Dec 16, 2022 - C
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