vliw
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This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction scheduling.
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May 14, 2021 - Verilog
A Python - Verilog combination that simulates the working of a 32-bit 5-stage pipelined VLIW processor from input assembly code while monitoring the updates in the processor register file.
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Apr 30, 2021 - Verilog
CS-470 Homework 2
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May 4, 2024 - Python
Source code for the TM32 disassembler created by asbokid https://sourceforge.net/projects/tm32dis/
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May 9, 2019 - C
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