Design and analysis of 6T SRAM memory cells using LTspice. Analysis of noise margin, Vdd scaling and data retention voltage for design optimization.
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Updated
Mar 26, 2024 - Python
Design and analysis of 6T SRAM memory cells using LTspice. Analysis of noise margin, Vdd scaling and data retention voltage for design optimization.
Repositório dedicado as disciplinas lecionadas pelo Professor Giuliano Bertoti
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