Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
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Dec 19, 2021 - Verilog
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reproducible-computation
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Presentation about the targets R package at the Los Angeles R Users Group Meetup
workflow r pipeline high-performance-computing make rstats reproducibility targets reproducible-computation
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Oct 25, 2020 - HTML
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