Miscellaneous stuff from the NDSU Digital Design Class
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Updated
Aug 5, 2017 - Mathematica
Miscellaneous stuff from the NDSU Digital Design Class
a quick interface to any digital device that features magazines as a product
Digital Design Timing Constraints
This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
This repository contains a few useful Verilog modules
For all the fidget spinneteers out there
PWM module using verilig HDL in XILINX ISE
4 bit divider design using first divider algorithm
Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.
Very simple Cortex-M1 SoC design based on ARM DesignStart
A repo to store the coursework I do in college! 🎓
RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
Took a module on Digital Design Fundamentals during my year 2 of my undergraduate studies of Electronic Circuits done using VHDL and Verilog, with a final project on FPGA Programmed Flappy Bird Gaming System using Sound and Light effects.
Basic digital lock system for safes, employing logic gates 🔐
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