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datapath-design

Here are 9 public repositories matching this topic...

mattiadane / Rock-Paper-Scissors-Circuit

University project about the game rock-paper-scissors

verilog sis datapath circuit systemverilog blif datapath-design fsm-designer

Updated Feb 19, 2024
SystemVerilog

skipfie / CPEN211

CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis

finite-state-machine ubc systemverilog university-course asic-design ubc-engineering datapath-design

Updated Oct 3, 2023
SystemVerilog

DavideTenediniPoliMi / RL_Project_21_22

This was the project assignment for the Digital Logic Design course.

fpga vhdl digital-logic digital-logic-design convolutional-encoder datapath-design

Updated Mar 24, 2023
VHDL

shahed22 / Architectural-Design-for-Bus-interface-connected-with-LFSR

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm

Updated May 28, 2024
Verilog

gautamop01 / CS211-Computer-Architecture

Learned as a part of Computer architecture Course

computer-science architecture mips-assembly verilog vivado datapath alu mips-architecture mips-processor qtspim cs211 computerarchitecture asembly flowcontrol dynamicmemory datapath-design datapath-analysis

Updated May 13, 2023
Assembly

LC2222a-ISA

tianrui-qi / LC2222a-ISA

Datapath and Control for a Turing Complete ISA with Interrupt Handling

microcontroller cpu networking system instructions logic isa datapath circuit interrupts lc-2200 datapath-design

Updated Sep 1, 2024
Python

Aledpl5 / Rock-Paper-Scissors-Circuit

Uni project about the game rock-paper-scissors

verilog sis datapath circuit systemverilog blif finate-state-machine datapath-design

Updated Feb 7, 2024
SystemVerilog

FarrukhAijaz / Single-Cycle-Multi-Cycle-and-Pipeline-ARM-Based-Processor-Design

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

processor-architecture arm processor verilog mcu computer-architecture hazard-detection pipeline-processor verilog-hdl 32-bit arm32 pipline processor-design single-cycle-processor multi-cycle-processor multi-cycle-cpu datapath-design

Updated Jun 28, 2024
Verilog

yanocavalcante / CTD-Jogo

Repositório para o trabalho final da disciplina de Circuitos e Técnicas Digitais do Prof. Héctor Pettenghi Roldán.

fpga vhdl datapath-design

Updated Nov 29, 2024
VHDL

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