Image Processing Toolbox in Verilog using Basys3 FPGA

⚙Hardware Synthesis Laboratory Using Verilog

A Single Cycle Risc-V 32 bit CPU

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

Single Cycle 32 bit MIPS

BASYS 3 - PONG GAME

👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

CS4362 - Hardware Description Languages. Implemented SNN on an FPGA for real-time image processing using VHDL

This repository has basic examples in VHDL using Basys3 board.

Morse Code Encoder on Basys 3 [Artix-7, part: xc7a35tcpg236-1]

Pulse generator on Basys 3 FPGA board

Digital clock implemented in vhdl for the Basys 3 Board from Digilent.

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

Color Detection using Basys3 FPGA

FPGA Audio Effect System project for Electronic Engineering course. This project spanned two semesters and was my final year project

Logic Analyzer IP Core

FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.

This is the repo is created for helping fellow Bilkenteers to pass their EEE102 Digital Electronics course. You can find Lab answers from Lab 1 to Final Project! Have fun!

A Sound and Sight Entertainment System (SSES) implemented on Basys3 FPGA Board