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May 19, 2024 - VHDL
asic-verification
Here are 19 public repositories matching this topic...
TCL examples from the Clif Flynt's classic
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Jan 24, 2018
A repo for small SVA examples
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Jan 8, 2018
High-Performance Binary Neural Networks for MNIST Classification: From Software to ASIC
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Jun 29, 2024 - VHDL
Moore.io Demo Project
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Mar 29, 2023 - SystemVerilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Oct 8, 2024 - SystemVerilog
Made Million Instruction Per Second Processor
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Feb 24, 2018
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
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May 6, 2023 - VHDL
Application Specific Integrated Circuit(ASIC)
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Jun 7, 2018 - SystemVerilog
Hdl is a tool for easing the work with hardware description languages.
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Dec 12, 2022 - Go
Quasar 2.0: Chisel equivalent of SweRV-EL2
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Apr 13, 2021 - Scala
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …
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Dec 3, 2023 - Verilog
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
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Oct 15, 2024 - VHDL
VIP for AXI Protocol
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May 24, 2022 - SystemVerilog
IC implementation of Systolic Array for TPU
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Mar 4, 2024 - Verilog
Awesome ASIC design verification
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Feb 9, 2022
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