The AC-63 is an 18-bit CPU designed
| Register | Purpose | Bits | Description |
|---|---|---|---|
| ACC | Accumumlator | 18 | Stores results of operations. |
| PC | Program Counter | 18 | Current location in memory of CPU. |
| GP1-3 | General Purpose | 18 | Three general purpose registers |
| SP | Stack Pointer | 18 | Allows function calls by storing address of the top of the stack |
OOOOIZRRXXXXXXXXXX
The 1st 4 bits of the word are the 4-bit opcode.
The 5th bit is the Addressing Mode bit. It specifies which addressing mode is used for this operation.
- Direct: Use the 10-bits directly
- Indirect: Use the 10-bits to construct a 18-bit address, which contains the operand
The 6th bit is the Zero or Page bit. It specifies how the additional 8 bits needed to make an 18 bit word are treated. This is essentially the paging bit.
- Filled with zeros.
- Uses the 8 high order bits of the PC.
The 7th and 8th bits are the Register Select bits. When zeroed no register is used, but when set to 1-3 they will alter the current operation to include a register.
The remaining 10 bits are the operand. As per the previous flags these will be used either directly, or to redirect
There are 16 base instructions.
Indirect addressing works as per above, and registers cannot be used for indirect addressing. If the value of the reg sel bits is 0, then they will not be used, however most operations are “Multi Function”, in that they will perform an additional step involving registers if the reg sel bits are set. All operations which additionally operate on a register can be run with an operand of 0, as if to operate only on the register
- A means operand section of word, commonly an address
- R means register specified by select bits
| Operation | Dec | Bin | Description | Reg step |
|---|---|---|---|---|
| NOP | 0 | 0000 | No Operation | |
| DAM R A | 1 | 0001 | Deposit ACC into A and clear ACC | |
| LDR R A | 2 | 0010 | Load A into R | n/a |
| DPR R A | 3 | 0011 | Deposit R into A | n/a |
| JMP R A | 4 | 0100 | Jump to A | Store return address in R |
| JEZ R A | 5 | 0101 | Jump to A if ACC = 0 | Store return address in R |
| JNZ R A | 6 | 0110 | Jump to A if ACC != 0 | Store return address in R |
| SHL A | 7 | 0111 | binary shift A left, store in ACC | |
| SHR A | 8 | 1000 | binary shift A right, store in ACC | |
| AND A | 9 | 1001 | binary and A with ACC | |
| OR A | 10 | 1010 | binary OR A with ACC | |
| ADD R A | 11 | 1011 | Add A to ACC | also add R |
| SUB R A | 12 | 1100 | Subtract A from ACC | also subtract R |
| POP A | 13 | 1101 | Copy mem at SP into A, then dec SP | |
| PSH A | 14 | 1110 | Copy A into mem at SP, then inc SP |
| Asm | Bin |
|---|---|
| ADD 50 | 101000000000110010 |
| ADD 30 | 101000000000011110 |
| DAM 3 | 000000000000000011 |
________________________________________________________________________________________________________________________ / ____________________________________________________________________________________________________________________ \ | / +++++++++++++++++++++++++++++++\ | | | |START|SINGL| | ++Astral Computing Inc. AC-63++| | | | | | | | +++++++++++++++++++++++++++++++| | | | | / \ | /_\ | | | | | | | \|/ | \ / | | | | | | | ^ | | | | | | | |STOP |STEP | | | | | | | | | |____________________________________________________________________________________________________________________| | | | ! ! ! | | | | ! !1. ! | | | | / \ / \ / \ / \ ! / \ / \ ! / \ / \ ! / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ | | | | \ / \ / \ / \ / ! \ / \ / ! \ / \ / ! \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / | | | | ! ! ! | | | | ! ! ! | | | | ! ! ! | | | | ! !2. ! | | | | / \ / \ / \ / \ ! / \ / \ ! / \ / \ ! / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ | | | | \ / \ / \ / \ / ! \ / \ / ! \ / \ / ! \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / | | | | ! ! ! | | | | ! ! ! | | | | ! ! ! | | | | ! !3. ! | | | | / \ / \ / \ / \ ! / \ / \ ! / \ / \ ! / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ | | | | \|/ \|/ \|/ \|/ ! \|/ \|/ ! \|/ \|/ ! \|/ \|/ \|/ \|/ \|/ \|/ \|/ \|/ \|/ \|/ | | | | ^ ^ ^ ^ ! ^ ^ ! ^ ^ ! ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ | | | | ! ! ! | | | \____________________________________________________________________________________________________________________/ | \________________________________________________________________________________________________________________________/
- Address Lights
- Data Lights
- Main Switches
- Control Switches
Notice the two vertical lines, these visually separate parts of the memory word into Instruction, Zero and Indirect bits, and Data segments respectively.