Week6.md

Week 6: Getting into the real world

• Digital Architecture: How to put a system together?

  • Concept of a digital bus
    • Why busses?
    • Wishbone
    • AMBA
  • Control path & Data path:
    • Common data bus
    • Dedicated point-point links

• FPGA specifics: Beyond the basics

  • Pin Constraints
  • Timing constraints
  • Place and Route

Material

• Module 6 Slide Deck

• Further Reading:

  • NoC
  • Wishbone Specification
  • Valid-Ready Protocol
  • Matt Venn's videos on yosys, nextpnr, icepack/iceprog
  • Lattice iCE40 Ultra Plus FPGA Datasheet

Challenge:

Go through a non-trivial FPGA design backend

• Download the upduino-video project
• Install the related toolchains
• Run the simulation
• Generate the bitfile
• Identify the following parts of the design process we learned about:
  • Simulations
  • Pin constraints
  • Clock constraints
  • Placement related steps
  • Routing related steps
  • Bitgen
• Are you able to identify how large the design is from the logs?
• What clock frquency was the design able to meet? Rerun the tools and see if this changes. Can you explain why this is different?
• Make changes to the code and play with it to see if you can get any changes in the output of the simulations.

Advanced Challenges/Thought experiments:

• Download the picosoc project and play with it.
  • Do you see any difference in how long the FPGA backend process takes?
  • Are you able to identify how large the design is from the logs?
  • What clock frquency was the design able to meet? Rerun the tools and see if this changes. Can you explain why this is different?