Blackhole muladd negation optimization

Blackhole's sfpmad instruction can negate a and/or c operands. This implements such an optimization. Thus vector expressions such as a * b - c, -a * b + c, a * -b - c, -a * -b - c, c - (a * b) compile to a single sfpmad instruction.

Add .ttinsn assembly pseudo

Adds a .ttinsn assembly pseudo, which takes a raw SFPU instruction encoding. For instance:

.ttinsn 0x700cc000

Assembles (and then disassembles) to:

00000000: c0330001 sfpload L0,0,12,3

Compiler Fixes

This release:

• Adds GS, WH & BH multilibs. This enables GS and WH workarounds for some chip errata.
• Adds QEMU test infrastructure, augmented build scripts and GCC testsuite.
• Fixes several internal compiler errors when checking is enabled.
• One outcome of those changes is that the rvtt_l1_ptr and rvtt_reg_ptr consistently create distinct types, and thus previously unreported type mismatch errors may occur. (Previously these attributes had inconsistent behavior regarding the distinctness of types.)

cmp-signedness

test release

New architecture extension mechanism

New RiscV-compliant architecture extension mechanism

Warning: incompatible command options and elf numbers

This release replaces the adhoc RiscV architecture flags and options with the more usual scheme. Command line options have changed -- there was no way to keep compatibility. But the good news is you do not have to specify things twice and risk doing that inconsistently.

0. Tenstorrent has reserved tt as an architecture extension prefix -- see https://github.com/riscv-non-isa/riscv-toolchain-conventions/blob/main/src/toolchain-conventions.adoc

1. There are 3 new RiscV architecture extension attributes: xttgs, xttwh & xttbh for Grayskull, Wormhole & Blackhole respectively. These replace the non-standard y, w & l letters. These extensions remain mutually incompatible -- you can only select at most one of them. This means a lack of binary compatibility with old object files and executables (as the attributes are embedded in .riscv_attributes sections).

2. The non-standard ELF machine numbers for the 3 ISAs are removed. All object files are marked with the conventional EM_RISCV (243) machine number. Thus a regular RiscV toolchain will be able to examine binaries, but not disassemble the new instructions. This means a lack of binary compatibility with old object files and executables.

3. The -mgrayskull, -mwormhole, -mblackhole command line options are removed from both compiler and assembler.

4. It is sufficient to use -march=rv32i_xttgs, -march=rv32im_xttwh or -march=rv32im_xttbh to select a variant. See below about a simpler mechanism available in the compiler.

5. The grayskull, wormhole & blackhole cpus have been renamed to tt-gs, tt-wh & tt-bh, which is consistent with other vendors' cpu names.

6. The compiler defines __riscv_tt_grayskull, __riscv_tt_wormhole or __riscv_tt_blackhole #defines when one of the architecture extensions is targetted.

7. A number of assembler & disassembler bugs have been fixed.

The simplest way to drive the compiler is to specify a cpu, e.g. -mcpu=tt-bh, rather than the previously-required combination of -march=rv32iml -mblackhole -mtune=rvtt-b1.

Updated release process

• Removes unused components
• Create binary release mechanism