From 9e3a0eee6c41930954e293a459f3ae0f4f9b9c90 Mon Sep 17 00:00:00 2001 From: Nikita Lukonenko Date: Mon, 2 Dec 2024 19:25:46 +0300 Subject: [PATCH] patch: add support dp_memory for tang primer 20k board --- src/includes/scr1_arch_description.svh | 1 + src/top/scr1_dp_memory.sv | 30 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/src/includes/scr1_arch_description.svh b/src/includes/scr1_arch_description.svh index 018d0d7b..2926bae1 100644 --- a/src/includes/scr1_arch_description.svh +++ b/src/includes/scr1_arch_description.svh @@ -46,6 +46,7 @@ // `define SCR1_TRGT_FPGA_INTEL_ARRIAV // target platform is Intel Arria V FPGAs (used in the SCR1-SDK project) // `define SCR1_TRGT_FPGA_XILINX // target platform is Xilinx FPGAs (used in the SCR1-SDK project) // `define SCR1_TRGT_ASIC // target platform is ASIC +// `define SCR1_TRGT_FPGA_GOWIN // target platform is Gowin FPGAs (used in the SCR1-SDK project) // `define SCR1_TRGT_SIMULATION // target is simulation (enable simulation code) `include "scr1_arch_custom.svh" diff --git a/src/top/scr1_dp_memory.sv b/src/top/scr1_dp_memory.sv index 971591db..af7a8af0 100644 --- a/src/top/scr1_dp_memory.sv +++ b/src/top/scr1_dp_memory.sv @@ -65,6 +65,36 @@ always_ff @(posedge clk) begin qa <= memory_array[addra]; end +`elsif SCR1_TRGT_FPGA_GOWIN + +localparam int unsigned RAM_SIZE_WORDS = SCR1_SIZE/SCR1_NBYTES; + +//------------------------------------------------------------------------------- +// Local signal declaration +//------------------------------------------------------------------------------- +(* ram_style = "block" *) logic [SCR1_WIDTH-1:0] ram_block [(RAM_SIZE_WORDS-1):0] /* synthesis syn_ramstyle = "block_ram" */; + +//FIXME here not supported bytes writing in dualport memory mode. Only words. +//------------------------------------------------------------------------------- +// Port B memory behavioral description +//------------------------------------------------------------------------------- +always_ff @(posedge clk) begin + if (wenb) begin + ram_block[addrb] <= datab; + end + if(renb) begin + qb <= ram_block[addrb]; + end +end +//------------------------------------------------------------------------------- +// Port A memory behavioral description +//------------------------------------------------------------------------------- +always_ff @(posedge clk) begin + if(rena) begin + qa <= ram_block[addra]; + end +end + `else // SCR1_TRGT_FPGA_INTEL // CASE: OTHERS - SCR1_TRGT_FPGA_XILINX, SIMULATION, ASIC etc