Fixed issue with outputs that have identical names to record elements

src/META-INF/MANIFEST.MF

@@ -2,7 +2,7 @@ Manifest-Version: 1.0
 Bundle-ManifestVersion: 2
 Bundle-Name: Verilog/VHDL Plugin 
 Bundle-SymbolicName: net.sourceforge.veditor; singleton:=true
-Bundle-Version: 1.2.1.c
+Bundle-Version: 1.2.1.16
 Bundle-ClassPath: veditor.jar
 Bundle-Activator: net.sourceforge.veditor.VerilogPlugin
 Bundle-Vendor: VEditor Team

src/src/net/sourceforge/veditor/semanticwarnings/SemanticWarnings.java

@@ -3,6 +3,8 @@
 import java.util.Vector;
 
 import org.eclipse.core.resources.IFile;
+
+import sun.org.mozilla.javascript.internal.ast.AstNode;
 import net.sourceforge.veditor.VerilogPlugin;
 import net.sourceforge.veditor.parser.vhdl.*;
 import net.sourceforge.veditor.semanticwarnings.VariableStore.DeclaredSymbol;
@@ -211,7 +213,8 @@ else if(node instanceof ASTentity_declaration) {
 			node instanceof ASTinterface_signal_declaration ||
 			node instanceof ASTfull_type_declaration ||
 			node instanceof ASTvariable_declaration ||
-			node instanceof ASTcomponent_instantiation_statement
+			node instanceof ASTcomponent_instantiation_statement ||
+			node instanceof ASTconcurrent_signal_assignment_statement
 		) {
 			for(int i=0;i<node.getChildCount();i++) {
 				if(node.getChild(i) instanceof ASTidentifier) {
@@ -374,7 +377,11 @@ private Vector<SimpleNode> getAllBaseIdentifierNodes(SimpleNode node) {
 		// do not go into expressions like "port'range"
 		Vector<SimpleNode> result = new Vector<SimpleNode>();
 		for(int i=0;i<node.getChildCount();i++) {
-			result.addAll(getAllBaseIdentifierNodes(node.getChild(i)));
+			SimpleNode child = node.getChild(i);
+			 // ignore choice selections for semantic warnings to avoid issues with record with identical element names
+			if (!(child instanceof ASTchoice)) {
+				result.addAll(getAllBaseIdentifierNodes(node.getChild(i)));
+			}
 		}
 		return result;
 	}
@@ -538,7 +545,10 @@ private void checkAssignmentSymbol(VariableStore store, SimpleNode node) {
 					checkAssignmentType(node, declared, assignedName);
 
 					// find in the inputs for the expression if there are any outputs used
-					Vector<SimpleNode> inputName = getAllBaseIdentifierNodes(node.getChild(i+1));
+					Vector<SimpleNode> inputName = new Vector<SimpleNode>();
+					for (int j=i+1; j<node.getChildCount();j++) {
+						inputName.addAll( getAllBaseIdentifierNodes(node.getChild(j)) );
+					}
 
 					// check if not of the inputs is an output of the entity
 					for (int k=0;k<inputName.size();k++) {

test_projects/Test_VHDL/output_name_conflict.vhd

@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tst is
+    port  (
+        outp : out std_logic
+    );
+end tst;
+
+architecture arch of tst is
+    type r is record
+        outp : std_logic;
+    end record;
+    signal ok_1,ok_2,parsing_problem : r;
+begin
+
+    ok_1 <= ( outp => '1'); 
+
+    p : process
+    begin 
+        ok_2.outp    <= '1';
+        parsing_problem <= (outp => '1');
+    end process;
+end arch;