Baseline / minimal working solution?

[ogdoak]

Dear authors,

I have been reading the documentation, going through the code and the examples you provided (mainly the one for Pluto and for ZCU102), but sadly getting more and more lost.

My goal is to implement / port the timestamping solution to a custom Zynq board. Which example from this repository would you say represents a baseline solution? Alternatively, which blocks in which configurations are required to get a minimal version of zynq timestamping up and running?

So far I was able to make the ADC path work with only

• timestamp_unit_lclk_count,
• adc_dmac_xlength_sniffer,
• adc_fifo_timestamp_enabler in FREERUN mode.

But not so lucky with the DAC path using:

• dac_dmac_xlength_sniffer,
• dac_fifo_timestamp_enabler (doesn't forward the data unless in BYPASS mode).

Specific points I found confusing:

1. there are blocks in the ADI_timestamping folder (also some ports) that are never used or only used in some, but not other examples (adc_timestamp_enabler_packetizer, srs_axi_control, dma_depack_channels, adc_12bit_readjustment),
2. there are blocks with seemingly overlapping functionality (adc_fifo_timestap_enabler, adc_timestamp_enabler_packetizer, adc_ and dac_dmac_xlength_sniffer) and blocks that have poor description and don't seem to do much at a first glance (adc_dma_packet_controller, dac_control_s_axi_aclk),
3. from what I understood, there are two mutually exclusive approaches: running SRS logic at 2x/4x sample clock or at axi clock, yet not all blocks have corresponding configuration parameters or ports (dac_dmac_xlength_sniffer for example), and it is not clear if and how they should be used in each case.

I will appreciate your thoughts and comments on that.

Best regards,
Andrey

[ofontbach]

Hi @ogdoak,

To start with it is important to know the kind of zynq you are targeting (i.e., 7000 or ultrascale) and which available solution would be closer to yours in terms of ADI interfacing (e.g., more pluto-like or zcu102 using a FMC daughterboard). With this, we can probably point you to the best example to base yourself on.

A few things:

• adc_fifo_timestamp_enabler in FREERUN mode is not waiting for the CPU (DMA) to request new I/Q data packets before forwarding data, so it's mostly meant for debug/testing

• dac_fifo_timestamp_enabler in BYPASS mode is obviously not implementing any timestamping
  from this first two I would guess your interfacing to the CPU/DMA is not as expected.

• Yes, not all blocks are used in all system implementations (and, yes, adc_12bit_readjustment shouldn't be there at all - again it's a dummy block meant for debug in the RFSoC). Likewise, the clock configuraton is depending on the interfacing with the ADI RFIC and the clock received by the FPGA.

• Sorry if you find the documentation poor. It has room for improvement, yes.

If you provide more details about your specific system it will be much easier to help.

Regards,
Oriol