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sram_7t_netlist
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* Generated for: PrimeSim
* Design library name: sb_lib_7T
* Design cell name: sb_7T_sram_tb_2
* Design view name: schematic
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09
*Fri Feb 25 16:51:59 2022
.global gnd!
********************************************************************************
* Library : sb_lib_7T
* Cell : sb_7T_sram
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt sb_7t_sram bl blb gnd_1 q qb vdd wl
xm6 q wl bl gnd_1 n105 w=0.2u l=0.03u nf=1 m=1
xm5 blb qb gnd_1 gnd_1 n105 w=0.2u l=0.03u nf=1 m=1
xm1 q qb gnd_1 gnd_1 n105 w=0.2u l=0.03u nf=1 m=1
xm0 qb q gnd_1 gnd_1 n105 w=0.2u l=0.03u nf=1 m=1
xm4 net29 q vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm3 q qb net29 net29 p105 w=0.1u l=0.03u nf=1 m=1
xm2 qb q net29 net29 p105 w=0.1u l=0.03u nf=1 m=1
.ends sb_7t_sram
********************************************************************************
* Library : sb_lib_7T
* Cell : sb_7T_sram_tb_2
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xi0 bl net15 gnd! q qb net9 wl sb_7t_sram
v1 net9 gnd! dc=0.9
v4 net15 gnd! dc=0 pulse ( 0.9 0 0 10p 10p 5n 10n )
v3 wl gnd! dc=0 pulse ( 0 0.9 2n 10p 10p 5n 10n )
v2 bl gnd! dc=0 pulse ( 0 0.9 0 10p 10p 5n 10n )
.tran '1n' '10n' name=tran
.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1
.probe tran v(q) v(qb) v(bl) v(wl)
.temp 25
.option primesim_output=wdf
.option parhier = LOCAL
.end