Table of Contents

1. Solution
2. Design of Finite State Machine(FSM)
3. Netlist Viewer
4. Register Transfer Level(RTL) Viewer
5. State Diagram Viewer
6. Code Explanation
   1. Top Module
   2. bin_to_bcd Module
   3. seven_seg Module
   4. close Module
   5. open Module
   6. ClockDivider Module
   7. Pin Plannar
7. DE2-115 Field Programmable Gate Array(FPGA) Result
   1. Pinout Board Overview
   2. State Transition Result
   3. Video Demonstration
8. Discussion
9. Conclusion
10. Reference
11. Solution
12. Design of Finite State Machine(FSM)

“8. Access Gate control for a gate that open with an RFID card.”

I approach this challenge by first dividing the system into clear operational phases that mirror how an access gate typically functions. I start by identifying the various stages— waiting for an RFID scan, checking the scan, approving or denying access, and then managing the mechanical opening or closing of the gate. Next, I define what happens at each stage, such as displaying different messages to users while waiting, indicating “Granted” or “Denied,” and enabling the gate to move. I map out each trigger that causes the system to progress from one phase to another—for instance, a correct RFID code leads to a “Granted” state, while an incorrect one leads to “Denied.” Once the roadmap of states and transitions is established, I incorporate essential components like the RFID reader, a mechanism to drive the gate, and any indicators or display modules needed. This approach ensures that the system remains organized, straightforward to test, and easy to refine as I finalize the design.

RFID Technology Overview

RFID (Radio Frequency Identification) operates by transmitting data wirelessly through radio waves between an RFID tag (often embedded in a card or key fob) and an RFID reader. When an RFID card is brought within range of the reader, the reader emits an electromagnetic field that powers the tag’s internal circuitry. The powered tag then responds by sending its stored identification data back to the reader. This data is checked against an authorized database—if the tag’s data is recognized, access is granted; otherwise, access is denied.

In my project, I replicate this same security check using a password rather than radio-based signals. Instead of the reader-wireless-tag exchange, I rely on a user-entered code that is compared against a pre-set “valid password” in my system. Conceptually, both methods achieve the same goal: verifying credentials before granting access. The primary difference lies in the medium of data transfer—RFID relies on radio frequency signals, while my project uses a direct input method for password verification.

2. Netlist Viewer
3. Register Transfer Level(RTL) Viewer

Open Door

Close Door

Binary to BCD Converter

Clock Divider

7 Segment Hex Out

State Machine

RTL Viewer

Function	Module Instances
Clock Divider
Close Door Effect LED Shifting
Open Door Effect LED Shifting
Binary to BCD converter

Seven Segment Output Display

2. State Machine Viewer

State Machine Viewer

• IDLE State: In the IDLE state, the system sits in a neutral position awaiting user interaction. No credential checks or door movements take place at this time. Instead, the system showing “IDLE” on the 7-segment displays and set an indicator LED to let the user know the system is ready. Once the user presses the “start” switch, the state machine transitions from IDLE to the VAL state, initiating the authentication process.

• VAL (Validation) State: The VAL state handles the crucial step of verifying whether the user’s input credentials match the preset or stored password. In a typical RFID or password-based system, the user’s data is compared against a known pattern, in my case, I set 11010 as authentication password. If the user has not yet pressed the button to confirm their input, the VAL state continues waiting. Once verification input is pressed, the system checks the entered credentials. A successful match triggers a transition to the GRANTED state, while a mismatch sends the system to the DENIED state.

• GRANTED State: Entering the GRANTED state indicates that the user-supplied password or RFID code has been successfully authenticated. Here, the system displays a confirmation message on the 7-segment displays spelling out a simplified “PASS” and success indicator all green LED lights up. The user then has the option to move to the OPEN state by pressing another signal, which effectively instructs the system to open the door. If c is not triggered, the state machine remains in GRANTED until the user decides to proceed.

• DENIED State: If the validation check fails in the VAL state, the system transitions to the DENIED state. This state presents a rejection or error message on the displays, typically spelling out “DENIED” or a similar indicator to inform the user that access was not authorized. Forcing the user to perform a reset or re-enter the system from IDLE. This prevents unauthorized repeated attempts without first resetting the system or reloading

  credentials.

• OPEN State: Upon receiving the “OPEN” signal from the GRANTED state, the system moves to the OPEN state to physically open the gate or door. In the Verilog code, this may involve setting a door signal high and assigning an “open” animation pattern to the led output through the open module. The module’s logic animates the LEDs to visually indicate the door’s movement, eventually reaching a steady state that signifies the door is fully open. The state machine remains here until it detects a “close” command (signal d), initiating the closing procedure.

• CLOSE State: Once the user triggers the “close” command (d) while in the OPEN state, the system transitions to CLOSE. Similar to the OPEN state, a specialized close module manages a separate LED animation, showing the door returning from open to closed position. Once fully closed, the system typically waits for an additional signal to return to the IDLE state. This final step resets the system to its neutral state, ready to begin the authentication process again for the next user.

Transition State Table

2. Code Explanation
3. Top Module: digitalAssign

The digitalAssign module is the main controller in this design. It implements a state machine to control the behavior of a digital lock system with the following features:

1. State Machine with six states:

• IDLE
• VAL (VALIDATION)
• DENIED
• GRANTED
• OPEN
• CLOSE

2. Password Checking: Validates a user-entered 5-bit password (i1, i2, i3, i4, i5) against a known password.
3. Door Control: Shows when the door is open or closed, and transitions the door’s LED patterns accordingly using the open and close modules.
4. Slower Clock Generation: Utilizes a ClockDivider instance to generate a slower clock for state transitions.
5. Display Indicators: Drives multiple 7-segment displays (status1–status5) and a single 7-segment output (HEX), as well as 8 bits of indicator and 18 bits of led.
6. Inputs and Outputs

• Inputs

1. clk: The main (fast) clock input (e.g., 50 MHz).
2. rst: Active-high reset signal.
3. rst_n: Active-low reset signal.
4. a, b, c, d, e: Control inputs used to move between states.
5. i1, i2, i3, i4, i5: Switch inputs representing the 5-bit password.

• Outputs

1. indicator[7:0]: LED indicators showing the current state(s).
2. HEX[6:0]: A 7-segment display driven by the bin_to_bcd and seven_seg modules (displays the state code).
3. door: A signal that indicates whether the door is open (1) or closed (0).
4. status1, status2, status3, status4, status5: Five independent 7-segment outputs showing specific words/messages depending on the state.
5. led[17:0]: 18-bit output representing LED patterns that respond to open/close states.
6. Internal Signals and Registers

• State Variables
• current_state, next_state: 5-bit registers for the finite state machine (though only 3 bits are used by the parameters).
• Control/Helper Signals
• result: 8-bit register used to pass the current state code to the bin_to_bcd module for display on the 7-segment.
• A1: 12-bit wire that holds the BCD output from the bin_to_bcd converter.
• slow_counter: 24-bit register used inside this module to demonstrate resetting logic, though the main slow clock is generated by the ClockDivider.
• slow_clk: The slower clock output from the ClockDivider.
• LED Control for OPEN/CLOSE
• open_led, close_led: 18-bit wires connected to the outputs of the open and close submodules, respectively.

3. Instantiation of Submodules

4. ClockDivider

   The ClockDivider is instantiated with a

   parameter .DIV_FACTOR(15_000_000) to generate a slow_clk from the fast clk.

5. open

   Instantiated to produce LED patterns for the OPEN state.

6. close

   Instantiated to produce LED patterns for the CLOSE state.

7. bin_to_bcd

   Converts the result (binary) to a 3-digit BCD (in A1).

8. seven_seg

   Takes the lowest 4 bits of A1 (the ones digit) and drives a 7-segment display, HEX.

9. Finite State Machine Logic Below is a brief description of each state:

10. IDLE

• Sets indicator[0] high, meaning we are in IDLE.
• Seven Segment shows a specific message on the 7-segment displays (status1–status4) show “IDLE”
• If a == 1, transitions to VAL, otherwise remains in IDLE.

IDLE State Case

2. VAL (Validation)

• Checks if b == 1 to verify the password. If the password matches (i1 == 1, i2 == 1, i3 == 0, i4 == 1, i5 == 0), moves to GRANTED, else DENIED.
• “Password” is set to be 11010.
• If b == 0, stays in VAL.
• Seven Segment show “PASS”

VAL State Case

3. DENIED

• Displays “DENIED” on some 7-segment pattern (status1–status4).

• Stays in DENIED (next_state=DENIED).

• Seven Segment show “NOPE”

  

DENIED State Case

4. GRANTED

• Lights up all bits of green indicator (indicator[7:0] = 8'b11111111).

• If c == 1, moves to OPEN, otherwise remains GRANTED.

• Status show “PASS” in seven segment

  

GRANTED State Case

5. OPEN

• Activates door = 1.
• Uses the open_led pattern on the output led.
• If d == 1, transitions to CLOSE, otherwise remains in OPEN.
• Seven Segment show “OPEN”

OPEN State Case

6. CLOSE

• Uses the close_led pattern on the output led.
• If e == 1, transitions back to IDLE, otherwise remains in CLOSE.
• Seven Segment show “CLOSE”

CLOSE State Case

5. Sequential Logic for State Transition

• The FSM state transitions occur on the rising edge of slow_clk.
• An active-low reset (!rst) forces the FSM back to IDLE.

2. bin_to_bcd Module

   Converts an 8-bit binary number (0–255) into a 3-digit Binary-Coded Decimal (BCD) output suitable for display on 7-segment displays or other decimal - based outputs.

3. Input and Outputs

• Input:
  • binary [7:0]: The 8-bit binary value to be converted.
• Output:
  • bcd [11:0]: The resulting three BCD digits. The bits are typically divided as:
    • [11:8] = Ones
    • [15:12] = Tens
    • [19:16] = Hundreds

bin_to_bcd Input and Output

2. Double-Dabble Algorithm

The double-dabble algorithm is used. In each iteration:

1. Check if each BCD nibble (hundreds, tens, ones) is >= 5; if yes, add 3 to that nibble.
2. Shift left by 1 bit (concatenating in the next binary bit).

Double-dabble Algorithm logic

3. seven_seg Module
4. Input and Outputs

• Input:
  • bcd [3:0]: The 4-bit BCD digit (0–9) to display.
• Output:

  • hex_out [6:0]: The 7-segment encoding for displaying digits 0–9 (or

    blank otherwise).

seven_seg Input and Outputs

2. Implementation Hex_out

Case for each hex_out bit

4. Close Module

   Generates a shifting LED pattern to visually indicate the closing sequence of the door. As time progresses the module updates the 18-bit output led to new patterns until it reaches a fully lit state.

5. Input and Outputs

• Inputs:

1. clock: The fast input clock (e.g., 50 MHz).
2. rst_n: Active-low reset.

• Output:

  1. led [17:0]: The LED pattern output.

Close Module Input and Outputs

2. Simulation Door Close Logic

• slow_counter: A 24-bit counter that increments on each rising edge of clock. When it overflows (or reaches a threshold like 24'h999999), the module toggles or shifts some bits in led.
• Behavior:

1. If !rst_n is active, the module sets led to 18'b000000000000000000.
2. Each time slow_counter meets 24'h999999, the code updates led bits by shifting or toggling them.
3. Once led == 18'b111111111111111111, it freezes without further changes.

LED Shifting Close simulation behaviour logic

5. Open Module

   Similar to the close module, this module displays an opening LED sequence. Over time, bits in led are toggled until a specific pattern is reached (led == 18'b000000000000000000), at which point the pattern freezes. It reverse the operation from Close Module.

LED Open door simulation

6. ClockDivider Module

Generates a slower clock (clk_out) from the high-frequency input clock (clk_in) of 50Mhz, it crash as too fast operation. This is used, for example, to slow down the state machine transitions in digitalAssign.

1. Parameter

DIV_FACTOR: Sets the division ratio. For a 50 MHz clock, a DIV_FACTOR of 25,000,000 would produce a 1 Hz output clock. Here, it is set to 15,000,000, which would yield a roughly 3.3 Hz clock (depending on the original frequency).

2. Inputs and Outputs

• Inputs:

1. clk_in: The high-frequency input clock.
2. rst: Active-high reset.

• Output:

1. clk_out: The divided/slower clock signal.

3. Behaviour Logic

A 32-bit counter increments on each rising edge of clk_in. When the counter reaches DIV_FACTOR - 1, it toggles clk_out and resets the counter:

Clk_out slower behaviour logic

2.6 Pin Plannar

Table below conclude all PINOUT set with reference with DE2-115 manual of pin preset:

To	Direction	Location	I/O Bank	VREF Group	Fitter Location	I/O Standard
	HEX[6]	Output		PIN_AA14	3	B3_N0	PIN_AA14	2.5 V
	HEX[5]	Output		PIN_AG18	4	B4_N2	PIN_AG18	2.5 V
	HEX[4]	Output		PIN_AF17	4	B4_N2	PIN_AF17	2.5 V
	HEX[3]	Output		PIN_AH17	4	B4_N2	PIN_AH17	2.5 V
	HEX[2]	Output		PIN_AG17	4	B4_N2	PIN_AG17	2.5 V
	HEX[1]	Output		PIN_AE17	4	B4_N2	PIN_AE17	2.5 V
	HEX[0]	Output		PIN_AD17	4	B4_N2	PIN_AD17	2.5 V
	a	Input		PIN_AB28	5	B5_N1	PIN_AB28	2.5 V
	b	Input		PIN_AC28	5	B5_N2	PIN_AC28	2.5 V
	c	Input		PIN_AC27	5	B5_N2	PIN_AC27	2.5 V
	clk	Input		PIN_Y2	2	B2_N0	PIN_Y2	2.5 V
	d	Input		PIN_AD27	5	B5_N2	PIN_AD27	2.5 V
	door	Output		PIN_F17	7	B7_N2	PIN_F17	2.5 V
	e	Input		PIN_AB27	5	B5_N1	PIN_AB27	2.5 V
	i1	Input		PIN_Y23	5	B5_N2	PIN_Y23	2.5 V
	i2	Input		PIN_Y24	5	B5_N2	PIN_Y24	2.5 V
	i3	Input		PIN_AA22	5	B5_N2	PIN_AA22	2.5 V
	i4	Input		PIN_AA23	5	B5_N2	PIN_AA23	2.5 V
	i5	Input		PIN_AA24	5	B5_N2	PIN_AA24	2.5 V
	indicator[7]	Output		PIN_G21	7	B7_N1	PIN_G21	2.5 V
	indicator[6]	Output		PIN_G22	7	B7_N2	PIN_G22	2.5 V
	indicator[5]	Output		PIN_G20	7	B7_N1	PIN_G20	2.5 V
	indicator[4]	Output		PIN_H21	7	B7_N2	PIN_H21	2.5 V
	indicator[3]	Output		PIN_E24	7	B7_N1	PIN_E24	2.5 V
	indicator[2]	Output		PIN_E25	7	B7_N1	PIN_E25	2.5 V
	indicator[1]	Output		PIN_E22	7	B7_N0	PIN_E22	2.5 V
	indicator[0]	Output		PIN_E21	7	B7_N0	PIN_E21	2.5 V
	led[17]	Output		PIN_H15	7	B7_N2	PIN_H15	2.5 V
	led[16]	Output		PIN_G16	7	B7_N2	PIN_G16	2.5 V
	led[15]	Output		PIN_G15	7	B7_N2	PIN_G15	2.5 V
	led[14]	Output		PIN_F15	7	B7_N2	PIN_F15	2.5 V
	led[13]	Output		PIN_H17	7	B7_N2	PIN_H17	2.5 V
	led[12]	Output		PIN_J16	7	B7_N2	PIN_J16	2.5 V
	led[11]	Output		PIN_H16	7	B7_N2	PIN_H16	2.5 V
	led[10]	Output		PIN_J15	7	B7_N2	PIN_J15	2.5 V
	led[9]	Output		PIN_G17	7	B7_N1	PIN_G17	2.5 V
	led[8]	Output		PIN_J17	7	B7_N2	PIN_J17	2.5 V
	led[7]	Output		PIN_H19	7	B7_N2	PIN_H19	2.5 V
	led[6]	Output		PIN_J19	7	B7_N2	PIN_J19	2.5 V
	led[5]	Output		PIN_E18	7	B7_N1	PIN_E18	2.5 V
	led[4]	Output		PIN_F18	7	B7_N1	PIN_F18	2.5 V
	led[3]	Output		PIN_F21	7	B7_N0	PIN_F21	2.5 V

	led[2]	Output		PIN_E19	7	B7_N0	PIN_E19	2.5 V
	led[1]	Output		PIN_F19	7	B7_N0	PIN_F19	2.5 V
	led[0]	Output		PIN_G19	7	B7_N2	PIN_G19	2.5 V
	rst	Input		PIN_M21	6	B6_N1	PIN_M21	2.5 V
	rst_n	Input		PIN_M23	6	B6_N2	PIN_M23	2.5 V
	status1[6]	Output		PIN_Y19	4	B4_N0	PIN_Y19	2.5 V
	status1[5]	Output		PIN_AF23	4	B4_N0	PIN_AF23	2.5 V
	status1[4]	Output		PIN_AD24	4	B4_N0	PIN_AD24	2.5 V
	status1[3]	Output		PIN_AA21	4	B4_N0	PIN_AA21	2.5 V
	status1[2]	Output		PIN_AB20	4	B4_N0	PIN_AB20	2.5 V
	status1[1]	Output		PIN_U21	5	B5_N0	PIN_U21	2.5 V
	status1[0]	Output		PIN_V21	5	B5_N1	PIN_V21	2.5 V
	status2[6]	Output		PIN_W28	5	B5_N1	PIN_W28	2.5 V
	status2[5]	Output		PIN_W27	5	B5_N1	PIN_W27	2.5 V
	status2[4]	Output		PIN_Y26	5	B5_N1	PIN_Y26	2.5 V
	status2[3]	Output		PIN_W26	5	B5_N1	PIN_W26	2.5 V
	status2[2]	Output		PIN_Y25	5	B5_N1	PIN_Y25	2.5 V
	status2[1]	Output		PIN_AA26	5	B5_N1	PIN_AA26	2.5 V
	status2[0]	Output		PIN_AA25	5	B5_N1	PIN_AA25	2.5 V
	status3[6]	Output		PIN_U24	5	B5_N0	PIN_U24	2.5 V
	status3[5]	Output		PIN_U23	5	B5_N1	PIN_U23	2.5 V
	status3[4]	Output		PIN_W25	5	B5_N1	PIN_W25	2.5 V
	status3[3]	Output		PIN_W22	5	B5_N0	PIN_W22	2.5 V
	status3[2]	Output		PIN_W21	5	B5_N1	PIN_W21	2.5 V
	status3[1]	Output		PIN_Y22	5	B5_N0	PIN_Y22	2.5 V
	status3[0]	Output		PIN_M24	6	B6_N2	PIN_M24	2.5 V
	status4[6]	Output		PIN_H22	6	B6_N0	PIN_H22	2.5 V
	status4[5]	Output		PIN_J22	6	B6_N0	PIN_J22	2.5 V
	status4[4]	Output		PIN_L25	6	B6_N1	PIN_L25	2.5 V
	status4[3]	Output		PIN_L26	6	B6_N1	PIN_L26	2.5 V
	status4[2]	Output		PIN_E17	7	B7_N2	PIN_E17	2.5 V
	status4[1]	Output		PIN_F22	7	B7_N0	PIN_F22	2.5 V
	status4[0]	Output		PIN_G18	7	B7_N2	PIN_G18	2.5 V
	status5[6]	Output		PIN_AE18	4	B4_N2	PIN_AE18	2.5 V
	status5[5]	Output		PIN_AF19	4	B4_N1	PIN_AF19	2.5 V
	status5[4]	Output		PIN_AE19	4	B4_N1	PIN_AE19	2.5 V
	status5[3]	Output		PIN_AH21	4	B4_N2	PIN_AH21	2.5 V
	status5[2]	Output		PIN_AG21	4	B4_N2	PIN_AG21	2.5 V
	status5[1]	Output		PIN_AA19	4	B4_N0	PIN_AA19	2.5 V
	status5[0]	Output		PIN_AB19	4	B4_N0	PIN_AB19	2.5 V
reset_n	Unknown	PIN_N21	6	B6_N2
Pinout Table for DE2-115 Board

Top View-Wire Bond for DE2-115 Board

3. DE2-115 Field Programmable Gate Array(FPGA) Result
4. DE2-115 board Pinout Overview:

Seven Segment Show current_state

State encoding

parameter in decimal

Green LED indicator Current State

Reset whole FSM Reset Door Passcode Input 5 5 Input Switch a, b, to IDLE state Animation

Bit number c, d and e

LED Door Simulation Open & Close

2. State Transition Result:

1st to 2nd State
2nd to 3rd State (Passcode Correct)
2nd to 4th State (Passcode Uncorrect)

3rd to 5th State
5th to 6th State
6th back to 1st State, will keep loop if all input high

3. Video Demonstration of open close door animation and auto Clock system can be see by scan the QR code below:

4. Discussion

In developing this digital door lock system, one of the early discoveries was that the FPGA’s internal clock (50 MHz) proved too fast for direct use in the main state machine. When attempting to update the logic and outputs at this very high frequency, the display and LED behaviours appeared frozen or produced error states on the development board as it was transiting too fast. To overcome this, a dedicated clock divider was added to generate a slower clock signal. By reducing the update frequency (for example, to a few Hertz), it became possible to reliably drive the 7-segment displays and LEDs without overwhelming the system. This approach demonstrates the importance of proper clock management in FPGA designs, where matching the clock speed to the intended application or user interface is crucial.

Src: https://www.terasic.com.tw/attachment/archive/502/DE2\_115\_User\_manual.pdf

Another key constraint involved attempting to use the FPGA’s built-in LCD. In general, such LCD screens are more conveniently driven using higher-level languages (like C) and specific libraries that manage the display’s command protocol. Because this project was implemented entirely in Verilog HDL, integrating the existing LCD libraries was not straightforward. Verilog does not inherently provide library support for driving character-based LCD panels, and as a result, it became impractical to fully incorporate the LCD for displaying messages. This illustrates how hardware description languages can sometimes limit access to ready-made drivers for advanced peripherals, emphasizing the need to pick the right tools or IP cores when designing FPGA systems with sophisticated interfaces.

To visualize the door’s open/close process in a simple yet effective manner, 18 on-board red LEDs were used. The code essentially simulates a door opening by shifting LED bits in one direction, and a door closing by shifting them in the opposite direction. This gives a dynamic animation that hints at door movement, despite there being no physical actuator. Implementing such a shifting pattern helps convey real-world behavior (like a door sliding) and serves as a practical demonstration of how shifting registers can be employed for visual effects with minimal hardware overhead.

Provide a decimal readout of numeric states on the 7-segment displays, the Double-Dabble algorithm was implemented in a bin_to_bcd module. This classic algorithm converts an 8-bit binary value into Binary-Coded Decimal, allowing the 7-segment displays to show decimal numbers instead of raw binary patterns. The Double-Dabble approach is often found in hardware designs that require decimal displays, as it performs these conversions efficiently using shift-and-add operations. Understanding this algorithm is crucial for any digital designer who plans to render binary data into a more familiar decimal form on hardware-driven displays.

Double-dabble Algorithm

5. Conclusion

Conclusion, this project successfully demonstrates how fundamental hardware concepts, such as state machines, clock domain management, and simple data transformations, can be integrated to create a functional digital door lock system on an FPGA. Learning working behind implementing Double-dabble Algorithm in most of the application is beneficial to me. By combining the clock divider approach with careful logic design, the system’s speed was brought under control to provide stable outputs and user-friendly interactions. Although certain constraints, particularly the limitations of using Verilog for driving the built-in LCD, introduced complexity in providing a full graphical interface, creative alternatives using on- board LEDs and 7-segment displays still achieved an effective user interface. Ultimately, this project underlines the importance of understanding both the low-level hardware description perspective and the practical considerations such as clock frequencies, hardware resource usage, and available language libraries—when designing embedded systems on an FPGA.

6. Reference

• DE2_115_User_manual.PDF. (n.d.). https://www.terasic.com.tw/attachment/archive/502/DE2_115_User_manual .pdf
• Wikipedia contributors. (2024, May 19). Double dabble. Wikipedia. https://en.wikipedia.org/wiki/Double\_dabble
• Best Sellers. (n.d.). https://www.wfoqfashion.shop/?ggcid=1656206 30