v0.1.3

sgherbst · Jan 17, 2020 · b369cb7 · b369cb7
1 parent 0a9207f
commit b369cb7
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/anasymod/analysis.py b/anasymod/analysis.py
@@ -156,7 +156,7 @@ def setup_filesets(self):
 
         # Add some default files depending on whether there is a custom top level
         # TODO: clean this part up with generated top level
-        self.filesets.add_source(source=VerilogSource(files=get_from_module('anasymod', 'verilog', 'vio_gen.sv'), config_path=config_path))
+        self.filesets.add_source(source=VerilogSource(files=get_from_anasymod('verilog', 'vio_gen.sv'), config_path=config_path))
         for fileset in ['sim', 'fpga']:
             try:
                 custom_top = self.cfg_file['TARGET'][fileset]['custom_top']
@@ -428,7 +428,7 @@ def _parse_args(self):
         python analysis.py -i filter --models --sim --view
 
         -i, --input: Path to project root directory of the project that shall be opened and worked with.
-            default=get_from_module('anasymod', 'tests', 'filter'))
+            default=None
 
         --simulator_name: Simulator that shall be used for logic simulation.
             default=icarus for windows, xrun for linux

diff --git a/setup.py b/setup.py
@@ -1,7 +1,7 @@
 from setuptools import setup
 
 name = 'anasymod'
-version = '0.1.2'
+version = '0.1.3'
 
 DESCRIPTION = '''\
 Tool for running mixed-signal emulations on FPGAs\