diff --git a/sc/prj/common/vips/sdcard/vip_sdcard_ctrl.h b/sc/prj/common/vips/sdcard/vip_sdcard_ctrl.h
index 599593896..d1c54bc78 100644
--- a/sc/prj/common/vips/sdcard/vip_sdcard_ctrl.h
+++ b/sc/prj/common/vips/sdcard/vip_sdcard_ctrl.h
@@ -137,7 +137,7 @@ SC_MODULE(vip_sdcard_ctrl) {
         iv.ocr_hcs = 0;
         iv.ocr_vdd_window = 0;
         iv.req_mem_valid = 0;
-        iv.req_mem_addr = 0ull;
+        iv.req_mem_addr = 0;
         iv.shiftdat = ~0ul;
         iv.bitcnt = 0;
         iv.crc16_clear = 0;
diff --git a/sc/rtl/ambalib/axi2apb_bus1.h b/sc/rtl/ambalib/axi2apb_bus1.h
index 6c88f8f57..0475939f4 100644
--- a/sc/rtl/ambalib/axi2apb_bus1.h
+++ b/sc/rtl/ambalib/axi2apb_bus1.h
@@ -75,8 +75,8 @@ SC_MODULE(axi2apb_bus1) {
         iv.selidx = 0;
         iv.pvalid = 0;
         iv.paddr = 0;
-        iv.pwdata = 0ull;
-        iv.prdata = 0ull;
+        iv.pwdata = 0;
+        iv.prdata = 0;
         iv.pwrite = 0;
         iv.pstrb = 0;
         iv.pprot = 0;
diff --git a/sc/rtl/ambalib/axi_slv.h b/sc/rtl/ambalib/axi_slv.h
index e37fe2e55..5aa23c44f 100644
--- a/sc/rtl/ambalib/axi_slv.h
+++ b/sc/rtl/ambalib/axi_slv.h
@@ -90,9 +90,9 @@ SC_MODULE(axi_slv) {
     void axi_slv_r_reset(axi_slv_registers &iv) {
         iv.state = State_Idle;
         iv.req_valid = 0;
-        iv.req_addr = 0ull;
+        iv.req_addr = 0;
         iv.req_write = 0;
-        iv.req_wdata = 0ull;
+        iv.req_wdata = 0;
         iv.req_wstrb = 0;
         iv.req_xsize = 0;
         iv.req_len = 0;
@@ -104,7 +104,7 @@ SC_MODULE(axi_slv) {
         iv.req_done = 0;
         iv.resp_valid = 0;
         iv.resp_last = 0;
-        iv.resp_rdata = 0ull;
+        iv.resp_rdata = 0;
         iv.resp_err = 0;
     }
 
diff --git a/sc/rtl/misclib/clint.h b/sc/rtl/misclib/clint.h
index 3766cfd9a..b4223262b 100644
--- a/sc/rtl/misclib/clint.h
+++ b/sc/rtl/misclib/clint.h
@@ -234,13 +234,13 @@ void clint<cpu_total>::comb() {
     v.rdata = vrdata;
 
     if (!async_reset_ && i_nrst.read() == 0) {
-        v.mtime = 0ull;
+        v.mtime = 0;
         for (int i = 0; i < cpu_total; i++) {
             v.hart[i].msip = 0;
             v.hart[i].mtip = 0;
             v.hart[i].mtimecmp = 0ull;
         }
-        v.rdata = 0ull;
+        v.rdata = 0;
     }
 
     for (int i = 0; i < cpu_total; i++) {
@@ -260,13 +260,13 @@ void clint<cpu_total>::comb() {
 template<int cpu_total>
 void clint<cpu_total>::registers() {
     if (async_reset_ && i_nrst.read() == 0) {
-        r.mtime = 0ull;
+        r.mtime = 0;
         for (int i = 0; i < cpu_total; i++) {
             r.hart[i].msip = 0;
             r.hart[i].mtip = 0;
             r.hart[i].mtimecmp = 0ull;
         }
-        r.rdata = 0ull;
+        r.rdata = 0;
     } else {
         r.mtime = v.mtime;
         for (int i = 0; i < cpu_total; i++) {
diff --git a/sc/rtl/misclib/plic.h b/sc/rtl/misclib/plic.h
index 9b70b5c62..d71247b51 100644
--- a/sc/rtl/misclib/plic.h
+++ b/sc/rtl/misclib/plic.h
@@ -367,8 +367,8 @@ void plic<ctxmax, irqmax>::comb() {
     }
 
     if (!async_reset_ && i_nrst.read() == 0) {
-        v.src_priority = 0ull;
-        v.pending = 0ull;
+        v.src_priority = 0;
+        v.pending = 0;
         v.ip = 0;
         for (int i = 0; i < ctxmax; i++) {
             v.ctx[i].priority_th = 0;
@@ -379,7 +379,7 @@ void plic<ctxmax, irqmax>::comb() {
             v.ctx[i].irq_idx = 0;
             v.ctx[i].irq_prio = 0;
         }
-        v.rdata = 0ull;
+        v.rdata = 0;
     }
 
     w_req_ready = 1;
@@ -392,8 +392,8 @@ void plic<ctxmax, irqmax>::comb() {
 template<int ctxmax, int irqmax>
 void plic<ctxmax, irqmax>::registers() {
     if (async_reset_ && i_nrst.read() == 0) {
-        r.src_priority = 0ull;
-        r.pending = 0ull;
+        r.src_priority = 0;
+        r.pending = 0;
         r.ip = 0;
         for (int i = 0; i < ctxmax; i++) {
             r.ctx[i].priority_th = 0;
@@ -404,7 +404,7 @@ void plic<ctxmax, irqmax>::registers() {
             r.ctx[i].irq_idx = 0;
             r.ctx[i].irq_prio = 0;
         }
-        r.rdata = 0ull;
+        r.rdata = 0;
     } else {
         r.src_priority = v.src_priority;
         r.pending = v.pending;
diff --git a/sc/rtl/riverlib/cache/cache_top.cpp b/sc/rtl/riverlib/cache/cache_top.cpp
index 53bcc96b5..02f226993 100644
--- a/sc/rtl/riverlib/cache/cache_top.cpp
+++ b/sc/rtl/riverlib/cache/cache_top.cpp
@@ -374,9 +374,9 @@ void CacheTop::comb() {
     sc_uint<RISCV_ARCH> vb_resp_ctrl_addr;
     sc_uint<RISCV_ARCH> vb_resp_data_addr;
 
-    vb_ctrl_bus = 0ull;
-    vb_data_bus = 0ull;
-    vb_queue_bus = 0ull;
+    vb_ctrl_bus = 0;
+    vb_data_bus = 0;
+    vb_queue_bus = 0;
     ctrl_path_id = CTRL_PATH;
     data_path_id = DATA_PATH;
     v_queue_we = 0;
diff --git a/sc/rtl/riverlib/cache/dcache_lru.h b/sc/rtl/riverlib/cache/dcache_lru.h
index a9ef8117d..07c7a94ae 100644
--- a/sc/rtl/riverlib/cache/dcache_lru.h
+++ b/sc/rtl/riverlib/cache/dcache_lru.h
@@ -143,15 +143,15 @@ SC_MODULE(DCacheLru) {
 
     void DCacheLru_r_reset(DCacheLru_registers &iv) {
         iv.req_type = 0;
-        iv.req_addr = 0ull;
-        iv.req_wdata = 0ull;
+        iv.req_addr = 0;
+        iv.req_wdata = 0;
         iv.req_wstrb = 0;
         iv.req_size = 0;
         iv.state = State_Reset;
         iv.req_mem_valid = 0;
         iv.req_mem_type = 0;
         iv.req_mem_size = 0;
-        iv.mem_addr = 0ull;
+        iv.mem_addr = 0;
         iv.load_fault = 0;
         iv.write_first = 0;
         iv.write_flush = 0;
@@ -162,13 +162,13 @@ SC_MODULE(DCacheLru) {
         iv.req_flush_addr = 0ull;
         iv.req_flush_cnt = 0;
         iv.flush_cnt = 0;
-        iv.cache_line_i = 0ull;
-        iv.cache_line_o = 0ull;
+        iv.cache_line_i = 0;
+        iv.cache_line_o = 0;
         iv.req_snoop_type = 0;
         iv.snoop_flags_valid = 0;
         iv.snoop_restore_wait_resp = 0;
         iv.snoop_restore_write_bus = 0;
-        iv.req_addr_restore = 0ull;
+        iv.req_addr_restore = 0;
     }
 
     sc_signal<bool> line_direct_access_i;
diff --git a/sc/rtl/riverlib/cache/icache_lru.h b/sc/rtl/riverlib/cache/icache_lru.h
index 2135089c9..0b134a6a6 100644
--- a/sc/rtl/riverlib/cache/icache_lru.h
+++ b/sc/rtl/riverlib/cache/icache_lru.h
@@ -108,12 +108,12 @@ SC_MODULE(ICacheLru) {
     } v, r;
 
     void ICacheLru_r_reset(ICacheLru_registers &iv) {
-        iv.req_addr = 0ull;
-        iv.req_addr_next = 0ull;
-        iv.write_addr = 0ull;
+        iv.req_addr = 0;
+        iv.req_addr_next = 0;
+        iv.write_addr = 0;
         iv.state = State_Reset;
         iv.req_mem_valid = 0;
-        iv.mem_addr = 0ull;
+        iv.mem_addr = 0;
         iv.req_mem_type = 0;
         iv.req_mem_size = 0;
         iv.load_fault = 0;
@@ -122,7 +122,7 @@ SC_MODULE(ICacheLru) {
         iv.req_flush_addr = 0ull;
         iv.req_flush_cnt = 0;
         iv.flush_cnt = 0;
-        iv.cache_line_i = 0ull;
+        iv.cache_line_i = 0;
     }
 
     sc_signal<bool> line_direct_access_i;
diff --git a/sc/rtl/riverlib/cache/pmp.cpp b/sc/rtl/riverlib/cache/pmp.cpp
index 6969432fe..ad45f764d 100644
--- a/sc/rtl/riverlib/cache/pmp.cpp
+++ b/sc/rtl/riverlib/cache/pmp.cpp
@@ -142,8 +142,8 @@ void PMP::comb() {
 
     if (!async_reset_ && i_nrst.read() == 0) {
         for (int i = 0; i < CFG_PMP_TBL_SIZE; i++) {
-            v.tbl[i].start_addr = 0ull;
-            v.tbl[i].end_addr = 0ull;
+            v.tbl[i].start_addr = 0;
+            v.tbl[i].end_addr = 0;
             v.tbl[i].flags = 0;
         }
     }
@@ -156,8 +156,8 @@ void PMP::comb() {
 void PMP::registers() {
     if (async_reset_ && i_nrst.read() == 0) {
         for (int i = 0; i < CFG_PMP_TBL_SIZE; i++) {
-            r.tbl[i].start_addr = 0ull;
-            r.tbl[i].end_addr = 0ull;
+            r.tbl[i].start_addr = 0;
+            r.tbl[i].end_addr = 0;
             r.tbl[i].flags = 0;
         }
     } else {
diff --git a/sc/rtl/riverlib/cache/tagmemcoupled.h b/sc/rtl/riverlib/cache/tagmemcoupled.h
index f1cb5f223..39b18a554 100644
--- a/sc/rtl/riverlib/cache/tagmemcoupled.h
+++ b/sc/rtl/riverlib/cache/tagmemcoupled.h
@@ -89,7 +89,7 @@ SC_MODULE(TagMemCoupled) {
     } v, r;
 
     void TagMemCoupled_r_reset(TagMemCoupled_registers &iv) {
-        iv.req_addr = 0ull;
+        iv.req_addr = 0;
     }
 
     tagmem_in_type linei[MemTotal];
diff --git a/sc/rtl/riverlib/cache/tagmemnway.h b/sc/rtl/riverlib/cache/tagmemnway.h
index f5006854b..01ccfa725 100644
--- a/sc/rtl/riverlib/cache/tagmemnway.h
+++ b/sc/rtl/riverlib/cache/tagmemnway.h
@@ -91,7 +91,7 @@ SC_MODULE(TagMemNWay) {
     } v, r;
 
     void TagMemNWay_r_reset(TagMemNWay_registers &iv) {
-        iv.req_addr = 0ull;
+        iv.req_addr = 0;
         iv.direct_access = 0;
         iv.invalidate = 0;
         iv.re = 0;
diff --git a/sc/rtl/riverlib/core/arith/alu_logic.h b/sc/rtl/riverlib/core/arith/alu_logic.h
index 67abb8d8a..03e8bac06 100644
--- a/sc/rtl/riverlib/core/arith/alu_logic.h
+++ b/sc/rtl/riverlib/core/arith/alu_logic.h
@@ -47,7 +47,7 @@ SC_MODULE(AluLogic) {
     } v, r;
 
     void AluLogic_r_reset(AluLogic_registers &iv) {
-        iv.res = 0ull;
+        iv.res = 0;
     }
 
 };
diff --git a/sc/rtl/riverlib/core/arith/int_addsub.h b/sc/rtl/riverlib/core/arith/int_addsub.h
index 616cf21a0..84c96ffb7 100644
--- a/sc/rtl/riverlib/core/arith/int_addsub.h
+++ b/sc/rtl/riverlib/core/arith/int_addsub.h
@@ -47,7 +47,7 @@ SC_MODULE(IntAddSub) {
     } v, r;
 
     void IntAddSub_r_reset(IntAddSub_registers &iv) {
-        iv.res = 0ull;
+        iv.res = 0;
     }
 
 };
diff --git a/sc/rtl/riverlib/core/arith/int_div.cpp b/sc/rtl/riverlib/core/arith/int_div.cpp
index d91a102ea..7ad05a1f4 100644
--- a/sc/rtl/riverlib/core/arith/int_div.cpp
+++ b/sc/rtl/riverlib/core/arith/int_div.cpp
@@ -139,7 +139,7 @@ void IntDiv::comb() {
     sc_uint<64> vb_div;
     bool v_a1_m0;                                           // a1 == -0ll
     bool v_a2_m1;                                           // a2 == -1ll
-    sc_uint<1> v_ena;                                       // 1
+    sc_uint<1> v_ena;
     sc_biguint<120> t_divisor;
 
     v_invert64 = 0;
diff --git a/sc/rtl/riverlib/core/arith/int_div.h b/sc/rtl/riverlib/core/arith/int_div.h
index 8f81050bf..e82a4bbde 100644
--- a/sc/rtl/riverlib/core/arith/int_div.h
+++ b/sc/rtl/riverlib/core/arith/int_div.h
@@ -73,13 +73,13 @@ SC_MODULE(IntDiv) {
         iv.overflow = 0;
         iv.busy = 0;
         iv.ena = 0;
-        iv.divident_i = 0ull;
-        iv.divisor_i = 0ull;
-        iv.bits_i = 0ull;
-        iv.result = 0ull;
-        iv.reference_div = 0ull;
+        iv.divident_i = 0;
+        iv.divisor_i = 0;
+        iv.bits_i = 0;
+        iv.result = 0;
+        iv.reference_div = 0;
         iv.a1_dbg = 0ull;
-        iv.a2_dbg = 0ull;
+        iv.a2_dbg = 0;
     }
 
     sc_signal<sc_biguint<124>> wb_divisor0_i;
diff --git a/sc/rtl/riverlib/core/arith/int_mul.cpp b/sc/rtl/riverlib/core/arith/int_mul.cpp
index f267426bc..873cffbd3 100644
--- a/sc/rtl/riverlib/core/arith/int_mul.cpp
+++ b/sc/rtl/riverlib/core/arith/int_mul.cpp
@@ -291,16 +291,16 @@ void IntMul::comb() {
     if (!async_reset_ && i_nrst.read() == 0) {
         v.busy = 0;
         v.ena = 0;
-        v.a1 = 0ull;
-        v.a2 = 0ull;
+        v.a1 = 0;
+        v.a2 = 0;
         v.unsign = 0;
         v.high = 0;
         v.rv32 = 0;
         v.zero = 0;
         v.inv = 0;
-        v.result = 0ull;
-        v.a1_dbg = 0ull;
-        v.a2_dbg = 0ull;
+        v.result = 0;
+        v.a1_dbg = 0;
+        v.a2_dbg = 0;
         v.reference_mul = 0ull;
         for (int i = 0; i < 16; i++) {
             v.lvl1[i] = 0ull;
@@ -318,16 +318,16 @@ void IntMul::registers() {
     if (async_reset_ && i_nrst.read() == 0) {
         r.busy = 0;
         r.ena = 0;
-        r.a1 = 0ull;
-        r.a2 = 0ull;
+        r.a1 = 0;
+        r.a2 = 0;
         r.unsign = 0;
         r.high = 0;
         r.rv32 = 0;
         r.zero = 0;
         r.inv = 0;
-        r.result = 0ull;
-        r.a1_dbg = 0ull;
-        r.a2_dbg = 0ull;
+        r.result = 0;
+        r.a1_dbg = 0;
+        r.a2_dbg = 0;
         r.reference_mul = 0ull;
         for (int i = 0; i < 16; i++) {
             r.lvl1[i] = 0ull;
diff --git a/sc/rtl/riverlib/core/arith/shift.h b/sc/rtl/riverlib/core/arith/shift.h
index b239e1292..36522f9e1 100644
--- a/sc/rtl/riverlib/core/arith/shift.h
+++ b/sc/rtl/riverlib/core/arith/shift.h
@@ -47,7 +47,7 @@ SC_MODULE(Shifter) {
     } v, r;
 
     void Shifter_r_reset(Shifter_registers &iv) {
-        iv.res = 0ull;
+        iv.res = 0;
     }
 
 };
diff --git a/sc/rtl/riverlib/core/bp_btb.cpp b/sc/rtl/riverlib/core/bp_btb.cpp
index 107afea75..caaca868c 100644
--- a/sc/rtl/riverlib/core/bp_btb.cpp
+++ b/sc/rtl/riverlib/core/bp_btb.cpp
@@ -149,7 +149,7 @@ void BpBTB::comb() {
     if ((!async_reset_ && i_nrst.read() == 0) || i_flush_pipeline) {
         for (int i = 0; i < CFG_BTB_SIZE; i++) {
             v.btb[i].pc = ~0ull;
-            v.btb[i].npc = 0ull;
+            v.btb[i].npc = 0;
             v.btb[i].exec = 0;
         }
     }
@@ -165,7 +165,7 @@ void BpBTB::registers() {
     if (async_reset_ && i_nrst.read() == 0) {
         for (int i = 0; i < CFG_BTB_SIZE; i++) {
             r.btb[i].pc = ~0ull;
-            r.btb[i].npc = 0ull;
+            r.btb[i].npc = 0;
             r.btb[i].exec = 0;
         }
     } else {
diff --git a/sc/rtl/riverlib/core/csr.cpp b/sc/rtl/riverlib/core/csr.cpp
index d13b57820..0f12c00ae 100644
--- a/sc/rtl/riverlib/core/csr.cpp
+++ b/sc/rtl/riverlib/core/csr.cpp
@@ -1302,18 +1302,18 @@ void CsrRegs::comb() {
         v.irq_pending = 0;
         v.cmd_type = 0;
         v.cmd_addr = 0;
-        v.cmd_data = 0ull;
+        v.cmd_data = 0;
         v.cmd_exception = 0;
         v.progbuf_end = 0;
         v.progbuf_err = 0;
         v.mip_ssip = 0;
         v.mip_stip = 0;
         v.mip_seip = 0;
-        v.medeleg = 0ull;
+        v.medeleg = 0;
         v.mideleg = 0;
         v.mcountinhibit = 0;
-        v.mstackovr = 0ull;
-        v.mstackund = 0ull;
+        v.mstackovr = 0;
+        v.mstackund = 0;
         v.mmu_ena = 0;
         v.satp_ppn = 0ull;
         v.satp_sv39 = 0;
@@ -1328,11 +1328,11 @@ void CsrRegs::comb() {
         v.ex_fpu_overflow = 0;
         v.ex_fpu_underflow = 0;
         v.ex_fpu_inexact = 0;
-        v.trap_addr = 0ull;
+        v.trap_addr = 0;
         v.mcycle_cnt = 0ull;
         v.minstret_cnt = 0ull;
-        v.dscratch0 = 0ull;
-        v.dscratch1 = 0ull;
+        v.dscratch0 = 0;
+        v.dscratch1 = 0;
         v.dpc = CFG_RESET_VECTOR;
         v.halt_cause = 0;
         v.dcsr_ebreakm = 0;
@@ -1347,8 +1347,8 @@ void CsrRegs::comb() {
         v.pmp_ena = 0;
         v.pmp_we = 0;
         v.pmp_region = 0;
-        v.pmp_start_addr = 0ull;
-        v.pmp_end_addr = 0ull;
+        v.pmp_start_addr = 0;
+        v.pmp_end_addr = 0;
         v.pmp_flags = 0;
     }
 
@@ -1412,18 +1412,18 @@ void CsrRegs::registers() {
         r.irq_pending = 0;
         r.cmd_type = 0;
         r.cmd_addr = 0;
-        r.cmd_data = 0ull;
+        r.cmd_data = 0;
         r.cmd_exception = 0;
         r.progbuf_end = 0;
         r.progbuf_err = 0;
         r.mip_ssip = 0;
         r.mip_stip = 0;
         r.mip_seip = 0;
-        r.medeleg = 0ull;
+        r.medeleg = 0;
         r.mideleg = 0;
         r.mcountinhibit = 0;
-        r.mstackovr = 0ull;
-        r.mstackund = 0ull;
+        r.mstackovr = 0;
+        r.mstackund = 0;
         r.mmu_ena = 0;
         r.satp_ppn = 0ull;
         r.satp_sv39 = 0;
@@ -1438,11 +1438,11 @@ void CsrRegs::registers() {
         r.ex_fpu_overflow = 0;
         r.ex_fpu_underflow = 0;
         r.ex_fpu_inexact = 0;
-        r.trap_addr = 0ull;
+        r.trap_addr = 0;
         r.mcycle_cnt = 0ull;
         r.minstret_cnt = 0ull;
-        r.dscratch0 = 0ull;
-        r.dscratch1 = 0ull;
+        r.dscratch0 = 0;
+        r.dscratch1 = 0;
         r.dpc = CFG_RESET_VECTOR;
         r.halt_cause = 0;
         r.dcsr_ebreakm = 0;
@@ -1457,8 +1457,8 @@ void CsrRegs::registers() {
         r.pmp_ena = 0;
         r.pmp_we = 0;
         r.pmp_region = 0;
-        r.pmp_start_addr = 0ull;
-        r.pmp_end_addr = 0ull;
+        r.pmp_start_addr = 0;
+        r.pmp_end_addr = 0;
         r.pmp_flags = 0;
     } else {
         for (int i = 0; i < 4; i++) {
diff --git a/sc/rtl/riverlib/core/dbg_port.h b/sc/rtl/riverlib/core/dbg_port.h
index 0b19c0d87..f51b53dc2 100644
--- a/sc/rtl/riverlib/core/dbg_port.h
+++ b/sc/rtl/riverlib/core/dbg_port.h
@@ -119,18 +119,18 @@ SC_MODULE(DbgPort) {
 
     void DbgPort_r_reset(DbgPort_registers &iv) {
         iv.dport_write = 0;
-        iv.dport_addr = 0ull;
-        iv.dport_wdata = 0ull;
-        iv.dport_rdata = 0ull;
+        iv.dport_addr = 0;
+        iv.dport_wdata = 0;
+        iv.dport_rdata = 0;
         iv.dport_size = 0;
         iv.dstate = idle;
-        iv.rdata = 0ull;
+        iv.rdata = 0;
         iv.stack_trace_cnt = 0;
         iv.req_accepted = 0;
         iv.resp_error = 0;
         iv.progbuf_ena = 0;
-        iv.progbuf_pc = 0ull;
-        iv.progbuf_instr = 0ull;
+        iv.progbuf_pc = 0;
+        iv.progbuf_instr = 0;
     }
 
     sc_signal<sc_uint<CFG_LOG2_STACK_TRACE_ADDR>> wb_stack_raddr;
diff --git a/sc/rtl/riverlib/core/dec_rv.h b/sc/rtl/riverlib/core/dec_rv.h
index 409972c45..7257c6134 100644
--- a/sc/rtl/riverlib/core/dec_rv.h
+++ b/sc/rtl/riverlib/core/dec_rv.h
@@ -114,7 +114,7 @@ SC_MODULE(DecoderRv) {
     void DecoderRv_r_reset(DecoderRv_registers &iv) {
         iv.pc = ~0ull;
         iv.isa_type = 0;
-        iv.instr_vec = 0ull;
+        iv.instr_vec = 0;
         iv.instr = ~0ul;
         iv.memop_store = 0;
         iv.memop_load = 0;
@@ -132,7 +132,7 @@ SC_MODULE(DecoderRv) {
         iv.radr2 = 0;
         iv.waddr = 0;
         iv.csr_addr = 0;
-        iv.imm = 0ull;
+        iv.imm = 0;
         iv.progbuf_ena = 0;
     }
 
diff --git a/sc/rtl/riverlib/core/dec_rvc.h b/sc/rtl/riverlib/core/dec_rvc.h
index e27952671..71f95c7cc 100644
--- a/sc/rtl/riverlib/core/dec_rvc.h
+++ b/sc/rtl/riverlib/core/dec_rvc.h
@@ -109,7 +109,7 @@ SC_MODULE(DecoderRvc) {
     void DecoderRvc_r_reset(DecoderRvc_registers &iv) {
         iv.pc = ~0ull;
         iv.isa_type = 0;
-        iv.instr_vec = 0ull;
+        iv.instr_vec = 0;
         iv.instr = ~0ul;
         iv.memop_store = 0;
         iv.memop_load = 0;
@@ -122,7 +122,7 @@ SC_MODULE(DecoderRvc) {
         iv.radr1 = 0;
         iv.radr2 = 0;
         iv.waddr = 0;
-        iv.imm = 0ull;
+        iv.imm = 0;
         iv.progbuf_ena = 0;
     }
 
diff --git a/sc/rtl/riverlib/core/decoder.cpp b/sc/rtl/riverlib/core/decoder.cpp
index 211a48b63..61696fd6a 100644
--- a/sc/rtl/riverlib/core/decoder.cpp
+++ b/sc/rtl/riverlib/core/decoder.cpp
@@ -329,7 +329,7 @@ void InstrDecoder::comb() {
         for (int i = 0; i < FULL_DEC_DEPTH; i++) {
             v.d[i].pc = ~0ull;
             v.d[i].isa_type = 0;
-            v.d[i].instr_vec = 0ull;
+            v.d[i].instr_vec = 0;
             v.d[i].instr = ~0ul;
             v.d[i].memop_store = 0;
             v.d[i].memop_load = 0;
@@ -347,7 +347,7 @@ void InstrDecoder::comb() {
             v.d[i].radr2 = 0;
             v.d[i].waddr = 0;
             v.d[i].csr_addr = 0;
-            v.d[i].imm = 0ull;
+            v.d[i].imm = 0;
             v.d[i].progbuf_ena = 0;
         }
     }
@@ -381,7 +381,7 @@ void InstrDecoder::registers() {
         for (int i = 0; i < FULL_DEC_DEPTH; i++) {
             r.d[i].pc = ~0ull;
             r.d[i].isa_type = 0;
-            r.d[i].instr_vec = 0ull;
+            r.d[i].instr_vec = 0;
             r.d[i].instr = ~0ul;
             r.d[i].memop_store = 0;
             r.d[i].memop_load = 0;
@@ -399,7 +399,7 @@ void InstrDecoder::registers() {
             r.d[i].radr2 = 0;
             r.d[i].waddr = 0;
             r.d[i].csr_addr = 0;
-            r.d[i].imm = 0ull;
+            r.d[i].imm = 0;
             r.d[i].progbuf_ena = 0;
         }
     } else {
diff --git a/sc/rtl/riverlib/core/execute.h b/sc/rtl/riverlib/core/execute.h
index b4081ecbd..034d88c2c 100644
--- a/sc/rtl/riverlib/core/execute.h
+++ b/sc/rtl/riverlib/core/execute.h
@@ -248,19 +248,19 @@ SC_MODULE(InstrExecute) {
         iv.state = State_Idle;
         iv.csrstate = CsrState_Idle;
         iv.amostate = AmoState_WaitMemAccess;
-        iv.pc = 0ull;
+        iv.pc = 0;
         iv.npc = CFG_RESET_VECTOR;
-        iv.dnpc = 0ull;
+        iv.dnpc = 0;
         iv.radr1 = 0;
         iv.radr2 = 0;
         iv.waddr = 0;
-        iv.rdata1 = 0ull;
-        iv.rdata2 = 0ull;
-        iv.rdata1_amo = 0ull;
-        iv.rdata2_amo = 0ull;
-        iv.ivec = 0ull;
+        iv.rdata1 = 0;
+        iv.rdata2 = 0;
+        iv.rdata1_amo = 0;
+        iv.rdata2_amo = 0;
+        iv.ivec = 0;
         iv.isa_type = 0;
-        iv.imm = 0ull;
+        iv.imm = 0;
         iv.instr = 0;
         iv.tagcnt = 0ull;
         iv.reg_write = 0;
@@ -269,15 +269,15 @@ SC_MODULE(InstrExecute) {
         iv.csr_req_rmw = 0;
         iv.csr_req_type = 0;
         iv.csr_req_addr = 0;
-        iv.csr_req_data = 0ull;
+        iv.csr_req_data = 0;
         iv.memop_valid = 0;
         iv.memop_debug = 0;
         iv.memop_halted = 0;
         iv.memop_type = 0;
         iv.memop_sign_ext = 0;
         iv.memop_size = 0;
-        iv.memop_memaddr = 0ull;
-        iv.memop_wdata = 0ull;
+        iv.memop_memaddr = 0;
+        iv.memop_wdata = 0;
         iv.unsigned_op = 0;
         iv.rv32 = 0;
         iv.compressed = 0;
@@ -288,10 +288,10 @@ SC_MODULE(InstrExecute) {
         iv.mem_ex_store_fault = 0;
         iv.page_fault_r = 0;
         iv.page_fault_w = 0;
-        iv.mem_ex_addr = 0ull;
-        iv.res_npc = 0ull;
-        iv.res_ra = 0ull;
-        iv.res_csr = 0ull;
+        iv.mem_ex_addr = 0;
+        iv.res_npc = 0;
+        iv.res_ra = 0;
+        iv.res_csr = 0;
         iv.select = 0;
         iv.valid = 0;
         iv.call = 0;
diff --git a/sc/rtl/riverlib/core/fetch.h b/sc/rtl/riverlib/core/fetch.h
index 16d8fa7d6..cc90bf534 100644
--- a/sc/rtl/riverlib/core/fetch.h
+++ b/sc/rtl/riverlib/core/fetch.h
@@ -83,7 +83,7 @@ SC_MODULE(InstrFetch) {
         iv.req_addr = ~0ull;
         iv.mem_resp_shadow = ~0ull;
         iv.pc = ~0ull;
-        iv.instr = 0ull;
+        iv.instr = 0;
         iv.instr_load_fault = 0;
         iv.instr_page_fault_x = 0;
         iv.progbuf_ena = 0;
diff --git a/sc/rtl/riverlib/core/fpu_d/d2l_d.h b/sc/rtl/riverlib/core/fpu_d/d2l_d.h
index 9851cf942..3ec9d683b 100644
--- a/sc/rtl/riverlib/core/fpu_d/d2l_d.h
+++ b/sc/rtl/riverlib/core/fpu_d/d2l_d.h
@@ -65,11 +65,11 @@ SC_MODULE(Double2Long) {
         iv.ena = 0;
         iv.signA = 0;
         iv.expA = 0;
-        iv.mantA = 0ull;
-        iv.result = 0ull;
+        iv.mantA = 0;
+        iv.result = 0;
         iv.op_signed = 0;
         iv.w32 = 0;
-        iv.mantPostScale = 0ull;
+        iv.mantPostScale = 0;
         iv.overflow = 0;
         iv.underflow = 0;
     }
diff --git a/sc/rtl/riverlib/core/fpu_d/fadd_d.h b/sc/rtl/riverlib/core/fpu_d/fadd_d.h
index b833c81fc..b25781ade 100644
--- a/sc/rtl/riverlib/core/fpu_d/fadd_d.h
+++ b/sc/rtl/riverlib/core/fpu_d/fadd_d.h
@@ -87,9 +87,9 @@ SC_MODULE(DoubleAdd) {
     void DoubleAdd_r_reset(DoubleAdd_registers &iv) {
         iv.busy = 0;
         iv.ena = 0;
-        iv.a = 0ull;
-        iv.b = 0ull;
-        iv.result = 0ull;
+        iv.a = 0;
+        iv.b = 0;
+        iv.result = 0;
         iv.illegal_op = 0;
         iv.overflow = 0;
         iv.add = 0;
@@ -105,15 +105,15 @@ SC_MODULE(DoubleAdd) {
         iv.preShift = 0;
         iv.signOpMore = 0;
         iv.expMore = 0;
-        iv.mantMore = 0ull;
-        iv.mantLess = 0ull;
-        iv.mantLessScale = 0ull;
-        iv.mantSum = 0ull;
+        iv.mantMore = 0;
+        iv.mantLess = 0;
+        iv.mantLessScale = 0;
+        iv.mantSum = 0;
         iv.lshift = 0;
-        iv.mantAlign = 0ull;
+        iv.mantAlign = 0;
         iv.expPostScale = 0;
         iv.expPostScaleInv = 0;
-        iv.mantPostScale = 0ull;
+        iv.mantPostScale = 0;
     }
 
 };
diff --git a/sc/rtl/riverlib/core/fpu_d/fdiv_d.h b/sc/rtl/riverlib/core/fpu_d/fdiv_d.h
index ff9e5f999..60283228c 100644
--- a/sc/rtl/riverlib/core/fpu_d/fdiv_d.h
+++ b/sc/rtl/riverlib/core/fpu_d/fdiv_d.h
@@ -73,18 +73,18 @@ SC_MODULE(DoubleDiv) {
     void DoubleDiv_r_reset(DoubleDiv_registers &iv) {
         iv.busy = 0;
         iv.ena = 0;
-        iv.a = 0ull;
-        iv.b = 0ull;
-        iv.result = 0ull;
+        iv.a = 0;
+        iv.b = 0;
+        iv.result = 0;
         iv.zeroA = 0;
         iv.zeroB = 0;
-        iv.divisor = 0ull;
+        iv.divisor = 0;
         iv.preShift = 0;
         iv.expAB = 0;
         iv.expAlign = 0;
-        iv.mantAlign = 0ull;
+        iv.mantAlign = 0;
         iv.postShift = 0;
-        iv.mantPostScale = 0ull;
+        iv.mantPostScale = 0;
         iv.nanRes = 0;
         iv.overflow = 0;
         iv.underflow = 0;
diff --git a/sc/rtl/riverlib/core/fpu_d/fmul_d.h b/sc/rtl/riverlib/core/fpu_d/fmul_d.h
index a39318dc2..913f7b305 100644
--- a/sc/rtl/riverlib/core/fpu_d/fmul_d.h
+++ b/sc/rtl/riverlib/core/fpu_d/fmul_d.h
@@ -71,18 +71,18 @@ SC_MODULE(DoubleMul) {
     void DoubleMul_r_reset(DoubleMul_registers &iv) {
         iv.busy = 0;
         iv.ena = 0;
-        iv.a = 0ull;
-        iv.b = 0ull;
-        iv.result = 0ull;
+        iv.a = 0;
+        iv.b = 0;
+        iv.result = 0;
         iv.zeroA = 0;
         iv.zeroB = 0;
-        iv.mantA = 0ull;
-        iv.mantB = 0ull;
+        iv.mantA = 0;
+        iv.mantB = 0;
         iv.expAB = 0;
         iv.expAlign = 0;
-        iv.mantAlign = 0ull;
+        iv.mantAlign = 0;
         iv.postShift = 0;
-        iv.mantPostScale = 0ull;
+        iv.mantPostScale = 0;
         iv.nanA = 0;
         iv.nanB = 0;
         iv.overflow = 0;
diff --git a/sc/rtl/riverlib/core/fpu_d/fpu_top.h b/sc/rtl/riverlib/core/fpu_d/fpu_top.h
index c5c244c99..8b7b099e1 100644
--- a/sc/rtl/riverlib/core/fpu_d/fpu_top.h
+++ b/sc/rtl/riverlib/core/fpu_d/fpu_top.h
@@ -79,9 +79,9 @@ SC_MODULE(FpuTop) {
         iv.ivec = 0;
         iv.busy = 0;
         iv.ready = 0;
-        iv.a = 0ull;
-        iv.b = 0ull;
-        iv.result = 0ull;
+        iv.a = 0;
+        iv.b = 0;
+        iv.result = 0;
         iv.ex_invalidop = 0;
         iv.ex_divbyzero = 0;
         iv.ex_overflow = 0;
diff --git a/sc/rtl/riverlib/core/fpu_d/idiv53.h b/sc/rtl/riverlib/core/fpu_d/idiv53.h
index 8b7a1074a..91ea1fa92 100644
--- a/sc/rtl/riverlib/core/fpu_d/idiv53.h
+++ b/sc/rtl/riverlib/core/fpu_d/idiv53.h
@@ -62,9 +62,9 @@ SC_MODULE(idiv53) {
         iv.delay = 0;
         iv.lshift = 0;
         iv.lshift_rdy = 0;
-        iv.divisor = 0ull;
-        iv.divident = 0ull;
-        iv.bits = 0ull;
+        iv.divisor = 0;
+        iv.divident = 0;
+        iv.bits = 0;
         iv.overflow = 0;
         iv.zero_resid = 0;
     }
diff --git a/sc/rtl/riverlib/core/fpu_d/imul53.h b/sc/rtl/riverlib/core/fpu_d/imul53.h
index 097108da8..a68c91e7b 100644
--- a/sc/rtl/riverlib/core/fpu_d/imul53.h
+++ b/sc/rtl/riverlib/core/fpu_d/imul53.h
@@ -59,8 +59,8 @@ SC_MODULE(imul53) {
         iv.delay = 0;
         iv.shift = 0;
         iv.accum_ena = 0;
-        iv.b = 0ull;
-        iv.sum = 0ull;
+        iv.b = 0;
+        iv.sum = 0;
         iv.overflow = 0;
     }
 
diff --git a/sc/rtl/riverlib/core/fpu_d/l2d_d.h b/sc/rtl/riverlib/core/fpu_d/l2d_d.h
index dd1b4751a..864d3e0b1 100644
--- a/sc/rtl/riverlib/core/fpu_d/l2d_d.h
+++ b/sc/rtl/riverlib/core/fpu_d/l2d_d.h
@@ -59,10 +59,10 @@ SC_MODULE(Long2Double) {
         iv.busy = 0;
         iv.ena = 0;
         iv.signA = 0;
-        iv.absA = 0ull;
-        iv.result = 0ull;
+        iv.absA = 0;
+        iv.result = 0;
         iv.op_signed = 0;
-        iv.mantAlign = 0ull;
+        iv.mantAlign = 0;
         iv.lshift = 0;
     }
 
diff --git a/sc/rtl/riverlib/core/memaccess.h b/sc/rtl/riverlib/core/memaccess.h
index b9bf6b70e..8f8aac1b9 100644
--- a/sc/rtl/riverlib/core/memaccess.h
+++ b/sc/rtl/riverlib/core/memaccess.h
@@ -133,20 +133,20 @@ SC_MODULE(MemAccess) {
         iv.mmu_sv39 = 0;
         iv.mmu_sv48 = 0;
         iv.memop_type = 0;
-        iv.memop_addr = 0ull;
-        iv.memop_wdata = 0ull;
+        iv.memop_addr = 0;
+        iv.memop_wdata = 0;
         iv.memop_wstrb = 0;
         iv.memop_sign_ext = 0;
         iv.memop_size = 0;
         iv.memop_debug = 0;
-        iv.memop_res_pc = 0ull;
+        iv.memop_res_pc = 0;
         iv.memop_res_instr = 0;
         iv.memop_res_addr = 0;
         iv.memop_res_wtag = 0;
-        iv.memop_res_data = 0ull;
+        iv.memop_res_data = 0;
         iv.memop_res_wena = 0;
-        iv.hold_rdata = 0ull;
-        iv.pc = 0ull;
+        iv.hold_rdata = 0;
+        iv.pc = 0;
         iv.valid = 0;
     }
 
diff --git a/sc/rtl/riverlib/core/mmu.h b/sc/rtl/riverlib/core/mmu.h
index f5e06ffe3..2ef930a58 100644
--- a/sc/rtl/riverlib/core/mmu.h
+++ b/sc/rtl/riverlib/core/mmu.h
@@ -132,9 +132,9 @@ SC_MODULE(Mmu) {
         iv.req_x = 0;
         iv.req_r = 0;
         iv.req_w = 0;
-        iv.req_pa = 0ull;
+        iv.req_pa = 0;
         iv.req_type = 0;
-        iv.req_wdata = 0ull;
+        iv.req_wdata = 0;
         iv.req_wstrb = 0;
         iv.req_size = 0;
         iv.req_flush = 0;
@@ -143,15 +143,15 @@ SC_MODULE(Mmu) {
         iv.last_pa = ~0ull;
         iv.last_permission = 0;
         iv.last_page_size = 0;
-        iv.resp_addr = 0ull;
-        iv.resp_data = 0ull;
+        iv.resp_addr = 0;
+        iv.resp_data = 0;
         iv.resp_load_fault = 0;
         iv.resp_store_fault = 0;
         iv.ex_page_fault = 0;
         iv.tlb_hit = 0;
         iv.tlb_level = 0;
         iv.tlb_page_size = 0;
-        iv.tlb_wdata = 0ull;
+        iv.tlb_wdata = 0;
         iv.tlb_flush_cnt = ~0ul;
         iv.tlb_flush_adr = 0;
     }
diff --git a/sc/rtl/riverlib/core/regibank.cpp b/sc/rtl/riverlib/core/regibank.cpp
index 1299330f8..d70117ff5 100644
--- a/sc/rtl/riverlib/core/regibank.cpp
+++ b/sc/rtl/riverlib/core/regibank.cpp
@@ -202,7 +202,7 @@ void RegIntBank::comb() {
 
     if (!async_reset_ && i_nrst.read() == 0) {
         for (int i = 0; i < REGS_TOTAL; i++) {
-            v.arr[i].val = 0ull;
+            v.arr[i].val = 0;
             v.arr[i].tag = 0;
         }
     }
@@ -249,7 +249,7 @@ void RegIntBank::comb() {
 void RegIntBank::registers() {
     if (async_reset_ && i_nrst.read() == 0) {
         for (int i = 0; i < REGS_TOTAL; i++) {
-            r.arr[i].val = 0ull;
+            r.arr[i].val = 0;
             r.arr[i].tag = 0;
         }
     } else {
diff --git a/sc/rtl/riverlib/core/tracer.cpp b/sc/rtl/riverlib/core/tracer.cpp
index de953b07d..eb2a73b5f 100644
--- a/sc/rtl/riverlib/core/tracer.cpp
+++ b/sc/rtl/riverlib/core/tracer.cpp
@@ -1417,21 +1417,21 @@ void Tracer::comb() {
 
     if (!async_reset_ && i_nrst.read() == 0) {
         for (int i = 0; i < TRACE_TBL_SZ; i++) {
-            v.trace_tbl[i].exec_cnt = 0ull;
-            v.trace_tbl[i].pc = 0ull;
+            v.trace_tbl[i].exec_cnt = 0;
+            v.trace_tbl[i].pc = 0;
             v.trace_tbl[i].instr = 0;
             v.trace_tbl[i].regactioncnt = 0;
             v.trace_tbl[i].memactioncnt = 0;
             for (int j = 0; j < TRACE_TBL_SZ; j++) {
                 v.trace_tbl[i].regaction[j].waddr = 0;
-                v.trace_tbl[i].regaction[j].wres = 0ull;
+                v.trace_tbl[i].regaction[j].wres = 0;
             }
             for (int j = 0; j < TRACE_TBL_SZ; j++) {
                 v.trace_tbl[i].memaction[j].store = 0;
                 v.trace_tbl[i].memaction[j].size = 0;
-                v.trace_tbl[i].memaction[j].mask = 0ull;
-                v.trace_tbl[i].memaction[j].memaddr = 0ull;
-                v.trace_tbl[i].memaction[j].data = 0ull;
+                v.trace_tbl[i].memaction[j].mask = 0;
+                v.trace_tbl[i].memaction[j].memaddr = 0;
+                v.trace_tbl[i].memaction[j].data = 0;
                 v.trace_tbl[i].memaction[j].regaddr = 0;
                 v.trace_tbl[i].memaction[j].complete = 0;
                 v.trace_tbl[i].memaction[j].sc_release = 0;
@@ -1449,21 +1449,21 @@ void Tracer::comb() {
 void Tracer::registers() {
     if (async_reset_ && i_nrst.read() == 0) {
         for (int i = 0; i < TRACE_TBL_SZ; i++) {
-            r.trace_tbl[i].exec_cnt = 0ull;
-            r.trace_tbl[i].pc = 0ull;
+            r.trace_tbl[i].exec_cnt = 0;
+            r.trace_tbl[i].pc = 0;
             r.trace_tbl[i].instr = 0;
             r.trace_tbl[i].regactioncnt = 0;
             r.trace_tbl[i].memactioncnt = 0;
             for (int j = 0; j < TRACE_TBL_SZ; j++) {
                 r.trace_tbl[i].regaction[j].waddr = 0;
-                r.trace_tbl[i].regaction[j].wres = 0ull;
+                r.trace_tbl[i].regaction[j].wres = 0;
             }
             for (int j = 0; j < TRACE_TBL_SZ; j++) {
                 r.trace_tbl[i].memaction[j].store = 0;
                 r.trace_tbl[i].memaction[j].size = 0;
-                r.trace_tbl[i].memaction[j].mask = 0ull;
-                r.trace_tbl[i].memaction[j].memaddr = 0ull;
-                r.trace_tbl[i].memaction[j].data = 0ull;
+                r.trace_tbl[i].memaction[j].mask = 0;
+                r.trace_tbl[i].memaction[j].memaddr = 0;
+                r.trace_tbl[i].memaction[j].data = 0;
                 r.trace_tbl[i].memaction[j].regaddr = 0;
                 r.trace_tbl[i].memaction[j].complete = 0;
                 r.trace_tbl[i].memaction[j].sc_release = 0;
diff --git a/sc/rtl/riverlib/dmi/dmidebug.h b/sc/rtl/riverlib/dmi/dmidebug.h
index 8f94778de..36c7cbd3c 100644
--- a/sc/rtl/riverlib/dmi/dmidebug.h
+++ b/sc/rtl/riverlib/dmi/dmidebug.h
@@ -173,10 +173,10 @@ SC_MODULE(dmidebug) {
         iv.data1 = 0;
         iv.data2 = 0;
         iv.data3 = 0;
-        iv.progbuf_data = 0ull;
+        iv.progbuf_data = 0;
         iv.dport_req_valid = 0;
-        iv.dport_addr = 0ull;
-        iv.dport_wdata = 0ull;
+        iv.dport_addr = 0;
+        iv.dport_wdata = 0;
         iv.dport_size = 0;
         iv.dport_resp_ready = 0;
         iv.pready = 0;
diff --git a/sc/rtl/riverlib/dmi/jtagcdc.h b/sc/rtl/riverlib/dmi/jtagcdc.h
index edb5c4231..454b439f3 100644
--- a/sc/rtl/riverlib/dmi/jtagcdc.h
+++ b/sc/rtl/riverlib/dmi/jtagcdc.h
@@ -70,7 +70,7 @@ SC_MODULE(jtagcdc) {
 
     void jtagcdc_r_reset(jtagcdc_registers &iv) {
         iv.l1 = ~0ull;
-        iv.l2 = 0ull;
+        iv.l2 = 0;
         iv.req_valid = 0;
         iv.req_accepted = 0;
         iv.req_write = 0;
diff --git a/sc/rtl/riverlib/ic_axi4_to_l1.h b/sc/rtl/riverlib/ic_axi4_to_l1.h
index dd4eb7117..46c4be814 100644
--- a/sc/rtl/riverlib/ic_axi4_to_l1.h
+++ b/sc/rtl/riverlib/ic_axi4_to_l1.h
@@ -75,19 +75,19 @@ SC_MODULE(ic_axi4_to_l1) {
 
     void ic_axi4_to_l1_r_reset(ic_axi4_to_l1_registers &iv) {
         iv.state = Idle;
-        iv.req_addr = 0ull;
+        iv.req_addr = 0;
         iv.req_id = 0;
         iv.req_user = 0;
         iv.req_wstrb = 0;
-        iv.req_wdata = 0ull;
+        iv.req_wdata = 0;
         iv.req_len = 0;
         iv.req_size = 0;
         iv.req_prot = 0;
         iv.writing = 0;
         iv.read_modify_write = 0;
-        iv.line_data = 0ull;
+        iv.line_data = 0;
         iv.line_wstrb = 0;
-        iv.resp_data = 0ull;
+        iv.resp_data = 0;
     }
 
 };
diff --git a/sc/rtl/riverlib/l2cache/l2_dst.h b/sc/rtl/riverlib/l2cache/l2_dst.h
index f58b2b7dc..643eedcf6 100644
--- a/sc/rtl/riverlib/l2cache/l2_dst.h
+++ b/sc/rtl/riverlib/l2cache/l2_dst.h
@@ -81,12 +81,12 @@ SC_MODULE(L2Destination) {
     void L2Destination_r_reset(L2Destination_registers &iv) {
         iv.state = Idle;
         iv.srcid = CFG_SLOT_L1_TOTAL;
-        iv.req_addr = 0ull;
+        iv.req_addr = 0;
         iv.req_size = 0;
         iv.req_prot = 0;
         iv.req_src = 0;
         iv.req_type = 0;
-        iv.req_wdata = 0ull;
+        iv.req_wdata = 0;
         iv.req_wstrb = 0;
         iv.ac_valid = 0;
         iv.cr_ready = 0;
diff --git a/sc/rtl/riverlib/l2cache/l2cache_lru.h b/sc/rtl/riverlib/l2cache/l2cache_lru.h
index 587935117..f2328ae5c 100644
--- a/sc/rtl/riverlib/l2cache/l2cache_lru.h
+++ b/sc/rtl/riverlib/l2cache/l2cache_lru.h
@@ -120,13 +120,13 @@ SC_MODULE(L2CacheLru) {
         iv.req_type = 0;
         iv.req_size = 0;
         iv.req_prot = 0;
-        iv.req_addr = 0ull;
-        iv.req_wdata = 0ull;
+        iv.req_addr = 0;
+        iv.req_wdata = 0;
         iv.req_wstrb = 0;
         iv.state = State_Reset;
         iv.req_mem_valid = 0;
         iv.req_mem_type = 0;
-        iv.mem_addr = 0ull;
+        iv.mem_addr = 0;
         iv.rb_resp = 0;
         iv.write_first = 0;
         iv.write_flush = 0;
@@ -136,8 +136,8 @@ SC_MODULE(L2CacheLru) {
         iv.req_flush_addr = 0ull;
         iv.req_flush_cnt = 0;
         iv.flush_cnt = 0;
-        iv.cache_line_i = 0ull;
-        iv.cache_line_o = 0ull;
+        iv.cache_line_i = 0;
+        iv.cache_line_o = 0;
     }
 
     sc_signal<bool> line_direct_access_i;
diff --git a/sc/rtl/riverlib/l2cache/l2dummy.h b/sc/rtl/riverlib/l2cache/l2dummy.h
index d82af410a..d702b4e64 100644
--- a/sc/rtl/riverlib/l2cache/l2dummy.h
+++ b/sc/rtl/riverlib/l2cache/l2dummy.h
@@ -72,15 +72,15 @@ SC_MODULE(L2Dummy) {
     void L2Dummy_r_reset(L2Dummy_registers &iv) {
         iv.state = Idle;
         iv.srcid = CFG_SLOT_L1_TOTAL;
-        iv.req_addr = 0ull;
+        iv.req_addr = 0;
         iv.req_size = 0;
         iv.req_prot = 0;
         iv.req_lock = 0;
         iv.req_id = 0;
         iv.req_user = 0;
-        iv.req_wdata = 0ull;
+        iv.req_wdata = 0;
         iv.req_wstrb = 0;
-        iv.rdata = 0ull;
+        iv.rdata = 0;
         iv.resp = 0;
     }
 
diff --git a/sc/rtl/riverlib/l2cache/l2serdes.h b/sc/rtl/riverlib/l2cache/l2serdes.h
index 2c690e57f..55ecdc29f 100644
--- a/sc/rtl/riverlib/l2cache/l2serdes.h
+++ b/sc/rtl/riverlib/l2cache/l2serdes.h
@@ -69,7 +69,7 @@ SC_MODULE(L2SerDes) {
         iv.state = State_Idle;
         iv.req_len = 0;
         iv.b_wait = 0;
-        iv.line = 0ull;
+        iv.line = 0;
         iv.wstrb = 0;
         iv.rmux = 0;
     }
diff --git a/sc/rtl/riverlib/river_amba.h b/sc/rtl/riverlib/river_amba.h
index f94878f6f..344d24cfa 100644
--- a/sc/rtl/riverlib/river_amba.h
+++ b/sc/rtl/riverlib/river_amba.h
@@ -102,18 +102,18 @@ SC_MODULE(RiverAmba) {
         iv.req_addr = state_idle;
         iv.req_path = 0;
         iv.req_cached = 0;
-        iv.req_wdata = 0ull;
+        iv.req_wdata = 0;
         iv.req_wstrb = 0;
         iv.req_size = 0;
         iv.req_prot = 0;
         iv.req_ar_snoop = 0;
         iv.req_aw_snoop = 0;
         iv.snoop_state = snoop_idle;
-        iv.ac_addr = 0ull;
+        iv.ac_addr = 0;
         iv.ac_snoop = 0;
         iv.cr_resp = 0;
         iv.req_snoop_type = 0;
-        iv.resp_snoop_data = 0ull;
+        iv.resp_snoop_data = 0;
         iv.cache_access = 0;
     }
 
diff --git a/sc/rtl/riverlib/river_cfg.h b/sc/rtl/riverlib/river_cfg.h
index 65d533830..a5c347bbc 100644
--- a/sc/rtl/riverlib/river_cfg.h
+++ b/sc/rtl/riverlib/river_cfg.h
@@ -21,8 +21,8 @@ namespace debugger {
 
 static const uint32_t CFG_VENDOR_ID = 0x000000F1;
 static const uint32_t CFG_IMPLEMENTATION_ID = 0x20220813;
-static const bool CFG_HW_FPU_ENABLE = true;
-static const bool CFG_TRACER_ENABLE = false;
+static const bool CFG_HW_FPU_ENABLE = 1;
+static const bool CFG_TRACER_ENABLE = 0;
 
 // Architectural size definition
 static const int RISCV_ARCH = 64;
diff --git a/sc/rtl/sdctrl/sdctrl_cache.h b/sc/rtl/sdctrl/sdctrl_cache.h
index 17e9c736a..07d473916 100644
--- a/sc/rtl/sdctrl/sdctrl_cache.h
+++ b/sc/rtl/sdctrl/sdctrl_cache.h
@@ -106,21 +106,21 @@ SC_MODULE(sdctrl_cache) {
 
     void sdctrl_cache_r_reset(sdctrl_cache_registers &iv) {
         iv.req_write = 0;
-        iv.req_addr = 0ull;
-        iv.req_wdata = 0ull;
+        iv.req_addr = 0;
+        iv.req_wdata = 0;
         iv.req_wstrb = 0;
         iv.state = State_Reset;
         iv.req_mem_valid = 0;
         iv.req_mem_write = 0;
-        iv.mem_addr = 0ull;
+        iv.mem_addr = 0;
         iv.mem_fault = 0;
         iv.write_first = 0;
         iv.write_flush = 0;
         iv.req_flush = 0;
         iv.flush_cnt = 0;
-        iv.line_addr_i = 0ull;
-        iv.cache_line_i = 0ull;
-        iv.cache_line_o = 0ull;
+        iv.line_addr_i = 0;
+        iv.cache_line_i = 0;
+        iv.cache_line_o = 0;
     }
 
     sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_wdata_i;
diff --git a/sc/rtl/sdctrl/sdctrl_cmd_transmitter.h b/sc/rtl/sdctrl/sdctrl_cmd_transmitter.h
index 30bf399b9..383f4b741 100644
--- a/sc/rtl/sdctrl/sdctrl_cmd_transmitter.h
+++ b/sc/rtl/sdctrl/sdctrl_cmd_transmitter.h
@@ -115,7 +115,7 @@ SC_MODULE(sdctrl_cmd_transmitter) {
         iv.cmdshift = ~0ull;
         iv.cmdmirror = 0;
         iv.regshift = 0;
-        iv.cidshift = 0ull;
+        iv.cidshift = 0;
         iv.crc_calc = 0;
         iv.crc_rx = 0;
         iv.cmdbitcnt = 0;
diff --git a/sc/rtl/sdctrl/sdctrl_sdmode.h b/sc/rtl/sdctrl/sdctrl_sdmode.h
index 63519cb39..3b9d11d33 100644
--- a/sc/rtl/sdctrl/sdctrl_sdmode.h
+++ b/sc/rtl/sdctrl/sdctrl_sdmode.h
@@ -159,7 +159,7 @@ SC_MODULE(sdctrl_sdmode) {
         iv.cmd_resp_cmd = 0;
         iv.cmd_resp_arg32 = 0;
         iv.data_addr = 0;
-        iv.data_data = 0ull;
+        iv.data_data = 0;
         iv.data_resp_valid = 0;
         iv.wdog_ena = 0;
         iv.crc16_clear = 1;
diff --git a/sc/rtl/sdctrl/sdctrl_spimode.h b/sc/rtl/sdctrl/sdctrl_spimode.h
index cb17f706b..7fa615076 100644
--- a/sc/rtl/sdctrl/sdctrl_spimode.h
+++ b/sc/rtl/sdctrl/sdctrl_spimode.h
@@ -131,7 +131,7 @@ SC_MODULE(sdctrl_spimode) {
         iv.cmd_resp_r1 = 0;
         iv.cmd_resp_r2 = 0;
         iv.data_addr = 0;
-        iv.data_data = 0ull;
+        iv.data_data = 0;
         iv.data_resp_valid = 0;
         iv.wdog_ena = 0;
         iv.crc16_clear = 1;