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[*] rtlgen update: initialization updated now applied to systemc (as …
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…previous commit into sv)
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@sergeykhbr
sergeykhbr committed Nov 25, 2023
1 parent 16ed9ac commit 77547ee
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Showing 50 changed files with 200 additions and 200 deletions.
2 changes: 1 addition & 1 deletion sc/prj/common/vips/sdcard/vip_sdcard_ctrl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,7 @@ SC_MODULE(vip_sdcard_ctrl) {
iv.ocr_hcs = 0;
iv.ocr_vdd_window = 0;
iv.req_mem_valid = 0;
iv.req_mem_addr = 0ull;
iv.req_mem_addr = 0;
iv.shiftdat = ~0ul;
iv.bitcnt = 0;
iv.crc16_clear = 0;
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4 changes: 2 additions & 2 deletions sc/rtl/ambalib/axi2apb_bus1.h
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Expand Up @@ -75,8 +75,8 @@ SC_MODULE(axi2apb_bus1) {
iv.selidx = 0;
iv.pvalid = 0;
iv.paddr = 0;
iv.pwdata = 0ull;
iv.prdata = 0ull;
iv.pwdata = 0;
iv.prdata = 0;
iv.pwrite = 0;
iv.pstrb = 0;
iv.pprot = 0;
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6 changes: 3 additions & 3 deletions sc/rtl/ambalib/axi_slv.h
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Expand Up @@ -90,9 +90,9 @@ SC_MODULE(axi_slv) {
void axi_slv_r_reset(axi_slv_registers &iv) {
iv.state = State_Idle;
iv.req_valid = 0;
iv.req_addr = 0ull;
iv.req_addr = 0;
iv.req_write = 0;
iv.req_wdata = 0ull;
iv.req_wdata = 0;
iv.req_wstrb = 0;
iv.req_xsize = 0;
iv.req_len = 0;
Expand All @@ -104,7 +104,7 @@ SC_MODULE(axi_slv) {
iv.req_done = 0;
iv.resp_valid = 0;
iv.resp_last = 0;
iv.resp_rdata = 0ull;
iv.resp_rdata = 0;
iv.resp_err = 0;
}

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8 changes: 4 additions & 4 deletions sc/rtl/misclib/clint.h
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Expand Up @@ -234,13 +234,13 @@ void clint<cpu_total>::comb() {
v.rdata = vrdata;

if (!async_reset_ && i_nrst.read() == 0) {
v.mtime = 0ull;
v.mtime = 0;
for (int i = 0; i < cpu_total; i++) {
v.hart[i].msip = 0;
v.hart[i].mtip = 0;
v.hart[i].mtimecmp = 0ull;
}
v.rdata = 0ull;
v.rdata = 0;
}

for (int i = 0; i < cpu_total; i++) {
Expand All @@ -260,13 +260,13 @@ void clint<cpu_total>::comb() {
template<int cpu_total>
void clint<cpu_total>::registers() {
if (async_reset_ && i_nrst.read() == 0) {
r.mtime = 0ull;
r.mtime = 0;
for (int i = 0; i < cpu_total; i++) {
r.hart[i].msip = 0;
r.hart[i].mtip = 0;
r.hart[i].mtimecmp = 0ull;
}
r.rdata = 0ull;
r.rdata = 0;
} else {
r.mtime = v.mtime;
for (int i = 0; i < cpu_total; i++) {
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12 changes: 6 additions & 6 deletions sc/rtl/misclib/plic.h
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Expand Up @@ -367,8 +367,8 @@ void plic<ctxmax, irqmax>::comb() {
}

if (!async_reset_ && i_nrst.read() == 0) {
v.src_priority = 0ull;
v.pending = 0ull;
v.src_priority = 0;
v.pending = 0;
v.ip = 0;
for (int i = 0; i < ctxmax; i++) {
v.ctx[i].priority_th = 0;
Expand All @@ -379,7 +379,7 @@ void plic<ctxmax, irqmax>::comb() {
v.ctx[i].irq_idx = 0;
v.ctx[i].irq_prio = 0;
}
v.rdata = 0ull;
v.rdata = 0;
}

w_req_ready = 1;
Expand All @@ -392,8 +392,8 @@ void plic<ctxmax, irqmax>::comb() {
template<int ctxmax, int irqmax>
void plic<ctxmax, irqmax>::registers() {
if (async_reset_ && i_nrst.read() == 0) {
r.src_priority = 0ull;
r.pending = 0ull;
r.src_priority = 0;
r.pending = 0;
r.ip = 0;
for (int i = 0; i < ctxmax; i++) {
r.ctx[i].priority_th = 0;
Expand All @@ -404,7 +404,7 @@ void plic<ctxmax, irqmax>::registers() {
r.ctx[i].irq_idx = 0;
r.ctx[i].irq_prio = 0;
}
r.rdata = 0ull;
r.rdata = 0;
} else {
r.src_priority = v.src_priority;
r.pending = v.pending;
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6 changes: 3 additions & 3 deletions sc/rtl/riverlib/cache/cache_top.cpp
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Expand Up @@ -374,9 +374,9 @@ void CacheTop::comb() {
sc_uint<RISCV_ARCH> vb_resp_ctrl_addr;
sc_uint<RISCV_ARCH> vb_resp_data_addr;

vb_ctrl_bus = 0ull;
vb_data_bus = 0ull;
vb_queue_bus = 0ull;
vb_ctrl_bus = 0;
vb_data_bus = 0;
vb_queue_bus = 0;
ctrl_path_id = CTRL_PATH;
data_path_id = DATA_PATH;
v_queue_we = 0;
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12 changes: 6 additions & 6 deletions sc/rtl/riverlib/cache/dcache_lru.h
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Original file line number Diff line number Diff line change
Expand Up @@ -143,15 +143,15 @@ SC_MODULE(DCacheLru) {

void DCacheLru_r_reset(DCacheLru_registers &iv) {
iv.req_type = 0;
iv.req_addr = 0ull;
iv.req_wdata = 0ull;
iv.req_addr = 0;
iv.req_wdata = 0;
iv.req_wstrb = 0;
iv.req_size = 0;
iv.state = State_Reset;
iv.req_mem_valid = 0;
iv.req_mem_type = 0;
iv.req_mem_size = 0;
iv.mem_addr = 0ull;
iv.mem_addr = 0;
iv.load_fault = 0;
iv.write_first = 0;
iv.write_flush = 0;
Expand All @@ -162,13 +162,13 @@ SC_MODULE(DCacheLru) {
iv.req_flush_addr = 0ull;
iv.req_flush_cnt = 0;
iv.flush_cnt = 0;
iv.cache_line_i = 0ull;
iv.cache_line_o = 0ull;
iv.cache_line_i = 0;
iv.cache_line_o = 0;
iv.req_snoop_type = 0;
iv.snoop_flags_valid = 0;
iv.snoop_restore_wait_resp = 0;
iv.snoop_restore_write_bus = 0;
iv.req_addr_restore = 0ull;
iv.req_addr_restore = 0;
}

sc_signal<bool> line_direct_access_i;
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10 changes: 5 additions & 5 deletions sc/rtl/riverlib/cache/icache_lru.h
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Original file line number Diff line number Diff line change
Expand Up @@ -108,12 +108,12 @@ SC_MODULE(ICacheLru) {
} v, r;

void ICacheLru_r_reset(ICacheLru_registers &iv) {
iv.req_addr = 0ull;
iv.req_addr_next = 0ull;
iv.write_addr = 0ull;
iv.req_addr = 0;
iv.req_addr_next = 0;
iv.write_addr = 0;
iv.state = State_Reset;
iv.req_mem_valid = 0;
iv.mem_addr = 0ull;
iv.mem_addr = 0;
iv.req_mem_type = 0;
iv.req_mem_size = 0;
iv.load_fault = 0;
Expand All @@ -122,7 +122,7 @@ SC_MODULE(ICacheLru) {
iv.req_flush_addr = 0ull;
iv.req_flush_cnt = 0;
iv.flush_cnt = 0;
iv.cache_line_i = 0ull;
iv.cache_line_i = 0;
}

sc_signal<bool> line_direct_access_i;
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8 changes: 4 additions & 4 deletions sc/rtl/riverlib/cache/pmp.cpp
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Expand Up @@ -142,8 +142,8 @@ void PMP::comb() {

if (!async_reset_ && i_nrst.read() == 0) {
for (int i = 0; i < CFG_PMP_TBL_SIZE; i++) {
v.tbl[i].start_addr = 0ull;
v.tbl[i].end_addr = 0ull;
v.tbl[i].start_addr = 0;
v.tbl[i].end_addr = 0;
v.tbl[i].flags = 0;
}
}
Expand All @@ -156,8 +156,8 @@ void PMP::comb() {
void PMP::registers() {
if (async_reset_ && i_nrst.read() == 0) {
for (int i = 0; i < CFG_PMP_TBL_SIZE; i++) {
r.tbl[i].start_addr = 0ull;
r.tbl[i].end_addr = 0ull;
r.tbl[i].start_addr = 0;
r.tbl[i].end_addr = 0;
r.tbl[i].flags = 0;
}
} else {
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2 changes: 1 addition & 1 deletion sc/rtl/riverlib/cache/tagmemcoupled.h
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Original file line number Diff line number Diff line change
Expand Up @@ -89,7 +89,7 @@ SC_MODULE(TagMemCoupled) {
} v, r;

void TagMemCoupled_r_reset(TagMemCoupled_registers &iv) {
iv.req_addr = 0ull;
iv.req_addr = 0;
}

tagmem_in_type linei[MemTotal];
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2 changes: 1 addition & 1 deletion sc/rtl/riverlib/cache/tagmemnway.h
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ SC_MODULE(TagMemNWay) {
} v, r;

void TagMemNWay_r_reset(TagMemNWay_registers &iv) {
iv.req_addr = 0ull;
iv.req_addr = 0;
iv.direct_access = 0;
iv.invalidate = 0;
iv.re = 0;
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2 changes: 1 addition & 1 deletion sc/rtl/riverlib/core/arith/alu_logic.h
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Expand Up @@ -47,7 +47,7 @@ SC_MODULE(AluLogic) {
} v, r;

void AluLogic_r_reset(AluLogic_registers &iv) {
iv.res = 0ull;
iv.res = 0;
}

};
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2 changes: 1 addition & 1 deletion sc/rtl/riverlib/core/arith/int_addsub.h
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Expand Up @@ -47,7 +47,7 @@ SC_MODULE(IntAddSub) {
} v, r;

void IntAddSub_r_reset(IntAddSub_registers &iv) {
iv.res = 0ull;
iv.res = 0;
}

};
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2 changes: 1 addition & 1 deletion sc/rtl/riverlib/core/arith/int_div.cpp
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Expand Up @@ -139,7 +139,7 @@ void IntDiv::comb() {
sc_uint<64> vb_div;
bool v_a1_m0; // a1 == -0ll
bool v_a2_m1; // a2 == -1ll
sc_uint<1> v_ena; // 1
sc_uint<1> v_ena;
sc_biguint<120> t_divisor;

v_invert64 = 0;
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12 changes: 6 additions & 6 deletions sc/rtl/riverlib/core/arith/int_div.h
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Expand Up @@ -73,13 +73,13 @@ SC_MODULE(IntDiv) {
iv.overflow = 0;
iv.busy = 0;
iv.ena = 0;
iv.divident_i = 0ull;
iv.divisor_i = 0ull;
iv.bits_i = 0ull;
iv.result = 0ull;
iv.reference_div = 0ull;
iv.divident_i = 0;
iv.divisor_i = 0;
iv.bits_i = 0;
iv.result = 0;
iv.reference_div = 0;
iv.a1_dbg = 0ull;
iv.a2_dbg = 0ull;
iv.a2_dbg = 0;
}

sc_signal<sc_biguint<124>> wb_divisor0_i;
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20 changes: 10 additions & 10 deletions sc/rtl/riverlib/core/arith/int_mul.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -291,16 +291,16 @@ void IntMul::comb() {
if (!async_reset_ && i_nrst.read() == 0) {
v.busy = 0;
v.ena = 0;
v.a1 = 0ull;
v.a2 = 0ull;
v.a1 = 0;
v.a2 = 0;
v.unsign = 0;
v.high = 0;
v.rv32 = 0;
v.zero = 0;
v.inv = 0;
v.result = 0ull;
v.a1_dbg = 0ull;
v.a2_dbg = 0ull;
v.result = 0;
v.a1_dbg = 0;
v.a2_dbg = 0;
v.reference_mul = 0ull;
for (int i = 0; i < 16; i++) {
v.lvl1[i] = 0ull;
Expand All @@ -318,16 +318,16 @@ void IntMul::registers() {
if (async_reset_ && i_nrst.read() == 0) {
r.busy = 0;
r.ena = 0;
r.a1 = 0ull;
r.a2 = 0ull;
r.a1 = 0;
r.a2 = 0;
r.unsign = 0;
r.high = 0;
r.rv32 = 0;
r.zero = 0;
r.inv = 0;
r.result = 0ull;
r.a1_dbg = 0ull;
r.a2_dbg = 0ull;
r.result = 0;
r.a1_dbg = 0;
r.a2_dbg = 0;
r.reference_mul = 0ull;
for (int i = 0; i < 16; i++) {
r.lvl1[i] = 0ull;
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2 changes: 1 addition & 1 deletion sc/rtl/riverlib/core/arith/shift.h
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ SC_MODULE(Shifter) {
} v, r;

void Shifter_r_reset(Shifter_registers &iv) {
iv.res = 0ull;
iv.res = 0;
}

};
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4 changes: 2 additions & 2 deletions sc/rtl/riverlib/core/bp_btb.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -149,7 +149,7 @@ void BpBTB::comb() {
if ((!async_reset_ && i_nrst.read() == 0) || i_flush_pipeline) {
for (int i = 0; i < CFG_BTB_SIZE; i++) {
v.btb[i].pc = ~0ull;
v.btb[i].npc = 0ull;
v.btb[i].npc = 0;
v.btb[i].exec = 0;
}
}
Expand All @@ -165,7 +165,7 @@ void BpBTB::registers() {
if (async_reset_ && i_nrst.read() == 0) {
for (int i = 0; i < CFG_BTB_SIZE; i++) {
r.btb[i].pc = ~0ull;
r.btb[i].npc = 0ull;
r.btb[i].npc = 0;
r.btb[i].exec = 0;
}
} else {
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