From 231ce173cc0f6f5734b23749fafdc4e41f268cd1 Mon Sep 17 00:00:00 2001
From: sergeykhbr <sergeykhbr@gmail.com>
Date: Sun, 10 Dec 2023 23:16:56 +0200
Subject: [PATCH] [*] minor changes: packages import order has been changed

---
 sv/rtl/riscv_soc.sv     | 2 +-
 sv/rtl/riscv_soc_pkg.sv | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/sv/rtl/riscv_soc.sv b/sv/rtl/riscv_soc.sv
index 725f600c..8e3aebcb 100644
--- a/sv/rtl/riscv_soc.sv
+++ b/sv/rtl/riscv_soc.sv
@@ -76,12 +76,12 @@ module riscv_soc #(
     input types_amba_pkg::axi4_slave_out_type i_ddr_xslvo   // AXI DDR memory interface
 );
 
-import target_cfg_pkg::*;
 import types_amba_pkg::*;
 import types_pnp_pkg::*;
 import types_bus0_pkg::*;
 import types_bus1_pkg::*;
 import river_cfg_pkg::*;
+import target_cfg_pkg::*;
 import riscv_soc_pkg::*;
 
 axi4_master_out_type acpo;
diff --git a/sv/rtl/riscv_soc_pkg.sv b/sv/rtl/riscv_soc_pkg.sv
index 18ad7628..756f7c91 100644
--- a/sv/rtl/riscv_soc_pkg.sv
+++ b/sv/rtl/riscv_soc_pkg.sv
@@ -20,6 +20,7 @@ import types_pnp_pkg::*;
 import types_bus0_pkg::*;
 import types_bus1_pkg::*;
 import river_cfg_pkg::*;
+import target_cfg_pkg::*;
 
 
 // Hardware SoC Identificator.