[*] update systemc with the latest rtlgen generated code: 0ull consta…

…nt is not used anymore
sergeykhbr · Dec 10, 2023 · 0a8ed6d · 0a8ed6d
1 parent f179595
commit 0a8ed6d
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Showing 13 changed files with 35 additions and 35 deletions.
diff --git a/sc/rtl/misclib/plic.h b/sc/rtl/misclib/plic.h
@@ -211,8 +211,8 @@ void plic<ctxmax, irqmax>::comb() {
     }
     for (int i = 0; i < ctxmax; i++) {
         vb_ctx[i].priority_th = 0;
-        vb_ctx[i].ie = 0ull;
-        vb_ctx[i].ip_prio = 0ull;
+        vb_ctx[i].ie = 0;
+        vb_ctx[i].ip_prio = 0;
         vb_ctx[i].prio_mask = 0;
         vb_ctx[i].sel_prio = 0;
         vb_ctx[i].irq_idx = 0;
@@ -380,8 +380,8 @@ void plic<ctxmax, irqmax>::comb() {
         v.ip = 0;
         for (int i = 0; i < ctxmax; i++) {
             v.ctx[i].priority_th = 0;
-            v.ctx[i].ie = 0ull;
-            v.ctx[i].ip_prio = 0ull;
+            v.ctx[i].ie = 0;
+            v.ctx[i].ip_prio = 0;
             v.ctx[i].prio_mask = 0;
             v.ctx[i].sel_prio = 0;
             v.ctx[i].irq_idx = 0;
@@ -405,8 +405,8 @@ void plic<ctxmax, irqmax>::registers() {
         r.ip = 0;
         for (int i = 0; i < ctxmax; i++) {
             r.ctx[i].priority_th = 0;
-            r.ctx[i].ie = 0ull;
-            r.ctx[i].ip_prio = 0ull;
+            r.ctx[i].ie = 0;
+            r.ctx[i].ip_prio = 0;
             r.ctx[i].prio_mask = 0;
             r.ctx[i].sel_prio = 0;
             r.ctx[i].irq_idx = 0;

diff --git a/sc/rtl/riverlib/cache/dcache_lru.cpp b/sc/rtl/riverlib/cache/dcache_lru.cpp
@@ -437,12 +437,12 @@ void DCacheLru::comb() {
     case State_TranslateAddress:
         if ((r.req_type.read()[MemopType_Store] == 1) && (i_pmp_w.read() == 0)) {
             v.load_fault = 1;
-            t_cache_line_i = 0ull;
+            t_cache_line_i = 0;
             v.cache_line_i = (~t_cache_line_i);
             v.state = State_CheckResp;
         } else if ((r.req_type.read()[MemopType_Store] == 0) && (i_pmp_r.read() == 0)) {
             v.load_fault = 1;
-            t_cache_line_i = 0ull;
+            t_cache_line_i = 0;
             v.cache_line_i = (~t_cache_line_i);
             v.state = State_CheckResp;
         } else {
@@ -482,12 +482,12 @@ void DCacheLru::comb() {
                 } else {
                     v.req_mem_type = ReadNoSnoop();
                 }
-                t_cache_line_i = 0ull;
+                t_cache_line_i = 0;
                 t_cache_line_i(63, 0) = r.req_wdata;
                 v.cache_line_o = t_cache_line_i;
             }
         }
-        v.cache_line_i = 0ull;
+        v.cache_line_i = 0;
         break;
     case State_WaitGrant:
         if (i_req_mem_ready.read() == 1) {
@@ -599,7 +599,7 @@ void DCacheLru::comb() {
         v_direct_access = r.req_flush_all;                  // 0=only if hit; 1=will be applied ignoring hit
         v_invalidate = 1;                                   // generate: wstrb='1; wflags='0
         v.write_flush = 0;
-        v.cache_line_i = 0ull;
+        v.cache_line_i = 0;
         break;
     case State_FlushCheck:
         v.cache_line_o = line_rdata_o;
@@ -702,7 +702,7 @@ void DCacheLru::comb() {
         } else if (r.req_flush.read() == 1) {
             v.state = State_FlushAddr;
             v.req_flush = 0;
-            v.cache_line_i = 0ull;
+            v.cache_line_i = 0;
             v.req_addr = (r.req_flush_addr.read() & (~LINE_BYTES_MASK));
             v.req_mem_size = CFG_LOG2_L1CACHE_BYTES_PER_LINE;
             v.flush_cnt = r.req_flush_cnt;

diff --git a/sc/rtl/riverlib/cache/icache_lru.cpp b/sc/rtl/riverlib/cache/icache_lru.cpp
@@ -261,7 +261,7 @@ void ICacheLru::comb() {
         break;
     case State_TranslateAddress:
         if (i_pmp_x.read() == 0) {
-            t_cache_line_i = 0ull;
+            t_cache_line_i = 0;
             v.cache_line_i = (~t_cache_line_i);
             v.state = State_CheckResp;
             v.load_fault = 1;
@@ -328,7 +328,7 @@ void ICacheLru::comb() {
         v.state = State_FlushCheck;
         v_direct_access = r.req_flush_all;                  // 0=only if hit; 1=will be applied ignoring hit
         v_invalidate = 1;                                   // generate: wstrb='1; wflags='0
-        v.cache_line_i = 0ull;
+        v.cache_line_i = 0;
         break;
     case State_FlushCheck:
         v.state = State_FlushAddr;
@@ -375,7 +375,7 @@ void ICacheLru::comb() {
         if (r.req_flush.read() == 1) {
             v.state = State_FlushAddr;
             v.req_flush = 0;
-            v.cache_line_i = 0ull;
+            v.cache_line_i = 0;
             v.req_addr = (r.req_flush_addr.read() & (~LINE_BYTES_MASK));
             v.flush_cnt = r.req_flush_cnt;
         } else {
@@ -409,7 +409,7 @@ void ICacheLru::comb() {
     o_req_mem_type = r.req_mem_type;
     o_req_mem_size = r.req_mem_size;
     o_req_mem_strob = 0;
-    o_req_mem_data = 0ull;
+    o_req_mem_data = 0;
 
     o_resp_valid = v_resp_valid;
     o_resp_data = vb_resp_data;

diff --git a/sc/rtl/riverlib/core/arith/int_mul.cpp b/sc/rtl/riverlib/core/arith/int_mul.cpp
@@ -272,7 +272,7 @@ void IntMul::comb() {
             v.result = wb_res32;
         } else if (r.high.read() == 1) {
             if (r.zero.read() == 1) {
-                v.result = 0ull;
+                v.result = 0;
             } else if (r.inv.read() == 1) {
                 v.result = (~wb_lvl5);
             } else {

diff --git a/sc/rtl/riverlib/core/execute.h b/sc/rtl/riverlib/core/execute.h
@@ -262,7 +262,7 @@ SC_MODULE(InstrExecute) {
         iv.isa_type = 0;
         iv.imm = 0;
         iv.instr = 0;
-        iv.tagcnt = 0ull;
+        iv.tagcnt = 0;
         iv.reg_write = 0;
         iv.reg_waddr = 0;
         iv.reg_wtag = 0;

diff --git a/sc/rtl/riverlib/core/fpu_d/fadd_d.cpp b/sc/rtl/riverlib/core/fpu_d/fadd_d.cpp
@@ -350,7 +350,7 @@ void DoubleAdd::comb() {
     mantLessScale = r.mantLess.read().to_uint64();
     mantLessScale = (mantLessScale << 52);
     if (r.ena.read()[1] == 1) {
-        v.mantLessScale = 0ull;
+        v.mantLessScale = 0;
         for (int i = 0; i < 105; i++) {
             if (i == r.preShift.read()) {
                 v.mantLessScale = (mantLessScale >> i);

diff --git a/sc/rtl/riverlib/core/fpu_d/imul53.cpp b/sc/rtl/riverlib/core/fpu_d/imul53.cpp
@@ -131,7 +131,7 @@ void imul53::comb() {
         v.b = (0, i_b.read());
         v.overflow = 0;
         v.accum_ena = 1;
-        v.sum = 0ull;
+        v.sum = 0;
         v.shift = 0;
     } else if (r.delay.read()[13] == 1) {
         v.accum_ena = 0;

diff --git a/sc/rtl/riverlib/core/mmu.cpp b/sc/rtl/riverlib/core/mmu.cpp
@@ -411,7 +411,7 @@ void Mmu::comb() {
         }
         if (r.req_flush.read() == 1) {
             v.req_flush = 0;
-            v.tlb_wdata = 0ull;
+            v.tlb_wdata = 0;
             v.state = FlushTlb;
         } else if ((i_mmu_ena.read() == 0) || (v_va_ena == 0)) {// MMU disabled
             // Direct connection to Cache

diff --git a/sc/rtl/riverlib/l2cache/l2cache_lru.cpp b/sc/rtl/riverlib/l2cache/l2cache_lru.cpp
@@ -407,7 +407,7 @@ void L2CacheLru::comb() {
             v.cache_line_o = t_cache_line_i;
         }
 
-        v.cache_line_i = 0ull;
+        v.cache_line_i = 0;
         v.rb_resp = 0;
         break;
     case State_WaitGrant:
@@ -490,7 +490,7 @@ void L2CacheLru::comb() {
         v_direct_access = r.req_flush_all;                  // 0=only if hit; 1=will be applied ignoring hit
         v_invalidate = 1;                                   // generate: wstrb='1; wflags='0
         v.write_flush = 0;
-        v.cache_line_i = 0ull;
+        v.cache_line_i = 0;
         break;
     case State_FlushCheck:
         v.cache_line_o = line_rdata_o;
@@ -552,7 +552,7 @@ void L2CacheLru::comb() {
         if (r.req_flush.read() == 1) {
             v.state = State_FlushAddr;
             v.req_flush = 0;
-            v.cache_line_i = 0ull;
+            v.cache_line_i = 0;
             v.req_addr = (r.req_flush_addr.read() & (!LINE_BYTES_MASK));
             v.req_size = CFG_L2_LOG2_BYTES_PER_LINE;
             v.flush_cnt = r.req_flush_cnt;

diff --git a/sc/rtl/riverlib/river_amba.cpp b/sc/rtl/riverlib/river_amba.cpp
@@ -297,7 +297,7 @@ void RiverAmba::comb() {
             v.req_prot = (req_mem_path_o.read() << 2);
             if (req_mem_type_o.read()[REQ_MEM_TYPE_WRITE] == 0) {
                 v.state = state_ar;
-                v.req_wdata = 0ull;
+                v.req_wdata = 0;
                 v.req_wstrb = 0;
                 if (req_mem_type_o.read()[REQ_MEM_TYPE_CACHED] == 1) {
                     v.req_cached = ARCACHE_WRBACK_READ_ALLOCATE;

diff --git a/sc/rtl/riverlib/river_amba.h b/sc/rtl/riverlib/river_amba.h
@@ -97,8 +97,8 @@ SC_MODULE(RiverAmba) {
     } v, r;
 
     void RiverAmba_r_reset(RiverAmba_registers &iv) {
-        iv.state = 0;
-        iv.req_addr = state_idle;
+        iv.state = state_idle;
+        iv.req_addr = 0;
         iv.req_path = 0;
         iv.req_cached = 0;
         iv.req_wdata = 0;

diff --git a/sc/rtl/riverlib/types_river.h b/sc/rtl/riverlib/types_river.h
@@ -225,7 +225,7 @@ class axi4_l1_out_type {
         aw_id = 0;
         aw_user = 0;
         w_valid = 0;
-        w_data = 0ull;
+        w_data = 0;
         w_last = 0;
         w_strb = 0;
         w_user = 0;
@@ -254,7 +254,7 @@ class axi4_l1_out_type {
         cr_valid = 1;
         cr_resp = 0;
         cd_valid = 0;
-        cd_data = 0ull;
+        cd_data = 0;
         cd_last = 0;
         rack = 0;
         wack = 0;
@@ -568,7 +568,7 @@ class axi4_l1_in_type {
         ar_ready = 0;
         r_valid = 0;
         r_resp = 0;
-        r_data = 0ull;
+        r_data = 0;
         r_last = 0;
         r_id = 0;
         r_user = 0;
@@ -760,7 +760,7 @@ class axi4_l2_out_type {
         aw_id = 0;
         aw_user = 0;
         w_valid = 0;
-        w_data = 0ull;
+        w_data = 0;
         w_last = 0;
         w_strb = 0;
         w_user = 0;
@@ -989,7 +989,7 @@ class axi4_l2_in_type {
         ar_ready = 0;
         r_valid = 0;
         r_resp = 0;
-        r_data = 0ull;
+        r_data = 0;
         r_last = 0;
         r_id = 0;
         r_user = 0;

diff --git a/sc/rtl/sdctrl/sdctrl_cache.cpp b/sc/rtl/sdctrl/sdctrl_cache.cpp
@@ -248,7 +248,7 @@ void sdctrl_cache::comb() {
         v.mem_fault = 0;
         if (r.req_flush.read() == 1) {
             v.state = State_FlushAddr;
-            v.cache_line_i = 0ull;
+            v.cache_line_i = 0;
             v.flush_cnt = FLUSH_ALL_VALUE;
         } else {
             v_req_ready = 1;
@@ -309,7 +309,7 @@ void sdctrl_cache::comb() {
             v.req_mem_write = r.req_write;
         }
         v.cache_line_o = line_rdata_o;
-        v.cache_line_i = 0ull;
+        v.cache_line_i = 0;
         break;
     case State_WaitGrant:
         if (i_req_mem_ready.read() == 1) {
@@ -378,7 +378,7 @@ void sdctrl_cache::comb() {
         vb_line_wstrb = ~0ull;
         vb_line_wflags = 0;
         v.write_flush = 0;
-        v.cache_line_i = 0ull;
+        v.cache_line_i = 0;
         break;
     case State_FlushCheck:
         v.cache_line_o = line_rdata_o;