diff --git a/sv/rtl/misclib/apb_prci.sv b/sv/rtl/misclib/apb_prci.sv
index 4502840e..c1c7a91f 100644
--- a/sv/rtl/misclib/apb_prci.sv
+++ b/sv/rtl/misclib/apb_prci.sv
@@ -42,7 +42,7 @@ logic w_req_valid;
 logic [31:0] wb_req_addr;
 logic w_req_write;
 logic [31:0] wb_req_wdata;
-apb_prci_registers r, rin;
+apb_prci_rhegisters rh, rhin;
 
 apb_slv #(
     .async_reset(async_reset),
@@ -50,7 +50,7 @@ apb_slv #(
     .did(OPTIMITECH_PRCI)
 ) pslv0 (
     .i_clk(i_clk),
-    .i_nrst(r.sys_nrst),
+    .i_nrst(rh.sys_nrst),
     .i_mapinfo(i_mapinfo),
     .o_cfg(o_cfg),
     .i_apbi(i_apbi),
@@ -59,9 +59,9 @@ apb_slv #(
     .o_req_addr(wb_req_addr),
     .o_req_write(w_req_write),
     .o_req_wdata(wb_req_wdata),
-    .i_resp_valid(r.resp_valid),
-    .i_resp_rdata(r.resp_rdata),
-    .i_resp_err(r.resp_err)
+    .i_resp_valid(rh.resp_valid),
+    .i_resp_rdata(rh.resp_rdata),
+    .i_resp_err(rh.resp_err)
 );
 
 always_comb
@@ -71,11 +71,11 @@ begin: comb_proc
 
     vb_rdata = '0;
 
-    v = r;
+    vh = rh;
 
-    v.sys_rst = (i_pwrreset || (~i_sys_locked) || i_dmireset);
-    v.sys_nrst = (~(i_pwrreset || (~i_sys_locked) || i_dmireset));
-    v.dbg_nrst = (~(i_pwrreset || (~i_sys_locked)));
+    vh.sys_rst = (i_pwrreset || (~i_sys_locked) || i_dmireset);
+    vh.sys_nrst = (~(i_pwrreset || (~i_sys_locked) || i_dmireset));
+    vh.dbg_nrst = (~(i_pwrreset || (~i_sys_locked)));
 
     // Registers access:
     case (wb_req_addr[11: 2])
@@ -84,8 +84,8 @@ begin: comb_proc
         vb_rdata[1] = i_ddr_locked;
     end
     10'd1: begin                                            // 0x04: reset status
-        vb_rdata[0] = r.sys_nrst;
-        vb_rdata[1] = r.dbg_nrst;
+        vb_rdata[0] = rh.sys_nrst;
+        vb_rdata[1] = rh.dbg_nrst;
         if (w_req_valid == 1'b1) begin
             if (w_req_write == 1'b1) begin
                 // todo:
@@ -96,39 +96,39 @@ begin: comb_proc
     end
     endcase
 
-    v.resp_valid = w_req_valid;
-    v.resp_rdata = vb_rdata;
-    v.resp_err = 1'b0;
+    vh.resp_valid = w_req_valid;
+    vh.resp_rdata = vb_rdata;
+    vh.resp_err = 1'b0;
 
     if (~async_reset && i_pwrreset == 1'b1) begin
-        v = apb_prci_r_reset;
+        vh = apb_prci_rh_reset;
     end
 
-    o_sys_rst = r.sys_rst;
-    o_sys_nrst = r.sys_nrst;
-    o_dbg_nrst = r.dbg_nrst;
+    o_sys_rst = rh.sys_rst;
+    o_sys_nrst = rh.sys_nrst;
+    o_dbg_nrst = rh.dbg_nrst;
 
-    rin = v;
+    rhin = vh;
 end: comb_proc
 
 
 generate
     if (async_reset) begin: async_rst_gen
 
-        always_ff @(posedge i_clk, posedge i_pwrreset) begin: rg_proc
+        always_ff @(posedge i_clk, posedge i_pwrreset) begin: rhg_proc
             if (i_pwrreset == 1'b1) begin
-                r <= apb_prci_r_reset;
+                rh <= apb_prci_rh_reset;
             end else begin
-                r <= rin;
+                rh <= rhin;
             end
-        end: rg_proc
+        end: rhg_proc
 
     end: async_rst_gen
     else begin: no_rst_gen
 
-        always_ff @(posedge i_clk) begin: rg_proc
-            r <= rin;
-        end: rg_proc
+        always_ff @(posedge i_clk) begin: rhg_proc
+            rh <= rhin;
+        end: rhg_proc
 
     end: no_rst_gen
 endgenerate
diff --git a/sv/rtl/misclib/apb_prci_pkg.sv b/sv/rtl/misclib/apb_prci_pkg.sv
index da5882e5..31560b37 100644
--- a/sv/rtl/misclib/apb_prci_pkg.sv
+++ b/sv/rtl/misclib/apb_prci_pkg.sv
@@ -27,9 +27,9 @@ typedef struct {
     logic resp_valid;
     logic [31:0] resp_rdata;
     logic resp_err;
-} apb_prci_registers;
+} apb_prci_rhegisters;
 
-const apb_prci_registers apb_prci_r_reset = '{
+const apb_prci_rhegisters apb_prci_rh_reset = '{
     1'b0,                               // sys_rst
     1'b0,                               // sys_nrst
     1'b0,                               // dbg_nrst
diff --git a/sv/rtl/misclib/apb_uart.sv b/sv/rtl/misclib/apb_uart.sv
index 87db02ce..524bc29c 100644
--- a/sv/rtl/misclib/apb_uart.sv
+++ b/sv/rtl/misclib/apb_uart.sv
@@ -470,7 +470,7 @@ begin: comb_proc
         v.err_stopbit = 1'b0;
         v.fwcpuid = '0;
         for (int i = 0; i < fifosz; i++) begin
-            v.rx_fifo[i] = '0;
+            v.rx_fifo[i] = 8'd0;
         end
         v.rx_state = idle;
         v.rx_ena = 1'b0;
@@ -486,7 +486,7 @@ begin: comb_proc
         v.rx_stop_cnt = 1'b0;
         v.rx_shift = '0;
         for (int i = 0; i < fifosz; i++) begin
-            v.tx_fifo[i] = '0;
+            v.tx_fifo[i] = 8'd0;
         end
         v.tx_state = idle;
         v.tx_ena = 1'b0;
@@ -567,7 +567,7 @@ generate
                 r.err_stopbit <= 1'b0;
                 r.fwcpuid <= '0;
                 for (int i = 0; i < fifosz; i++) begin
-                    r.rx_fifo[i] <= '0;
+                    r.rx_fifo[i] <= 8'd0;
                 end
                 r.rx_state <= idle;
                 r.rx_ena <= 1'b0;
@@ -583,7 +583,7 @@ generate
                 r.rx_stop_cnt <= 1'b0;
                 r.rx_shift <= '0;
                 for (int i = 0; i < fifosz; i++) begin
-                    r.tx_fifo[i] <= '0;
+                    r.tx_fifo[i] <= 8'd0;
                 end
                 r.tx_state <= idle;
                 r.tx_ena <= 1'b0;
diff --git a/sv/rtl/misclib/plic.sv b/sv/rtl/misclib/plic.sv
index 7aed62b0..49dfcb33 100644
--- a/sv/rtl/misclib/plic.sv
+++ b/sv/rtl/misclib/plic.sv
@@ -96,7 +96,13 @@ begin: comb_proc
     logic [CFG_SYSBUS_DATA_BITS-1:0] vrdata;
     logic [9:0] vb_irq_idx[0: ctxmax-1];                    // Currently selected most prio irq
     logic [9:0] vb_irq_prio[0: ctxmax-1];                   // Currently selected prio level
-    plic_context_type vb_ctx[0: ctxmax-1];
+    logic [3:0] vb_ctx_priority_th[0: ctxmax-1];
+    logic [1023:0] vb_ctx_ie[0: ctxmax-1];
+    logic [(4 * 1024)-1:0] vb_ctx_ip_prio[0: ctxmax-1];
+    logic [15:0] vb_ctx_prio_mask[0: ctxmax-1];
+    logic [3:0] vb_ctx_sel_prio[0: ctxmax-1];
+    logic [9:0] vb_ctx_irq_idx[0: ctxmax-1];
+    logic [9:0] vb_ctx_irq_prio[0: ctxmax-1];
     logic [(4 * 1024)-1:0] vb_src_priority;
     logic [1023:0] vb_pending;
     logic [ctxmax-1:0] vb_ip;
@@ -110,13 +116,25 @@ begin: comb_proc
         vb_irq_prio[i] = '0;
     end
     for (int i = 0; i < ctxmax; i++) begin
-        vb_ctx[i].priority_th = 4'd0;
-        vb_ctx[i].ie = '0;
-        vb_ctx[i].ip_prio = '0;
-        vb_ctx[i].prio_mask = 16'd0;
-        vb_ctx[i].sel_prio = 4'd0;
-        vb_ctx[i].irq_idx = 10'd0;
-        vb_ctx[i].irq_prio = 10'd0;
+        vb_ctx_priority_th[i] = 4'd0;
+    end
+    for (int i = 0; i < ctxmax; i++) begin
+        vb_ctx_ie[i] = '0;
+    end
+    for (int i = 0; i < ctxmax; i++) begin
+        vb_ctx_ip_prio[i] = '0;
+    end
+    for (int i = 0; i < ctxmax; i++) begin
+        vb_ctx_prio_mask[i] = 16'd0;
+    end
+    for (int i = 0; i < ctxmax; i++) begin
+        vb_ctx_sel_prio[i] = 4'd0;
+    end
+    for (int i = 0; i < ctxmax; i++) begin
+        vb_ctx_irq_idx[i] = 10'd0;
+    end
+    for (int i = 0; i < ctxmax; i++) begin
+        vb_ctx_irq_prio[i] = 10'd0;
     end
     vb_src_priority = '0;
     vb_pending = '0;
@@ -143,10 +161,10 @@ begin: comb_proc
     vb_src_priority = r.src_priority;
     vb_pending = r.pending;
     for (int i = 0; i < ctxmax; i++) begin
-        vb_ctx[i].priority_th = r.ctx[i].priority_th;
-        vb_ctx[i].ie = r.ctx[i].ie;
-        vb_ctx[i].irq_idx = r.ctx[i].irq_idx;
-        vb_ctx[i].irq_prio = r.ctx[i].irq_prio;
+        vb_ctx_priority_th[i] = r.ctx[i].priority_th;
+        vb_ctx_ie[i] = r.ctx[i].ie;
+        vb_ctx_irq_idx[i] = r.ctx[i].irq_idx;
+        vb_ctx_irq_prio[i] = r.ctx[i].irq_prio;
     end
 
     for (int i = 1; i < irqmax; i++) begin
@@ -160,8 +178,8 @@ begin: comb_proc
             if ((r.pending[i] == 1'b1)
                     && (r.ctx[n].ie[i] == 1'b1)
                     && (int'(r.src_priority[(4 * i) +: 4]) > r.ctx[n].priority_th)) begin
-                vb_ctx[n].ip_prio[(4 * i) +: 4] = r.src_priority[(4 * i) +: 4];
-                vb_ctx[n].prio_mask[int'(r.src_priority[(4 * i) +: 4])] = 1'b1;
+                vb_ctx_ip_prio[n][(4 * i) +: 4] = r.src_priority[(4 * i) +: 4];
+                vb_ctx_prio_mask[n][int'(r.src_priority[(4 * i) +: 4])] = 1'b1;
             end
         end
     end
@@ -170,7 +188,7 @@ begin: comb_proc
     for (int n = 0; n < ctxmax; n++) begin
         for (int i = 0; i < 16; i++) begin
             if (r.ctx[n].prio_mask[i] == 1'b1) begin
-                vb_ctx[n].sel_prio = i;
+                vb_ctx_sel_prio[n] = i;
             end
         end
     end
@@ -188,8 +206,8 @@ begin: comb_proc
     end
 
     for (int n = 0; n < ctxmax; n++) begin
-        vb_ctx[n].irq_idx = vb_irq_idx[n];
-        vb_ctx[n].irq_prio = vb_irq_prio[n];
+        vb_ctx_irq_idx[n] = vb_irq_idx[n];
+        vb_ctx_irq_prio[n] = vb_irq_prio[n];
         vb_ip[n] = (|vb_irq_idx[n]);
     end
 
@@ -230,10 +248,10 @@ begin: comb_proc
         vrdata = r.ctx[wb_req_addr[11: 7]].ie[(64 * wb_req_addr[6: 3]) +: 64];
         if ((w_req_valid == 1'b1) && (w_req_write == 1'b1)) begin
             if ((|wb_req_wstrb[3: 0]) == 1'b1) begin
-                vb_ctx[wb_req_addr[11: 7]].ie[(64 * wb_req_addr[6: 3]) +: 32] = wb_req_wdata[31: 0];
+                vb_ctx_ie[wb_req_addr[11: 7]][(64 * wb_req_addr[6: 3]) +: 32] = wb_req_wdata[31: 0];
             end
             if ((|wb_req_wstrb[7: 4]) == 1'b1) begin
-                vb_ctx[wb_req_addr[11: 7]].ie[((64 * wb_req_addr[6: 3]) + 32) +: 32] = wb_req_wdata[63: 32];
+                vb_ctx_ie[wb_req_addr[11: 7]][((64 * wb_req_addr[6: 3]) + 32) +: 32] = wb_req_wdata[63: 32];
             end
         end
     end else if ((wb_req_addr[21: 12] >= 10'h200) && (wb_req_addr[20: 12] < ctxmax)) begin
@@ -248,11 +266,11 @@ begin: comb_proc
             end
             if ((w_req_valid == 1'b1) && (w_req_write == 1'b1)) begin
                 if ((|wb_req_wstrb[3: 0]) == 1'b1) begin
-                    vb_ctx[rctx_idx].priority_th = wb_req_wdata[3: 0];
+                    vb_ctx_priority_th[rctx_idx] = wb_req_wdata[3: 0];
                 end
                 if ((|wb_req_wstrb[7: 4]) == 1'b1) begin
                     // claim/ complete. Reading clears pedning bit
-                    vb_ctx[rctx_idx].irq_idx = '0;
+                    vb_ctx_irq_idx[rctx_idx] = '0;
                 end
             end
         end else begin
@@ -265,13 +283,13 @@ begin: comb_proc
     v.pending = vb_pending;
     v.ip = vb_ip;
     for (int n = 0; n < ctxmax; n++) begin
-        v.ctx[n].priority_th = vb_ctx[n].priority_th;
-        v.ctx[n].ie = vb_ctx[n].ie;
-        v.ctx[n].ip_prio = vb_ctx[n].ip_prio;
-        v.ctx[n].prio_mask = vb_ctx[n].prio_mask;
-        v.ctx[n].sel_prio = vb_ctx[n].sel_prio;
-        v.ctx[n].irq_idx = vb_ctx[n].irq_idx;
-        v.ctx[n].irq_prio = vb_ctx[n].irq_prio;
+        v.ctx[n].priority_th = vb_ctx_priority_th[n];
+        v.ctx[n].ie = vb_ctx_ie[n];
+        v.ctx[n].ip_prio = vb_ctx_ip_prio[n];
+        v.ctx[n].prio_mask = vb_ctx_prio_mask[n];
+        v.ctx[n].sel_prio = vb_ctx_sel_prio[n];
+        v.ctx[n].irq_idx = vb_ctx_irq_idx[n];
+        v.ctx[n].irq_prio = vb_ctx_irq_prio[n];
     end
 
     if (~async_reset && i_nrst == 1'b0) begin
diff --git a/sv/rtl/riverlib/cache/lrunway.sv b/sv/rtl/riverlib/cache/lrunway.sv
index c3fb5c00..ab034a86 100644
--- a/sv/rtl/riverlib/cache/lrunway.sv
+++ b/sv/rtl/riverlib/cache/lrunway.sv
@@ -39,9 +39,9 @@ localparam int LINE_WIDTH = (WAYS_TOTAL * waybits);
 typedef struct {
     logic [abits-1:0] radr;
     logic [LINE_WIDTH-1:0] mem[0: LINES_TOTAL - 1];
-} lrunway_registers;
+} lrunway_rxegisters;
 
-lrunway_registers r, rin;
+lrunway_rxegisters rx, rxin;
 
 
 always_comb
@@ -67,13 +67,13 @@ begin: comb_proc
     shift_ena_up = 1'b0;
     shift_ena_down = 1'b0;
 
-    v.radr = r.radr;
+    vx.radr = rx.radr;
     for (int i = 0; i < LINES_TOTAL; i++) begin
-        v.mem[i] = r.mem[i];
+        vx.mem[i] = rx.mem[i];
     end
 
-    v.radr = i_raddr;
-    wb_tbl_rdata = r.mem[int'(r.radr)];
+    vx.radr = i_raddr;
+    wb_tbl_rdata = rx.mem[int'(rx.radr)];
 
     v_we = (i_up || i_down || i_init);
 
@@ -125,21 +125,21 @@ begin: comb_proc
     end
 
     if (v_we == 1'b1) begin
-        v.mem[int'(i_waddr)] = vb_tbl_wdata;
+        vx.mem[int'(i_waddr)] = vb_tbl_wdata;
     end
     o_lru = wb_tbl_rdata[(waybits - 1): 0];
 
-    rin.radr = v.radr;
+    rxin.radr = vx.radr;
     for (int i = 0; i < LINES_TOTAL; i++) begin
-        rin.mem[i] = v.mem[i];
+        rxin.mem[i] = vx.mem[i];
     end
 end: comb_proc
 
-
-always_ff @(posedge i_clk) begin: rg_proc
-    r.radr <= rin.radr;
+always_ff @(posedge i_clk) begin: rxg_proc
+    rx.radr <= rxin.radr;
     for (int i = 0; i < LINES_TOTAL; i++) begin
-        r.mem[i] <= rin.mem[i];
+        rx.mem[i] <= rxin.mem[i];
     end
-end: rg_proc
+end: rxg_proc
+
 endmodule: lrunway
diff --git a/sv/rtl/riverlib/cache/pmp.sv b/sv/rtl/riverlib/cache/pmp.sv
index a5e414f5..8b6536f9 100644
--- a/sv/rtl/riverlib/cache/pmp.sv
+++ b/sv/rtl/riverlib/cache/pmp.sv
@@ -105,8 +105,8 @@ begin: comb_proc
 
     if (~async_reset && i_nrst == 1'b0) begin
         for (int i = 0; i < CFG_PMP_TBL_SIZE; i++) begin
-            v.tbl[i].start_addr = '0;
-            v.tbl[i].end_addr = '0;
+            v.tbl[i].start_addr = 64'd0;
+            v.tbl[i].end_addr = 64'd0;
             v.tbl[i].flags = 5'd0;
         end
     end
@@ -129,8 +129,8 @@ generate
         always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
             if (i_nrst == 1'b0) begin
                 for (int i = 0; i < CFG_PMP_TBL_SIZE; i++) begin
-                    r.tbl[i].start_addr <= '0;
-                    r.tbl[i].end_addr <= '0;
+                    r.tbl[i].start_addr <= 64'd0;
+                    r.tbl[i].end_addr <= 64'd0;
                     r.tbl[i].flags <= 5'd0;
                 end
             end else begin
diff --git a/sv/rtl/riverlib/core/bp_btb.sv b/sv/rtl/riverlib/core/bp_btb.sv
index eb6d8432..6987cb43 100644
--- a/sv/rtl/riverlib/core/bp_btb.sv
+++ b/sv/rtl/riverlib/core/bp_btb.sv
@@ -109,7 +109,7 @@ begin: comb_proc
     if ((~async_reset && i_nrst == 1'b0) || i_flush_pipeline) begin
         for (int i = 0; i < CFG_BTB_SIZE; i++) begin
             v.btb[i].pc = '1;
-            v.btb[i].npc = '0;
+            v.btb[i].npc = 64'd0;
             v.btb[i].exec = 1'b0;
         end
     end
@@ -135,7 +135,7 @@ generate
             if (i_nrst == 1'b0) begin
                 for (int i = 0; i < CFG_BTB_SIZE; i++) begin
                     r.btb[i].pc <= '1;
-                    r.btb[i].npc <= '0;
+                    r.btb[i].npc <= 64'd0;
                     r.btb[i].exec <= 1'b0;
                 end
             end else begin
diff --git a/sv/rtl/riverlib/core/decoder.sv b/sv/rtl/riverlib/core/decoder.sv
index 3a721806..30a8190d 100644
--- a/sv/rtl/riverlib/core/decoder.sv
+++ b/sv/rtl/riverlib/core/decoder.sv
@@ -209,7 +209,7 @@ begin: comb_proc
     if ((~async_reset && i_nrst == 1'b0) || (i_flush_pipeline == 1'b1)) begin
         for (int i = 0; i < FULL_DEC_DEPTH; i++) begin
             v.d[i].pc = '1;
-            v.d[i].isa_type = '0;
+            v.d[i].isa_type = 6'd0;
             v.d[i].instr_vec = '0;
             v.d[i].instr = '1;
             v.d[i].memop_store = 1'b0;
@@ -224,11 +224,11 @@ begin: comb_proc
             v.d[i].instr_load_fault = 1'b0;
             v.d[i].instr_page_fault_x = 1'b0;
             v.d[i].instr_unimplemented = 1'b0;
-            v.d[i].radr1 = '0;
-            v.d[i].radr2 = '0;
-            v.d[i].waddr = '0;
-            v.d[i].csr_addr = '0;
-            v.d[i].imm = '0;
+            v.d[i].radr1 = 6'd0;
+            v.d[i].radr2 = 6'd0;
+            v.d[i].waddr = 6'd0;
+            v.d[i].csr_addr = 12'd0;
+            v.d[i].imm = 64'd0;
             v.d[i].progbuf_ena = 1'b0;
         end
     end
@@ -290,7 +290,7 @@ generate
             if (i_nrst == 1'b0) begin
                 for (int i = 0; i < FULL_DEC_DEPTH; i++) begin
                     r.d[i].pc <= '1;
-                    r.d[i].isa_type <= '0;
+                    r.d[i].isa_type <= 6'd0;
                     r.d[i].instr_vec <= '0;
                     r.d[i].instr <= '1;
                     r.d[i].memop_store <= 1'b0;
@@ -305,11 +305,11 @@ generate
                     r.d[i].instr_load_fault <= 1'b0;
                     r.d[i].instr_page_fault_x <= 1'b0;
                     r.d[i].instr_unimplemented <= 1'b0;
-                    r.d[i].radr1 <= '0;
-                    r.d[i].radr2 <= '0;
-                    r.d[i].waddr <= '0;
-                    r.d[i].csr_addr <= '0;
-                    r.d[i].imm <= '0;
+                    r.d[i].radr1 <= 6'd0;
+                    r.d[i].radr2 <= 6'd0;
+                    r.d[i].waddr <= 6'd0;
+                    r.d[i].csr_addr <= 12'd0;
+                    r.d[i].imm <= 64'd0;
                     r.d[i].progbuf_ena <= 1'b0;
                 end
             end else begin
diff --git a/sv/rtl/riverlib/core/queue.sv b/sv/rtl/riverlib/core/queue.sv
index 12bfd953..183809d4 100644
--- a/sv/rtl/riverlib/core/queue.sv
+++ b/sv/rtl/riverlib/core/queue.sv
@@ -36,10 +36,18 @@ localparam int DEPTH = (2**abits);
 
 typedef struct {
     logic [(abits + 1)-1:0] wcnt;
-    logic [dbits-1:0] mem[0: DEPTH - 1];
 } Queue_registers;
 
+const Queue_registers Queue_r_reset = '{
+    7'd0                                // wcnt
+};
+
+typedef struct {
+    logic [dbits-1:0] mem[0: DEPTH - 1];
+} Queue_rxegisters;
+
 Queue_registers r, rin;
+Queue_rxegisters rx, rxin;
 
 
 always_comb
@@ -55,9 +63,9 @@ begin: comb_proc
     full = 1'b0;
     show_full = 1'b0;
 
-    v.wcnt = r.wcnt;
+    v = r;
     for (int i = 0; i < DEPTH; i++) begin
-        v.mem[i] = r.mem[i];
+        vx.mem[i] = rx.mem[i];
     end
 
     if (r.wcnt == DEPTH) begin
@@ -69,31 +77,31 @@ begin: comb_proc
 
     if ((i_re == 1'b1) && (i_we == 1'b1)) begin
         for (int i = 1; i < DEPTH; i++) begin
-            v.mem[(i - 1)] = r.mem[i];
+            vx.mem[(i - 1)] = rx.mem[i];
         end
         if ((|r.wcnt) == 1'b1) begin
-            v.mem[(int'(r.wcnt) - 1)] = i_wdata;
+            vx.mem[(int'(r.wcnt) - 1)] = i_wdata;
         end else begin
             // do nothing, it will directly pass to output
         end
     end else if ((i_re == 1'b0) && (i_we == 1'b1)) begin
         if (full == 1'b0) begin
             v.wcnt = (r.wcnt + 1);
-            v.mem[int'(r.wcnt)] = i_wdata;
+            vx.mem[int'(r.wcnt)] = i_wdata;
         end
     end else if ((i_re == 1'b1) && (i_we == 1'b0)) begin
         if ((|r.wcnt) == 1'b1) begin
             v.wcnt = (r.wcnt - 1);
         end
         for (int i = 1; i < DEPTH; i++) begin
-            v.mem[(i - 1)] = r.mem[i];
+            vx.mem[(i - 1)] = rx.mem[i];
         end
     end
 
     if ((|r.wcnt) == 1'b0) begin
         vb_data_o = i_wdata;
     end else begin
-        vb_data_o = r.mem[0];
+        vb_data_o = rx.mem[0];
     end
 
     if ((i_we == 1'b1) || ((|r.wcnt) == 1'b1)) begin
@@ -101,16 +109,16 @@ begin: comb_proc
     end
 
     if (~async_reset && i_nrst == 1'b0) begin
-        v.wcnt = 7'd0;
+        v = Queue_r_reset;
     end
 
     o_nempty = nempty;
     o_full = show_full;
     o_rdata = vb_data_o;
 
-    rin.wcnt = v.wcnt;
+    rin = v;
     for (int i = 0; i < DEPTH; i++) begin
-        rin.mem[i] = v.mem[i];
+        rxin.mem[i] = vx.mem[i];
     end
 end: comb_proc
 
@@ -120,24 +128,30 @@ generate
 
         always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
             if (i_nrst == 1'b0) begin
-                r.wcnt <= 7'd0;
+                r <= Queue_r_reset;
             end else begin
-                r.wcnt <= rin.wcnt;
-                for (int i = 0; i < DEPTH; i++) begin
-                    r.mem[i] <= rin.mem[i];
-                end
+                r <= rin;
             end
         end: rg_proc
 
+        always_ff @(posedge i_clk) begin: rxg_proc
+            for (int i = 0; i < DEPTH; i++) begin
+                rx.mem[i] <= rxin.mem[i];
+            end
+        end: rxg_proc
+
     end: async_rst_gen
     else begin: no_rst_gen
 
         always_ff @(posedge i_clk) begin: rg_proc
-            r.wcnt <= rin.wcnt;
+            r <= rin;
+        end: rg_proc
+
+        always_ff @(posedge i_clk) begin: rxg_proc
             for (int i = 0; i < DEPTH; i++) begin
-                r.mem[i] <= rin.mem[i];
+                rx.mem[i] <= rxin.mem[i];
             end
-        end: rg_proc
+        end: rxg_proc
 
     end: no_rst_gen
 endgenerate
diff --git a/sv/rtl/riverlib/core/stacktrbuf.sv b/sv/rtl/riverlib/core/stacktrbuf.sv
index e71f6005..8bd7c088 100644
--- a/sv/rtl/riverlib/core/stacktrbuf.sv
+++ b/sv/rtl/riverlib/core/stacktrbuf.sv
@@ -28,35 +28,35 @@ module StackTraceBuffer(
 import river_cfg_pkg::*;
 import stacktrbuf_pkg::*;
 
-StackTraceBuffer_registers r, rin;
+StackTraceBuffer_rxegisters rx, rxin;
 
 
 always_comb
 begin: comb_proc
     StackTraceBuffer_registers v;
-    v.raddr = r.raddr;
+    vx.raddr = rx.raddr;
     for (int i = 0; i < STACK_TRACE_BUF_SIZE; i++) begin
-        v.stackbuf[i] = r.stackbuf[i];
+        vx.stackbuf[i] = rx.stackbuf[i];
     end
 
-    v.raddr = i_raddr;
+    vx.raddr = i_raddr;
     if (i_we == 1'b1) begin
-        v.stackbuf[int'(i_waddr)] = i_wdata;
+        vx.stackbuf[int'(i_waddr)] = i_wdata;
     end
 
-    o_rdata = r.stackbuf[int'(r.raddr)];
+    o_rdata = rx.stackbuf[int'(rx.raddr)];
 
-    rin.raddr = v.raddr;
+    rxin.raddr = vx.raddr;
     for (int i = 0; i < STACK_TRACE_BUF_SIZE; i++) begin
-        rin.stackbuf[i] = v.stackbuf[i];
+        rxin.stackbuf[i] = vx.stackbuf[i];
     end
 end: comb_proc
 
-
-always_ff @(posedge i_clk) begin: rg_proc
-    r.raddr <= rin.raddr;
+always_ff @(posedge i_clk) begin: rxg_proc
+    rx.raddr <= rxin.raddr;
     for (int i = 0; i < STACK_TRACE_BUF_SIZE; i++) begin
-        r.stackbuf[i] <= rin.stackbuf[i];
+        rx.stackbuf[i] <= rxin.stackbuf[i];
     end
-end: rg_proc
+end: rxg_proc
+
 endmodule: StackTraceBuffer
diff --git a/sv/rtl/riverlib/core/stacktrbuf_pkg.sv b/sv/rtl/riverlib/core/stacktrbuf_pkg.sv
index 6f6f3d85..f5b1293c 100644
--- a/sv/rtl/riverlib/core/stacktrbuf_pkg.sv
+++ b/sv/rtl/riverlib/core/stacktrbuf_pkg.sv
@@ -20,6 +20,6 @@ import river_cfg_pkg::*;
 typedef struct {
     logic [4:0] raddr;
     logic [(2 * RISCV_ARCH)-1:0] stackbuf[0: STACK_TRACE_BUF_SIZE - 1];
-} StackTraceBuffer_registers;
+} StackTraceBuffer_rxegisters;
 
 endpackage: stacktrbuf_pkg
diff --git a/sv/rtl/riverlib/core/tracer.sv b/sv/rtl/riverlib/core/tracer.sv
index 1aab3b9e..1518bd8f 100644
--- a/sv/rtl/riverlib/core/tracer.sv
+++ b/sv/rtl/riverlib/core/tracer.sv
@@ -1058,21 +1058,21 @@ begin: comb_proc
 
     if (~async_reset && i_nrst == 1'b0) begin
         for (int i = 0; i < TRACE_TBL_SZ; i++) begin
-            v.trace_tbl[i].exec_cnt = '0;
+            v.trace_tbl[i].exec_cnt = 64'd0;
             v.trace_tbl[i].pc = '0;
-            v.trace_tbl[i].instr = '0;
-            v.trace_tbl[i].regactioncnt = '0;
-            v.trace_tbl[i].memactioncnt = '0;
+            v.trace_tbl[i].instr = 32'd0;
+            v.trace_tbl[i].regactioncnt = 32'd0;
+            v.trace_tbl[i].memactioncnt = 32'd0;
             for (int j = 0; j < TRACE_TBL_SZ; j++) begin
-                v.trace_tbl[i].regaction[j].waddr = '0;
-                v.trace_tbl[i].regaction[j].wres = '0;
+                v.trace_tbl[i].regaction[j].waddr = 6'd0;
+                v.trace_tbl[i].regaction[j].wres = 64'd0;
             end
             for (int j = 0; j < TRACE_TBL_SZ; j++) begin
                 v.trace_tbl[i].memaction[j].store = 1'b0;
-                v.trace_tbl[i].memaction[j].size = '0;
-                v.trace_tbl[i].memaction[j].mask = '0;
-                v.trace_tbl[i].memaction[j].memaddr = '0;
-                v.trace_tbl[i].memaction[j].data = '0;
+                v.trace_tbl[i].memaction[j].size = 2'd0;
+                v.trace_tbl[i].memaction[j].mask = 64'd0;
+                v.trace_tbl[i].memaction[j].memaddr = 64'd0;
+                v.trace_tbl[i].memaction[j].data = 64'd0;
                 v.trace_tbl[i].memaction[j].regaddr = 6'd0;
                 v.trace_tbl[i].memaction[j].complete = 1'b0;
                 v.trace_tbl[i].memaction[j].sc_release = 1'b0;
@@ -1122,21 +1122,21 @@ generate
         always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
             if (i_nrst == 1'b0) begin
                 for (int i = 0; i < TRACE_TBL_SZ; i++) begin
-                    r.trace_tbl[i].exec_cnt <= '0;
+                    r.trace_tbl[i].exec_cnt <= 64'd0;
                     r.trace_tbl[i].pc <= '0;
-                    r.trace_tbl[i].instr <= '0;
-                    r.trace_tbl[i].regactioncnt <= '0;
-                    r.trace_tbl[i].memactioncnt <= '0;
+                    r.trace_tbl[i].instr <= 32'd0;
+                    r.trace_tbl[i].regactioncnt <= 32'd0;
+                    r.trace_tbl[i].memactioncnt <= 32'd0;
                     for (int j = 0; j < TRACE_TBL_SZ; j++) begin
-                        r.trace_tbl[i].regaction[j].waddr <= '0;
-                        r.trace_tbl[i].regaction[j].wres <= '0;
+                        r.trace_tbl[i].regaction[j].waddr <= 6'd0;
+                        r.trace_tbl[i].regaction[j].wres <= 64'd0;
                     end
                     for (int j = 0; j < TRACE_TBL_SZ; j++) begin
                         r.trace_tbl[i].memaction[j].store <= 1'b0;
-                        r.trace_tbl[i].memaction[j].size <= '0;
-                        r.trace_tbl[i].memaction[j].mask <= '0;
-                        r.trace_tbl[i].memaction[j].memaddr <= '0;
-                        r.trace_tbl[i].memaction[j].data <= '0;
+                        r.trace_tbl[i].memaction[j].size <= 2'd0;
+                        r.trace_tbl[i].memaction[j].mask <= 64'd0;
+                        r.trace_tbl[i].memaction[j].memaddr <= 64'd0;
+                        r.trace_tbl[i].memaction[j].data <= 64'd0;
                         r.trace_tbl[i].memaction[j].regaddr <= 6'd0;
                         r.trace_tbl[i].memaction[j].complete <= 1'b0;
                         r.trace_tbl[i].memaction[j].sc_release <= 1'b0;
diff --git a/sv/rtl/riverlib/dmi/jtagtap.sv b/sv/rtl/riverlib/dmi/jtagtap.sv
index e330bcfb..5cb832a8 100644
--- a/sv/rtl/riverlib/dmi/jtagtap.sv
+++ b/sv/rtl/riverlib/dmi/jtagtap.sv
@@ -72,6 +72,16 @@ localparam bit [3:0] UPDATE_IR = 4'd15;
 
 localparam int drlen = ((abits + 32) + 2);
 
+typedef struct {
+    logic [irlen-1:0] ir;
+    logic [abits-1:0] dmi_addr;
+} jtagtap_nrhegisters;
+
+const jtagtap_nrhegisters jtagtap_nrh_reset = '{
+    IR_IDCODE,                          // ir
+    '0                                  // dmi_addr
+};
+
 typedef struct {
     logic [3:0] state;
     logic [6:0] dr_length;
@@ -80,9 +90,9 @@ typedef struct {
     logic [31:0] datacnt;
     logic dmi_busy;
     logic [1:0] err_sticky;
-} jtagtap_registers;
+} jtagtap_rhegisters;
 
-const jtagtap_registers jtagtap_r_reset = '{
+const jtagtap_rhegisters jtagtap_rh_reset = '{
     RESET_TAP,                          // state
     '0,                                 // dr_length
     idcode,                             // dr
@@ -92,18 +102,8 @@ const jtagtap_registers jtagtap_r_reset = '{
     '0                                  // err_sticky
 };
 
-typedef struct {
-    logic [irlen-1:0] ir;
-    logic [abits-1:0] dmi_addr;
-} jtagtap_nregisters;
-
-const jtagtap_nregisters jtagtap_nr_reset = '{
-    IR_IDCODE,                          // ir
-    '0                                  // dmi_addr
-};
-
-jtagtap_registers r, rin;
-jtagtap_nregisters nr, nrin;
+jtagtap_nrhegisters nrh, nrhin;
+jtagtap_rhegisters rh, rhin;
 
 
 always_comb
@@ -126,216 +126,216 @@ begin: comb_proc
     vb_err_sticky = '0;
     v_dmi_hardreset = 1'b0;
 
-    v = r;
-    nv = nr;
+    nvh = nrh;
+    vh = rh;
 
-    vb_dr = r.dr;
-    vb_err_sticky = r.err_sticky;
+    vb_dr = rh.dr;
+    vb_err_sticky = rh.err_sticky;
 
-    case (r.state)
+    case (rh.state)
     RESET_TAP: begin
-        nv.ir = IR_IDCODE;
+        nvh.ir = IR_IDCODE;
         if (i_tms == 1'b1) begin
-            v.state = RESET_TAP;
+            vh.state = RESET_TAP;
         end else begin
-            v.state = IDLE;
+            vh.state = IDLE;
         end
     end
     IDLE: begin
         if (i_tms == 1'b1) begin
-            v.state = SELECT_DR_SCAN;
+            vh.state = SELECT_DR_SCAN;
         end else begin
-            v.state = IDLE;
+            vh.state = IDLE;
         end
     end
     SELECT_DR_SCAN: begin
         if (i_tms == 1'b1) begin
-            v.state = SELECT_IR_SCAN;
+            vh.state = SELECT_IR_SCAN;
         end else begin
-            v.state = CAPTURE_DR;
+            vh.state = CAPTURE_DR;
         end
     end
     CAPTURE_DR: begin
         if (i_tms == 1'b1) begin
-            v.state = EXIT1_DR;
+            vh.state = EXIT1_DR;
         end else begin
-            v.state = SHIFT_DR;
+            vh.state = SHIFT_DR;
         end
-        if (nr.ir == IR_IDCODE) begin
+        if (nrh.ir == IR_IDCODE) begin
             vb_dr = idcode;
-            v.dr_length = 7'd32;
-        end else if (nr.ir == IR_DTMCONTROL) begin
+            vh.dr_length = 7'd32;
+        end else if (nrh.ir == IR_DTMCONTROL) begin
             vb_dr[31: 0] = '0;
             vb_dr[3: 0] = 4'h1;                             // version
             vb_dr[9: 4] = abits;                            // the size of the address
-            vb_dr[11: 10] = r.err_sticky;
-            v.dr_length = 7'd32;
-        end else if (nr.ir == IR_DBUS) begin
+            vb_dr[11: 10] = rh.err_sticky;
+            vh.dr_length = 7'd32;
+        end else if (nrh.ir == IR_DBUS) begin
             if (i_dmi_error == 1'b1) begin
                 vb_err_sticky = DMISTAT_FAILED;
                 vb_dr[1: 0] = DMISTAT_FAILED;
             end else begin
-                vb_dr[1: 0] = r.err_sticky;
+                vb_dr[1: 0] = rh.err_sticky;
             end
             vb_dr[33: 2] = i_dmi_resp_data;
-            vb_dr[((34 + abits) - 1): 34] = nr.dmi_addr;
-            v.dr_length = (abits + 7'd34);
-        end else if (nr.ir == IR_BYPASS) begin
-            vb_dr[0] = r.bypass;
-            v.dr_length = 7'd1;
+            vb_dr[((34 + abits) - 1): 34] = nrh.dmi_addr;
+            vh.dr_length = (abits + 7'd34);
+        end else if (nrh.ir == IR_BYPASS) begin
+            vb_dr[0] = rh.bypass;
+            vh.dr_length = 7'd1;
         end
-        v.datacnt = 32'd0;
+        vh.datacnt = 32'd0;
     end
     SHIFT_DR: begin
         if (i_tms == 1'b1) begin
-            v.state = EXIT1_DR;
+            vh.state = EXIT1_DR;
         end else begin
-            v.state = SHIFT_DR;
+            vh.state = SHIFT_DR;
         end
-        if (r.dr_length > 7'd1) begin
+        if (rh.dr_length > 7'd1) begin
             // For the bypass dr_length = 1
-            vb_dr = {1'b0, r.dr[(drlen - 1): 1]};
-            vb_dr[(int'(r.dr_length) - 1)] = i_tdi;
+            vb_dr = {1'b0, rh.dr[(drlen - 1): 1]};
+            vb_dr[(int'(rh.dr_length) - 1)] = i_tdi;
         end else begin
             vb_dr[0] = i_tdi;
         end
-        v.datacnt = (r.datacnt + 1);                        // debug counter no need in rtl
+        vh.datacnt = (rh.datacnt + 1);                      // debug counter no need in rtl
     end
     EXIT1_DR: begin
         if (i_tms == 1'b1) begin
-            v.state = UPDATE_DR;
+            vh.state = UPDATE_DR;
         end else begin
-            v.state = PAUSE_DR;
+            vh.state = PAUSE_DR;
         end
     end
     PAUSE_DR: begin
         if (i_tms == 1'b1) begin
-            v.state = EXIT2_DR;
+            vh.state = EXIT2_DR;
         end else begin
-            v.state = PAUSE_DR;
+            vh.state = PAUSE_DR;
         end
     end
     EXIT2_DR: begin
         if (i_tms == 1'b1) begin
-            v.state = UPDATE_DR;
+            vh.state = UPDATE_DR;
         end else begin
-            v.state = SHIFT_DR;
+            vh.state = SHIFT_DR;
         end
     end
     UPDATE_DR: begin
         if (i_tms == 1'b1) begin
-            v.state = SELECT_DR_SCAN;
+            vh.state = SELECT_DR_SCAN;
         end else begin
-            v.state = IDLE;
+            vh.state = IDLE;
         end
-        if (nr.ir == IR_DTMCONTROL) begin
-            v_dmi_hardreset = r.dr[DTMCONTROL_DMIHARDRESET];
-            if (r.dr[DTMCONTROL_DMIRESET] == 1'b1) begin
+        if (nrh.ir == IR_DTMCONTROL) begin
+            v_dmi_hardreset = rh.dr[DTMCONTROL_DMIHARDRESET];
+            if (rh.dr[DTMCONTROL_DMIRESET] == 1'b1) begin
                 vb_err_sticky = DMISTAT_SUCCESS;
             end
-        end else if (nr.ir == IR_BYPASS) begin
-            v.bypass = r.dr[0];
-        end else if (nr.ir == IR_DBUS) begin
-            if (r.err_sticky != DMISTAT_SUCCESS) begin
+        end else if (nrh.ir == IR_BYPASS) begin
+            vh.bypass = rh.dr[0];
+        end else if (nrh.ir == IR_DBUS) begin
+            if (rh.err_sticky != DMISTAT_SUCCESS) begin
                 // This operation should never result in a busy or error response.
-            end else if (r.dmi_busy == 1'b1) begin
+            end else if (rh.dmi_busy == 1'b1) begin
                 vb_err_sticky = DMISTAT_BUSY;
             end else begin
-                v_dmi_req_valid = (|r.dr[1: 0]);
+                v_dmi_req_valid = (|rh.dr[1: 0]);
             end
-            v_dmi_req_write = r.dr[1];
-            vb_dmi_req_data = r.dr[33: 2];
-            vb_dmi_req_addr = r.dr[((34 + abits) - 1): 34];
+            v_dmi_req_write = rh.dr[1];
+            vb_dmi_req_data = rh.dr[33: 2];
+            vb_dmi_req_addr = rh.dr[((34 + abits) - 1): 34];
 
-            nv.dmi_addr = r.dr[((34 + abits) - 1): 34];
+            nvh.dmi_addr = rh.dr[((34 + abits) - 1): 34];
         end
     end
     SELECT_IR_SCAN: begin
         if (i_tms == 1'b1) begin
-            v.state = RESET_TAP;
+            vh.state = RESET_TAP;
         end else begin
-            v.state = CAPTURE_IR;
+            vh.state = CAPTURE_IR;
         end
     end
     CAPTURE_IR: begin
         if (i_tms == 1'b1) begin
-            v.state = EXIT1_IR;
+            vh.state = EXIT1_IR;
         end else begin
-            v.state = SHIFT_IR;
+            vh.state = SHIFT_IR;
         end
-        vb_dr[(irlen - 1): 2] = nr.ir[(irlen - 1): 2];
+        vb_dr[(irlen - 1): 2] = nrh.ir[(irlen - 1): 2];
         vb_dr[1: 0] = 2'h1;
     end
     SHIFT_IR: begin
         if (i_tms == 1'b1) begin
-            v.state = EXIT1_IR;
+            vh.state = EXIT1_IR;
         end else begin
-            v.state = SHIFT_IR;
+            vh.state = SHIFT_IR;
         end
         vb_dr[(irlen - 1)] = i_tdi;
-        vb_dr[(irlen - 2): 0] = r.dr[(irlen - 1): 1];
+        vb_dr[(irlen - 2): 0] = rh.dr[(irlen - 1): 1];
     end
     EXIT1_IR: begin
         if (i_tms == 1'b1) begin
-            v.state = UPDATE_IR;
+            vh.state = UPDATE_IR;
         end else begin
-            v.state = PAUSE_IR;
+            vh.state = PAUSE_IR;
         end
     end
     PAUSE_IR: begin
         if (i_tms == 1'b1) begin
-            v.state = EXIT2_IR;
+            vh.state = EXIT2_IR;
         end else begin
-            v.state = PAUSE_IR;
+            vh.state = PAUSE_IR;
         end
     end
     EXIT2_IR: begin
         if (i_tms == 1'b1) begin
-            v.state = UPDATE_IR;
+            vh.state = UPDATE_IR;
         end else begin
-            v.state = SHIFT_IR;
+            vh.state = SHIFT_IR;
         end
     end
     UPDATE_IR: begin
         if (i_tms == 1'b1) begin
-            v.state = SELECT_DR_SCAN;
+            vh.state = SELECT_DR_SCAN;
         end else begin
-            v.state = IDLE;
+            vh.state = IDLE;
         end
-        nv.ir = r.dr[(irlen - 1): 0];
+        nvh.ir = rh.dr[(irlen - 1): 0];
     end
     default: begin
     end
     endcase
-    v.dr = vb_dr;
-    v.dmi_busy = i_dmi_busy;
-    v.err_sticky = vb_err_sticky;
+    vh.dr = vb_dr;
+    vh.dmi_busy = i_dmi_busy;
+    vh.err_sticky = vb_err_sticky;
 
-    o_tdo = r.dr[0];
+    o_tdo = rh.dr[0];
     o_dmi_req_valid = v_dmi_req_valid;
     o_dmi_req_write = v_dmi_req_write;
     o_dmi_req_data = vb_dmi_req_data;
     o_dmi_req_addr = vb_dmi_req_addr;
     o_dmi_hardreset = v_dmi_hardreset;
 
-    rin = v;
-    nrin = nv;
+    nrhin = nvh;
+    rhin = vh;
 end: comb_proc
 
-
-always_ff @(posedge i_tck, posedge i_trst) begin: rg_proc
+always_ff @(negedge i_tck, posedge i_trst) begin: nrhg_proc
     if (i_trst == 1'b1) begin
-        r <= jtagtap_r_reset;
+        nrh <= jtagtap_nrh_reset;
     end else begin
-        r <= rin;
+        nrh <= nrhin;
     end
-end: rg_proc
+end: nrhg_proc
 
-always_ff @(negedge i_tck, posedge i_trst) begin
+always_ff @(posedge i_tck, posedge i_trst) begin: rhg_proc
     if (i_trst == 1'b1) begin
-        nr <= jtagtap_nr_reset;
+        rh <= jtagtap_rh_reset;
     end else begin
-        nr <= nrin;
+        rh <= rhin;
     end
-end
+end: rhg_proc
+
 endmodule: jtagtap