Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Elfloader: NVIDIA Jetson Orin support #190

Open
wants to merge 19 commits into
base: master
Choose a base branch
from
Open

Elfloader: NVIDIA Jetson Orin support #190

Show file tree
Hide file tree
Changes from 14 commits
Commits
Show all changes
19 commits
Select commit Hold shift + click to select a range
9f2a8d0
elfloader: add support for Jetson Orin
Oct 24, 2023
276519b
elfloader: arm: flush dcache by va range instead
Nov 3, 2023
b9c6f44
elfloader: arm: stabilize secondary core booting
Nov 16, 2023
0cdf9c2
elfloader: arm: move kernel page table init code
Nov 16, 2023
0108b77
elfloader: arm: do not save FP and LR on stack
Nov 16, 2023
7b3c2f3
elfloader: arm: fix incorrect sp when restoring
Jul 11, 2023
1aa2fb0
elfloader: arm: fix function declaration
mro-github-12345 Jul 11, 2023
c329bef
elfloader: arm: fix alignment of AArch32
mro-github-12345 Jul 18, 2023
e8a15ec
elfloader: fix variable prototype and remove var
mro-github-12345 Aug 22, 2023
dea6924
elfloader: fix EFI image size
mro-github-12345 Aug 14, 2023
65b49ae
elfloader: move the data of ELFloader together
mro-github-12345 Aug 23, 2023
fa81fff
elfloader: arm: do not hard-code values
mro-github-12345 Jul 14, 2023
33f00c8
elfloader: arm: fix potential UB in right shift
mro-github-12345 Aug 21, 2023
4996de7
elfloader: setup pagetables as needed
mro-github-12345 Aug 23, 2023
5ebb1fc
elfloader: Exit UEFI boot services very early
mro-github-12345 Aug 24, 2023
80b8902
elfloader: Rewrite loop: Do not use goto
mro-github-12345 Dec 14, 2023
0e0a99d
elfloader: fix UEFI integration bug: descriptor
mro-github-12345 Dec 14, 2023
16ea8ef
elfloader: Set Exec-Never for Device Memory
mro-github-12345 Jan 31, 2024
84a55cd
elfloader: unconditionally set PTE shareability to
Feb 7, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion cmake-tool/helpers/application_settings.cmake
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ function(ApplyData61ElfLoaderSettings kernel_platform kernel_sel4_arch)
binary_list
"tx1;hikey;odroidc2;odroidc4;imx8mq-evk;imx8mm-evk;hifive;tqma8xqp1gb;bcm2711;rocketchip"
)
set(efi_list "tk1;rockpro64;quartz64")
set(efi_list "tk1;rockpro64;quartz64;orin")
set(uimage_list "tx2;am335x")
if(
${kernel_platform} IN_LIST efi_list
Expand Down
65 changes: 65 additions & 0 deletions elfloader-tool/include/arch-arm/64/mode/aarch64.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,65 @@
/*
* Copyright 2023, NIO GmbH
*
* SPDX-License-Identifier: GPL-2.0-only
*/
#pragma once

/* This file contains useful defines for assembly and C code. */

#define PSR_F_BIT 0x00000040
#define PSR_I_BIT 0x00000080
#define PSR_A_BIT 0x00000100
#define PSR_D_BIT 0x00000200

#define PSR_MODE_EL0t 0x00000000
#define PSR_MODE_EL1t 0x00000004
#define PSR_MODE_EL1h 0x00000005
#define PSR_MODE_EL2t 0x00000008
#define PSR_MODE_EL2h 0x00000009
#define PSR_MODE_SVC_32 0x00000013

#define TCR_T0SZ(x) ((64 - (x)))
#define TCR_T1SZ(x) ((64 - (x)) << 16)
#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))

#define TCR_IRGN0_WBWC (1 << 8)
#define TCR_IRGN_NC ((0 << 8) | (0 << 24))
#define TCR_IRGN_WBWA ((1 << 8) | (1 << 24))
#define TCR_IRGN_WT ((2 << 8) | (2 << 24))
#define TCR_IRGN_WBnWA ((3 << 8) | (3 << 24))
#define TCR_IRGN_MASK ((3 << 8) | (3 << 24))

#define TCR_ORGN0_WBWC (1 << 10)
#define TCR_ORGN_NC ((0 << 10) | (0 << 26))
#define TCR_ORGN_WBWA ((1 << 10) | (1 << 26))
#define TCR_ORGN_WT ((2 << 10) | (2 << 26))
#define TCR_ORGN_WBnWA ((3 << 10) | (3 << 26))
#define TCR_ORGN_MASK ((3 << 10) | (3 << 26))

#define TCR_SH0_ISH (3 << 12)
#define TCR_SHARED ((3 << 12) | (3 << 28))

#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG1_4K (2 << 30)
#define TCR_TG1_64K (3 << 30)

#define TCR_PS_4G (0 << 16)
#define TCR_PS_64G (1 << 16)
#define TCR_PS_1T (2 << 16)
#define TCR_PS_4T (3 << 16)
#define TCR_PS_16T (4 << 16)
#define TCR_PS_256T (5 << 16)

/* bits are reserved as 1 */
#define TCR_EL2_RES1 ((1 << 23) | (1 << 31))
#define TCR_ASID16 (1 << 36)

#define MT_DEVICE_nGnRnE 0
#define MT_DEVICE_nGnRE 1
#define MT_DEVICE_GRE 2
#define MT_NORMAL_NC 3
#define MT_NORMAL 4
#define MT_NORMAL_WT 5
#define MAIR(_attr, _mt) ((_attr) << ((_mt) * 8))
76 changes: 11 additions & 65 deletions elfloader-tool/include/arch-arm/64/mode/assembler.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,65 +9,17 @@
/* This file contains useful macros for assembly code. */

#ifdef __ASSEMBLER__
#include <mode/aarch64.h>

#define PSR_F_BIT 0x00000040
#define PSR_I_BIT 0x00000080
#define PSR_A_BIT 0x00000100
#define PSR_D_BIT 0x00000200

#define PSR_MODE_EL0t 0x00000000
#define PSR_MODE_EL1t 0x00000004
#define PSR_MODE_EL1h 0x00000005
#define PSR_MODE_EL2t 0x00000008
#define PSR_MODE_EL2h 0x00000009
#define PSR_MODE_SVC_32 0x00000013

#define TCR_T0SZ(x) ((64 - (x)))
#define TCR_T1SZ(x) ((64 - (x)) << 16)
#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))

#define TCR_IRGN0_WBWC (1 << 8)
#define TCR_IRGN_NC ((0 << 8) | (0 << 24))
#define TCR_IRGN_WBWA ((1 << 8) | (1 << 24))
#define TCR_IRGN_WT ((2 << 8) | (2 << 24))
#define TCR_IRGN_WBnWA ((3 << 8) | (3 << 24))
#define TCR_IRGN_MASK ((3 << 8) | (3 << 24))

#define TCR_ORGN0_WBWC (1 << 10)
#define TCR_ORGN_NC ((0 << 10) | (0 << 26))
#define TCR_ORGN_WBWA ((1 << 10) | (1 << 26))
#define TCR_ORGN_WT ((2 << 10) | (2 << 26))
#define TCR_ORGN_WBnWA ((3 << 10) | (3 << 26))
#define TCR_ORGN_MASK ((3 << 10) | (3 << 26))

#define TCR_SH0_ISH (3 << 12)
#define TCR_SHARED ((3 << 12) | (3 << 28))

#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG1_4K (2 << 30)
#define TCR_TG1_64K (3 << 30)

#define TCR_PS_4G (0 << 16)
#define TCR_PS_64G (1 << 16)
#define TCR_PS_1T (2 << 16)
#define TCR_PS_4T (3 << 16)
#define TCR_PS_16T (4 << 16)
#define TCR_PS_256T (5 << 16)

/* bits are reserved as 1 */
#define TCR_EL2_RES1 ((1 << 23) | (1 << 31))
#define TCR_ASID16 (1 << 36)

#define MT_DEVICE_nGnRnE 0
#define MT_DEVICE_nGnRE 1
#define MT_DEVICE_GRE 2
#define MT_NORMAL_NC 3
#define MT_NORMAL 4
#define MT_NORMAL_WT 5
#define MAIR(_attr, _mt) ((_attr) << ((_mt) * 8))
.macro disable_mmu sctlr tmp
__disable_mmu \sctlr, \tmp
ic ialluis
dsb sy
isb
.endm

.macro enable_mmu sctlr tmp
dsb sy
mrs \tmp, \sctlr
orr \tmp, \tmp, #(1 << 0)
orr \tmp, \tmp, #(1 << 2)
Expand All @@ -76,17 +28,11 @@
isb
.endm

.macro disable_mmu sctlr tmp
mrs \tmp, \sctlr
bic \tmp, \tmp, #(1 << 0)
bic \tmp, \tmp, #(1 << 2)
bic \tmp, \tmp, #(1 << 12)
msr \sctlr, \tmp
.macro __disable_mmu sctlr tmp
dsb sy
isb
.endm

.macro disable_id_cache sctlr tmp
mrs \tmp, \sctlr
bic \tmp, \tmp, #(1 << 0)
bic \tmp, \tmp, #(1 << 2)
bic \tmp, \tmp, #(1 << 12)
msr \sctlr, \tmp
Expand Down
16 changes: 9 additions & 7 deletions elfloader-tool/include/arch-arm/64/mode/structures.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,12 @@

#pragma once

/* ARM VMSAv8-64 (with a fully populated last level) has the same number of PTEs
* in all levels (we don't use concatenated pagetables in ELFloader) and each
* table entry is always eight bytes large.
*/
#define BITS_PER_LEVEL (PAGE_BITS - 3)

#define ARM_1GB_BLOCK_BITS 30
#define ARM_2MB_BLOCK_BITS 21

Expand All @@ -21,14 +27,10 @@
#define PMD_BITS 9
#define PMD_SIZE_BITS (PMD_BITS + PMDE_SIZE_BITS)

#define GET_PGD_INDEX(x) (((x) >> (ARM_2MB_BLOCK_BITS + PMD_BITS + PUD_BITS)) & MASK(PGD_BITS))
#define GET_PUD_INDEX(x) (((x) >> (ARM_2MB_BLOCK_BITS + PMD_BITS)) & MASK(PUD_BITS))
#define GET_PMD_INDEX(x) (((x) >> (ARM_2MB_BLOCK_BITS)) & MASK(PMD_BITS))
#define GET_PGD_INDEX(x) (((word_t)(x) >> (ARM_2MB_BLOCK_BITS + PMD_BITS + PUD_BITS)) & MASK(PGD_BITS))
#define GET_PUD_INDEX(x) (((word_t)(x) >> (ARM_2MB_BLOCK_BITS + PMD_BITS)) & MASK(PUD_BITS))
#define GET_PMD_INDEX(x) (((word_t)(x) >> (ARM_2MB_BLOCK_BITS)) & MASK(PMD_BITS))

extern uint64_t _boot_pgd_up[BIT(PGD_BITS)];
extern uint64_t _boot_pud_up[BIT(PUD_BITS)];
extern uint64_t _boot_pmd_up[BIT(PMD_BITS)];

extern uint64_t _boot_pgd_down[BIT(PGD_BITS)];
extern uint64_t _boot_pud_down[BIT(PUD_BITS)];

2 changes: 1 addition & 1 deletion elfloader-tool/include/arch-arm/cpuid.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
uint32_t read_cpuid_id(void);

/* read MP ID register from CPUID */
uint32_t read_cpuid_mpidr(void);
word_t read_cpuid_mpidr(void);

/* check if CPU is in HYP/EL2 mode */
word_t is_hyp_mode(void);
Expand Down
15 changes: 15 additions & 0 deletions elfloader-tool/include/arch-arm/elfloader.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,22 @@ typedef void (*init_arm_kernel_t)(word_t ui_p_reg_start,

/* Enable the mmu. */
extern void arm_enable_mmu(void);

/* These functions are very similar however, there are some small differences
* between the ARMv8 and legacy implementation.
*
* New ARMv8 implementation:
* - Does the MMU disabling. This is to keep the time spent with MMU off low.
* - Is only meant if seL4 runs in EL2.
*/
#if defined(CONFIG_ARCH_AARCH64)
/* Switches MMU-related stuff: pagetables, MAIR & TCR etc. Works also if the MMU
* was off initially. EL2 translation regime only.
*/
extern void arm_switch_to_hyp_tables(void);
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Perhaps call it aarch64_switch_to_hyp_tables if there is no 32-bit version of it.

#else
extern void arm_enable_hyp_mmu(void);
#endif


/* Setup boot VSpace. */
Expand Down
5 changes: 5 additions & 0 deletions elfloader-tool/include/drivers/uart.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@

#pragma once

#include <autoconf.h>
#include <drivers/common.h>

#define dev_get_uart(dev) ((struct elfloader_uart_ops *)(dev->drv->ops))
Expand All @@ -16,3 +17,7 @@ struct elfloader_uart_ops {

volatile void *uart_get_mmio(void);
void uart_set_out(struct elfloader_device *out);
#if defined(CONFIG_ARCH_AARCH64)
/* Implemented in mmu.c */
void mmu_set_uart_base(volatile void *base);
#endif
1 change: 1 addition & 0 deletions elfloader-tool/src/arch-arm/64/cpuid.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@

#include <armv/machine.h>
#include <types.h>
#include <cpuid.h>

/* we only care about the affinity bits */
#define MPIDR_MASK (0xff00ffffff)
Expand Down
2 changes: 1 addition & 1 deletion elfloader-tool/src/arch-arm/64/crt0.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ BEGIN_FUNC(_start)
bl fixup_image_base
mov x2, x0
/* restore original arguments for next step */
ldp x0, x1, [sp, #-16]!
ldp x0, x1, [sp], #16
/* fixup_image_base returns 1 if no need to move */
cmp x2, #1
beq 1f
Expand Down
Loading