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cfgparse: add support for variable expansion
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saursin committed Dec 15, 2023
1 parent 5afc714 commit 2855d55
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Showing 2 changed files with 19 additions and 4 deletions.
8 changes: 6 additions & 2 deletions rtl/config/hydrogensoc.json
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,9 @@
"en_embedded": false,
"en_compressed": true,
"en_csr": true,
"en_exceptions": true
"en_exceptions": true,
"num_gpio_io": 32,
"num_spi_cs": 1
},
"isa": "rv32[en_embedded?e:i][en_compressed?c:]_[en_csr?zicsr:]",
"abi": "ilp32[en_embedded?e:]",
Expand All @@ -13,7 +15,9 @@
"[en_embedded?EN_RVE:]",
"[en_csr?EN_RVZICSR:]",
"[en_exceptions?EN_EXCEPT:]",
"[en_compressed?EN_RVC:]"
"[en_compressed?EN_RVC:]",
"NGPIO=[num_gpio_io]",
"NSPI_CS=[num_spi_cs]"
],
"vsrcs": [
"${RVATOM}/rtl/soc/hydrogensoc/HydrogenSoC.v"
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15 changes: 13 additions & 2 deletions scripts/cfgparse.py
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,7 @@ def search_file(filename: str, search_dirs: list):
# module.json
# {
# "name": "xyz", // name of the module
# "extends": "abc" // derive configuration for xyz from abc overriding the params
# "defines": [], // preprocessor defines
# "vsrcs": [], // Verilog sources
# "incdirs": [] // Verilog include directories
Expand Down Expand Up @@ -110,15 +111,25 @@ def eval_conditionals(self, ds:str or list or dict):
"""
def __eval(txt:str):
while '[' in txt:
# get expr bounds
expr_strt = txt.find('[')
expr_end = txt.find(']', expr_strt)
assert expr_end != -1, "malformed expression"

# Get fields
expr_que = txt.find('?', expr_strt)
if expr_que == -1: # ? not found: just evaluate expr and emplace
condn = txt[expr_strt+1:expr_end]
res = str(eval(condn, self.get_params()))
txt = txt[0:expr_strt]+res+txt[expr_end+1:]
continue

expr_col = txt.find(':', expr_que)
expr_end = txt.find(']', expr_col)
if expr_strt == -1 or expr_que == -1 or expr_col == -1 or expr_end == -1:
raise f'Malformed expr in {self.jsonfile}:{txt}'
condn = txt[expr_strt+1:expr_que]
res = txt[expr_que+1:expr_col] if eval(condn, self.get_params()) else txt[expr_col+1:expr_end]
txt = txt[0:expr_strt]+res+txt[expr_end+1:]
txt = txt[0:expr_strt]+res+txt[expr_end+1:]
return txt

if isinstance(ds, str):
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