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Aleph One 386 486PC Expansion Card (Diva PAL)
IOC address map :
0000-3fff - ROM
MEMC Address map (only A4/A5 decoded) :
00 - Interrupt source status register
bits 0-3 - high 4 bits of mailbox address
= 1 for IO
>= A for memory
bit 4 - is read access
bit 5 - is word access
bit 7 - ISSR contents valid
10 - Interrupt source control register
bit 0 - POWERGOOD
bit 1 - HISPEED
bit 6 - raise IRQ1 (keyboard)
bit 7 - raise IRQ8 (RTC)
bit 8 - raise IRQ3 (COM2)
bit 9 - raise IRQ6 (floppy)
bit 10 - raise IRQ5 (LPT2)
bit 11 - raise IRQ15 (HPC)
20 - Mailbox data register
read clears pending write and resumes 386
write clears pending read and resumes 386
30 - Mailbox address register
386 side is a basic 386SX design, using a SCAMP to provide most motherboard functions (DRAM control, PIC, PIT, DMA etc), and a UM82C452 for the onboard serial and parallel ports. Non-shadowed memory accesses between 0A0000-0FFFFF, as well as all IO accesses, will trap with address + data becoming present in the ARM-side mailbox. This allows for emulation of the missing components. The ARM can also trigger interrupts on the 386 side.
Either 1 or 4 MB of RAM is on board, with links determining the SCAMP RAMMAP register on reset.
There is no ROM on the 386 side, accesses to the BIOS area are trapped and emulated. On initial boot the BIOS code will copy itself to shadow RAM and disable ROM at that point.
CPUs were an Intel 386SX/25 on the 386PC card and a Cyrix 486SLC/25 on the 486PC card. BIOS source suggests a TI 486SXLC2/50 was also an option, I am unsure if any PAL-based cards were shipped with this CPU or if this was only used on the later Elvis cards.
The register interface seems to be the same for both "slow PAL" and "fast PAL" cards. Only difference is that the ARM-side code for "fast PAL" performs fewer dummy register accesses. PROM is likely different so that the cards can be distinguished.
Chris's Acorns: Aleph1 386PC Expansion Card