diff --git a/.editorconfig b/.editorconfig
index 8a3054287..ae4c97662 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -1,19 +1,31 @@
# Remove the line below if you want to inherit .editorconfig settings from higher directories
root = true
-# C# files
-[*.cs]
+[*]
#### Core EditorConfig Options ####
+# Set default charset
+charset = utf-8
+
# Indentation and spacing
indent_size = 4
indent_style = space
tab_width = 4
# New line preferences
-end_of_line = crlf
-insert_final_newline = false
+end_of_line = lf
+insert_final_newline = true
+
+# JSON files
+[*.json]
+
+# Indentation and spacing
+indent_size = 2
+tab_width = 2
+
+# C# files
+[*.cs]
#### .NET Coding Conventions ####
@@ -59,7 +71,7 @@ dotnet_style_prefer_simplified_interpolation = true:suggestion
dotnet_style_readonly_field = true:suggestion
# Parameter preferences
-dotnet_code_quality_unused_parameters = all:suggestion
+dotnet_code_quality_unused_parameters = all:silent
#### C# Coding Conventions ####
@@ -85,7 +97,7 @@ csharp_style_expression_bodied_properties = true:silent
# Pattern matching preferences
csharp_style_pattern_matching_over_as_with_null_check = true:suggestion
csharp_style_pattern_matching_over_is_with_cast_check = true:suggestion
-csharp_style_prefer_switch_expression = true:suggestion
+csharp_style_prefer_switch_expression = false:silent
# Null-checking preferences
csharp_style_conditional_delegate_call = true:suggestion
@@ -94,6 +106,7 @@ csharp_style_conditional_delegate_call = true:suggestion
csharp_prefer_static_local_function = true:suggestion
csharp_preferred_modifier_order = public,private,protected,internal,static,extern,new,virtual,abstract,sealed,override,readonly,unsafe,volatile,async:silent
csharp_style_prefer_readonly_struct = true
+csharp_style_prefer_method_group_conversion = true
# Code-block preferences
csharp_prefer_braces = true:silent
@@ -109,6 +122,7 @@ csharp_style_prefer_range_operator = true:suggestion
csharp_style_throw_expression = true:suggestion
csharp_style_unused_value_assignment_preference = discard_variable:suggestion
csharp_style_unused_value_expression_statement_preference = discard_variable:silent
+csharp_style_implicit_object_creation_when_type_is_apparent = true
# 'using' directive preferences
csharp_using_directive_placement = outside_namespace:silent
@@ -140,7 +154,6 @@ csharp_space_after_dot = false
csharp_space_after_keywords_in_control_flow_statements = true
csharp_space_after_semicolon_in_for_statement = true
csharp_space_around_binary_operators = before_and_after
-csharp_space_around_declaration_statements = false
csharp_space_before_colon_in_inheritance_clause = true
csharp_space_before_comma = false
csharp_space_before_dot = false
@@ -158,23 +171,31 @@ csharp_space_between_square_brackets = false
# Wrapping preferences
csharp_preserve_single_line_blocks = true
-csharp_preserve_single_line_statements = true
+csharp_preserve_single_line_statements = false
#### Naming styles ####
# Naming rules
-dotnet_naming_rule.interface_should_be_begins_with_i.severity = suggestion
-dotnet_naming_rule.interface_should_be_begins_with_i.symbols = interface
-dotnet_naming_rule.interface_should_be_begins_with_i.style = begins_with_i
+dotnet_naming_rule.interfaces_should_be_prefixed_with_I.severity = suggestion
+dotnet_naming_rule.interfaces_should_be_prefixed_with_I.symbols = interface
+dotnet_naming_rule.interfaces_should_be_prefixed_with_I.style = IPascalCase
dotnet_naming_rule.types_should_be_pascal_case.severity = suggestion
dotnet_naming_rule.types_should_be_pascal_case.symbols = types
-dotnet_naming_rule.types_should_be_pascal_case.style = pascal_case
+dotnet_naming_rule.types_should_be_pascal_case.style = PascalCase
dotnet_naming_rule.non_field_members_should_be_pascal_case.severity = suggestion
dotnet_naming_rule.non_field_members_should_be_pascal_case.symbols = non_field_members
-dotnet_naming_rule.non_field_members_should_be_pascal_case.style = pascal_case
+dotnet_naming_rule.non_field_members_should_be_pascal_case.style = PascalCase
+
+dotnet_naming_rule.private_static_readonly_fields_should_be_camel_case_and_prefixed_with__.symbols = private_static_readonly_fields
+dotnet_naming_rule.private_static_readonly_fields_should_be_camel_case_and_prefixed_with__.severity = suggestion
+dotnet_naming_rule.private_static_readonly_fields_should_be_camel_case_and_prefixed_with__.style = _camelCase
+
+dotnet_naming_rule.local_constants_should_be_pascal_case.symbols = local_constants
+dotnet_naming_rule.local_constants_should_be_pascal_case.severity = suggestion
+dotnet_naming_rule.local_constants_should_be_pascal_case.style = PascalCase
# Symbol specifications
@@ -190,14 +211,62 @@ dotnet_naming_symbols.non_field_members.applicable_kinds = property, event, meth
dotnet_naming_symbols.non_field_members.applicable_accessibilities = public, internal, private, protected, protected_internal, private_protected
dotnet_naming_symbols.non_field_members.required_modifiers =
-# Naming styles
+dotnet_naming_symbols.private_static_readonly_fields.applicable_kinds = field
+dotnet_naming_symbols.private_static_readonly_fields.applicable_accessibilities = private
+dotnet_naming_symbols.private_static_readonly_fields.required_modifiers = static, readonly
+
+dotnet_naming_symbols.local_constants.applicable_kinds = local
+dotnet_naming_symbols.local_constants.applicable_accessibilities = local
+dotnet_naming_symbols.local_constants.required_modifiers = const
-dotnet_naming_style.pascal_case.required_prefix =
-dotnet_naming_style.pascal_case.required_suffix =
-dotnet_naming_style.pascal_case.word_separator =
-dotnet_naming_style.pascal_case.capitalization = pascal_case
+# Naming styles
-dotnet_naming_style.begins_with_i.required_prefix = I
-dotnet_naming_style.begins_with_i.required_suffix =
-dotnet_naming_style.begins_with_i.word_separator =
-dotnet_naming_style.begins_with_i.capitalization = pascal_case
\ No newline at end of file
+dotnet_naming_style._camelCase.required_prefix = _
+dotnet_naming_style._camelCase.required_suffix =
+dotnet_naming_style._camelCase.word_separator =
+dotnet_naming_style._camelCase.capitalization = camel_case
+
+dotnet_naming_style.PascalCase.required_prefix =
+dotnet_naming_style.PascalCase.required_suffix =
+dotnet_naming_style.PascalCase.word_separator =
+dotnet_naming_style.PascalCase.capitalization = pascal_case
+
+dotnet_naming_style.IPascalCase.required_prefix = I
+dotnet_naming_style.IPascalCase.required_suffix =
+dotnet_naming_style.IPascalCase.word_separator =
+dotnet_naming_style.IPascalCase.capitalization = pascal_case
+
+# TODO:
+# .NET 8 migration (new warnings are caused by the NET 8 C# compiler and analyzer)
+# The following info messages might need to be fixed in the source code instead of hiding the actual message
+# Without the following lines, dotnet format would fail
+# Disable "Collection initialization can be simplified"
+dotnet_diagnostic.IDE0028.severity = none
+dotnet_diagnostic.IDE0300.severity = none
+dotnet_diagnostic.IDE0301.severity = none
+dotnet_diagnostic.IDE0302.severity = none
+dotnet_diagnostic.IDE0305.severity = none
+# Disable "'new' expression can be simplified"
+dotnet_diagnostic.IDE0090.severity = none
+# Disable "Use primary constructor"
+dotnet_diagnostic.IDE0290.severity = none
+# Disable "Member '' does not access instance data and can be marked as static"
+dotnet_diagnostic.CA1822.severity = none
+# Disable "Change type of field '' from '' to '' for improved performance"
+dotnet_diagnostic.CA1859.severity = none
+# Disable "Prefer 'static readonly' fields over constant array arguments if the called method is called repeatedly and is not mutating the passed array"
+dotnet_diagnostic.CA1861.severity = none
+# Disable "Prefer using 'string.Equals(string, StringComparison)' to perform a case-insensitive comparison, but keep in mind that this might cause subtle changes in behavior, so make sure to conduct thorough testing after applying the suggestion, or if culturally sensitive comparison is not required, consider using 'StringComparison.OrdinalIgnoreCase'"
+dotnet_diagnostic.CA1862.severity = none
+
+[src/Ryujinx.HLE/HOS/Services/**.cs]
+# Disable "mark members as static" rule for services
+dotnet_diagnostic.CA1822.severity = none
+
+[src/Ryujinx.Ava/UI/ViewModels/**.cs]
+# Disable "mark members as static" rule for ViewModels
+dotnet_diagnostic.CA1822.severity = none
+
+[src/Ryujinx.Tests/Cpu/*.cs]
+# Disable naming rules for CPU tests
+dotnet_diagnostic.IDE1006.severity = none
diff --git a/.github/ISSUE_TEMPLATE/missing_shader_instruction.yml b/.github/ISSUE_TEMPLATE/missing_shader_instruction.yml
new file mode 100644
index 000000000..df37859a5
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/missing_shader_instruction.yml
@@ -0,0 +1,19 @@
+name: Missing Shader Instruction
+description: Shader Instruction is missing in Ryujinx.
+title: "[GPU]"
+labels: [gpu, not-implemented]
+body:
+ - type: textarea
+ id: instruction
+ attributes:
+ label: Shader instruction
+ description: What shader instruction is missing?
+ validations:
+ required: true
+ - type: textarea
+ id: required
+ attributes:
+ label: Required by
+ description: Add links to the [compatibility list page(s)](https://github.com/Ryujinx/Ryujinx-Games-List/issues) of the game(s) that require this instruction.
+ validations:
+ required: true
diff --git a/.github/csc.json b/.github/csc.json
new file mode 100644
index 000000000..2b960edd1
--- /dev/null
+++ b/.github/csc.json
@@ -0,0 +1,18 @@
+{
+ "problemMatcher": [
+ {
+ "owner": "csc",
+ "pattern": [
+ {
+ "regexp": "^((?:\\\\|/)(?:[^\\\\/:]+(?:\\\\|/))+[^\\\\/]+)\\((\\d+),(\\d+)\\):\\s+([a-zA-Z]+)\\s+([^:]+):\\s+([^[]+)\\s+\\[",
+ "file": 1,
+ "line": 2,
+ "column": 3,
+ "severity": 4,
+ "code": 5,
+ "message": 6
+ }
+ ]
+ }
+ ]
+}
diff --git a/.github/dependabot.yml b/.github/dependabot.yml
index 1516f8a7d..491676acb 100644
--- a/.github/dependabot.yml
+++ b/.github/dependabot.yml
@@ -13,7 +13,7 @@ updates:
- package-ecosystem: nuget
directory: /
- open-pull-requests-limit: 5
+ open-pull-requests-limit: 10
schedule:
interval: daily
labels:
@@ -22,3 +22,19 @@ updates:
- marysaka
commit-message:
prefix: nuget
+ groups:
+ Avalonia:
+ patterns:
+ - "*Avalonia*"
+ Silk.NET:
+ patterns:
+ - "Silk.NET*"
+ OpenTK:
+ patterns:
+ - "OpenTK*"
+ SixLabors:
+ patterns:
+ - "SixLabors*"
+ NUnit:
+ patterns:
+ - "NUnit*"
diff --git a/.github/labeler.yml b/.github/labeler.yml
new file mode 100644
index 000000000..027448437
--- /dev/null
+++ b/.github/labeler.yml
@@ -0,0 +1,35 @@
+audio:
+- changed-files:
+ - any-glob-to-any-file: 'src/Ryujinx.Audio*/**'
+
+cpu:
+- changed-files:
+ - any-glob-to-any-file: ['src/ARMeilleure/**', 'src/Ryujinx.Cpu/**', 'src/Ryujinx.Memory/**']
+
+gpu:
+- changed-files:
+ - any-glob-to-any-file: ['src/Ryujinx.Graphics.*/**', 'src/Spv.Generator/**', 'src/Ryujinx.ShaderTools/**']
+
+'graphics-backend:opengl':
+- changed-files:
+ - any-glob-to-any-file: 'src/Ryujinx.Graphics.OpenGL/**'
+
+'graphics-backend:vulkan':
+- changed-files:
+ - any-glob-to-any-file: ['src/Ryujinx.Graphics.Vulkan/**', 'src/Spv.Generator/**']
+
+gui:
+- changed-files:
+ - any-glob-to-any-file: ['src/Ryujinx/**', 'src/Ryujinx.Ui.Common/**', 'src/Ryujinx.Ui.LocaleGenerator/**', 'src/Ryujinx.Ava/**']
+
+horizon:
+- changed-files:
+ - any-glob-to-any-file: ['src/Ryujinx.HLE/**', 'src/Ryujinx.Horizon/**']
+
+kernel:
+- changed-files:
+ - any-glob-to-any-file: 'src/Ryujinx.HLE/HOS/Kernel/**'
+
+infra:
+- changed-files:
+ - any-glob-to-any-file: ['.github/**', 'distribution/**', 'Directory.Packages.props']
diff --git a/.github/reviewers.yml b/.github/reviewers.yml
new file mode 100644
index 000000000..052594f23
--- /dev/null
+++ b/.github/reviewers.yml
@@ -0,0 +1,32 @@
+audio:
+ - marysaka
+
+cpu:
+ - gdkchan
+ - riperiperi
+ - marysaka
+ - LDj3SNuD
+
+gpu:
+ - gdkchan
+ - riperiperi
+ - marysaka
+
+gui:
+ - Ack77
+ - emmauss
+ - TSRBerry
+ - marysaka
+
+horizon:
+ - gdkchan
+ - Ack77
+ - marysaka
+ - TSRBerry
+
+infra:
+ - marysaka
+ - TSRBerry
+
+default:
+ - '@developers'
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 843dd492a..cf4fdf051 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -1,27 +1,18 @@
name: Build job
on:
- workflow_dispatch:
- inputs: {}
- #push:
- # branches: [ master ]
- # paths-ignore:
- # - '.github/*'
- # - '.github/ISSUE_TEMPLATE/**'
- # - '*.yml'
- # - 'README.md'
- pull_request:
- branches: [ master ]
- paths-ignore:
- - '.github/*'
- - '.github/ISSUE_TEMPLATE/**'
- - '*.yml'
- - 'README.md'
+ workflow_call:
+
+env:
+ POWERSHELL_TELEMETRY_OPTOUT: 1
+ DOTNET_CLI_TELEMETRY_OPTOUT: 1
+ RYUJINX_BASE_VERSION: "1.1.0"
jobs:
build:
- name: ${{ matrix.os }} (${{ matrix.configuration }})
+ name: ${{ matrix.OS_NAME }} (${{ matrix.configuration }})
runs-on: ${{ matrix.os }}
+ timeout-minutes: 45
strategy:
matrix:
os: [ubuntu-latest, macOS-latest, windows-latest]
@@ -33,57 +24,135 @@ jobs:
RELEASE_ZIP_OS_NAME: linux_x64
- os: macOS-latest
- OS_NAME: MacOS x64
+ OS_NAME: macOS x64
DOTNET_RUNTIME_IDENTIFIER: osx-x64
RELEASE_ZIP_OS_NAME: osx_x64
- os: windows-latest
OS_NAME: Windows x64
- DOTNET_RUNTIME_IDENTIFIER: win10-x64
+ DOTNET_RUNTIME_IDENTIFIER: win-x64
RELEASE_ZIP_OS_NAME: win_x64
fail-fast: false
- env:
- POWERSHELL_TELEMETRY_OPTOUT: 1
- DOTNET_CLI_TELEMETRY_OPTOUT: 1
- RYUJINX_BASE_VERSION: "1.1.0"
steps:
- - uses: actions/checkout@v3
- - uses: actions/setup-dotnet@v3
+ - uses: actions/checkout@v4
+
+ - uses: actions/setup-dotnet@v4
with:
- dotnet-version: 7.0.x
+ global-json-file: global.json
+
+ - name: Overwrite csc problem matcher
+ run: echo "::add-matcher::.github/csc.json"
+
- name: Get git short hash
id: git_short_hash
run: echo "result=$(git rev-parse --short "${{ github.sha }}")" >> $GITHUB_OUTPUT
shell: bash
+
- name: Build
run: dotnet build -c "${{ matrix.configuration }}" -p:Version="${{ env.RYUJINX_BASE_VERSION }}" -p:SourceRevisionId="${{ steps.git_short_hash.outputs.result }}" -p:ExtraDefineConstants=DISABLE_UPDATER
+
- name: Test
- run: dotnet test --no-build -c "${{ matrix.configuration }}"
+ uses: TSRBerry/unstable-commands@v1
+ with:
+ commands: dotnet test --no-build -c "${{ matrix.configuration }}"
+ timeout-minutes: 10
+ retry-codes: 139
+
- name: Publish Ryujinx
run: dotnet publish -c "${{ matrix.configuration }}" -r "${{ matrix.DOTNET_RUNTIME_IDENTIFIER }}" -o ./publish -p:Version="${{ env.RYUJINX_BASE_VERSION }}" -p:DebugType=embedded -p:SourceRevisionId="${{ steps.git_short_hash.outputs.result }}" -p:ExtraDefineConstants=DISABLE_UPDATER src/Ryujinx --self-contained true
- if: github.event_name == 'pull_request'
+ if: github.event_name == 'pull_request' && matrix.os != 'macOS-latest'
+
- name: Publish Ryujinx.Headless.SDL2
run: dotnet publish -c "${{ matrix.configuration }}" -r "${{ matrix.DOTNET_RUNTIME_IDENTIFIER }}" -o ./publish_sdl2_headless -p:Version="${{ env.RYUJINX_BASE_VERSION }}" -p:DebugType=embedded -p:SourceRevisionId="${{ steps.git_short_hash.outputs.result }}" -p:ExtraDefineConstants=DISABLE_UPDATER src/Ryujinx.Headless.SDL2 --self-contained true
- if: github.event_name == 'pull_request'
+ if: github.event_name == 'pull_request' && matrix.os != 'macOS-latest'
+
- name: Publish Ryujinx.Ava
run: dotnet publish -c "${{ matrix.configuration }}" -r "${{ matrix.DOTNET_RUNTIME_IDENTIFIER }}" -o ./publish_ava -p:Version="${{ env.RYUJINX_BASE_VERSION }}" -p:DebugType=embedded -p:SourceRevisionId="${{ steps.git_short_hash.outputs.result }}" -p:ExtraDefineConstants=DISABLE_UPDATER src/Ryujinx.Ava --self-contained true
- if: github.event_name == 'pull_request'
+ if: github.event_name == 'pull_request' && matrix.os != 'macOS-latest'
+
+ - name: Set executable bit
+ run: |
+ chmod +x ./publish/Ryujinx ./publish/Ryujinx.sh
+ chmod +x ./publish_sdl2_headless/Ryujinx.Headless.SDL2 ./publish_sdl2_headless/Ryujinx.sh
+ chmod +x ./publish_ava/Ryujinx.Ava ./publish_ava/Ryujinx.sh
+ if: github.event_name == 'pull_request' && matrix.os == 'ubuntu-latest'
+
- name: Upload Ryujinx artifact
- uses: actions/upload-artifact@v3
+ uses: actions/upload-artifact@v4
with:
name: ryujinx-${{ matrix.configuration }}-${{ env.RYUJINX_BASE_VERSION }}+${{ steps.git_short_hash.outputs.result }}-${{ matrix.RELEASE_ZIP_OS_NAME }}
path: publish
- if: github.event_name == 'pull_request'
+ if: github.event_name == 'pull_request' && matrix.os != 'macOS-latest'
+
- name: Upload Ryujinx.Headless.SDL2 artifact
- uses: actions/upload-artifact@v3
+ uses: actions/upload-artifact@v4
with:
name: sdl2-ryujinx-headless-${{ matrix.configuration }}-${{ env.RYUJINX_BASE_VERSION }}+${{ steps.git_short_hash.outputs.result }}-${{ matrix.RELEASE_ZIP_OS_NAME }}
path: publish_sdl2_headless
- if: github.event_name == 'pull_request'
+ if: github.event_name == 'pull_request' && matrix.os != 'macOS-latest'
+
- name: Upload Ryujinx.Ava artifact
- uses: actions/upload-artifact@v3
+ uses: actions/upload-artifact@v4
with:
name: ava-ryujinx-${{ matrix.configuration }}-${{ env.RYUJINX_BASE_VERSION }}+${{ steps.git_short_hash.outputs.result }}-${{ matrix.RELEASE_ZIP_OS_NAME }}
path: publish_ava
- if: github.event_name == 'pull_request'
\ No newline at end of file
+ if: github.event_name == 'pull_request' && matrix.os != 'macOS-latest'
+
+ build_macos:
+ name: macOS Universal (${{ matrix.configuration }})
+ runs-on: ubuntu-latest
+ timeout-minutes: 45
+ strategy:
+ matrix:
+ configuration: [ Debug, Release ]
+
+ steps:
+ - uses: actions/checkout@v4
+
+ - uses: actions/setup-dotnet@v4
+ with:
+ global-json-file: global.json
+
+ - name: Setup LLVM 14
+ run: |
+ wget https://apt.llvm.org/llvm.sh
+ chmod +x llvm.sh
+ sudo ./llvm.sh 14
+
+ - name: Install rcodesign
+ run: |
+ mkdir -p $HOME/.bin
+ gh release download -R indygreg/apple-platform-rs -O apple-codesign.tar.gz -p 'apple-codesign-*-x86_64-unknown-linux-musl.tar.gz'
+ tar -xzvf apple-codesign.tar.gz --wildcards '*/rcodesign' --strip-components=1
+ rm apple-codesign.tar.gz
+ mv rcodesign $HOME/.bin/
+ echo "$HOME/.bin" >> $GITHUB_PATH
+ env:
+ GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+
+ - name: Get git short hash
+ id: git_short_hash
+ run: echo "result=$(git rev-parse --short "${{ github.sha }}")" >> $GITHUB_OUTPUT
+
+ - name: Publish macOS Ryujinx.Ava
+ run: |
+ ./distribution/macos/create_macos_build_ava.sh . publish_tmp_ava publish_ava ./distribution/macos/entitlements.xml "${{ env.RYUJINX_BASE_VERSION }}" "${{ steps.git_short_hash.outputs.result }}" "${{ matrix.configuration }}" "-p:ExtraDefineConstants=DISABLE_UPDATER"
+
+ - name: Publish macOS Ryujinx.Headless.SDL2
+ run: |
+ ./distribution/macos/create_macos_build_headless.sh . publish_tmp_headless publish_headless ./distribution/macos/entitlements.xml "${{ env.RYUJINX_BASE_VERSION }}" "${{ steps.git_short_hash.outputs.result }}" "${{ matrix.configuration }}" "-p:ExtraDefineConstants=DISABLE_UPDATER"
+
+ - name: Upload Ryujinx.Ava artifact
+ uses: actions/upload-artifact@v4
+ with:
+ name: ava-ryujinx-${{ matrix.configuration }}-${{ env.RYUJINX_BASE_VERSION }}+${{ steps.git_short_hash.outputs.result }}-macos_universal
+ path: "publish_ava/*.tar.gz"
+ if: github.event_name == 'pull_request'
+
+ - name: Upload Ryujinx.Headless.SDL2 artifact
+ uses: actions/upload-artifact@v4
+ with:
+ name: sdl2-ryujinx-headless-${{ matrix.configuration }}-${{ env.RYUJINX_BASE_VERSION }}+${{ steps.git_short_hash.outputs.result }}-macos_universal
+ path: "publish_headless/*.tar.gz"
+ if: github.event_name == 'pull_request'
diff --git a/.github/workflows/checks.yml b/.github/workflows/checks.yml
new file mode 100644
index 000000000..5311a67f6
--- /dev/null
+++ b/.github/workflows/checks.yml
@@ -0,0 +1,74 @@
+name: Perform checks
+
+on:
+ pull_request:
+ branches: [ master ]
+ paths:
+ - '**'
+ - '!.github/**'
+ - '!*.yml'
+ - '!*.config'
+ - '!README.md'
+ - '.github/workflows/*.yml'
+
+permissions:
+ pull-requests: write
+ checks: write
+
+concurrency:
+ group: pr-checks-${{ github.event.number }}
+ cancel-in-progress: true
+
+jobs:
+ format:
+ runs-on: ubuntu-latest
+ steps:
+ - uses: actions/checkout@v4
+ with:
+ fetch-depth: 0
+
+ - uses: actions/setup-dotnet@v4
+ with:
+ global-json-file: global.json
+
+ - name: Overwrite csc problem matcher
+ run: echo "::add-matcher::.github/csc.json"
+
+ - run: dotnet restore
+
+ - name: Print dotnet format version
+ run: dotnet format --version
+
+ - name: Run dotnet format whitespace
+ run: |
+ dotnet format whitespace --verify-no-changes --report ./whitespace-report.json -v d
+
+ # For some unknown reason this step sometimes fails with exit code 139 (segfault?),
+ # so in that case we'll try again (3 tries max).
+ - name: Run dotnet format style
+ uses: TSRBerry/unstable-commands@v1
+ with:
+ commands: dotnet format style --severity info --verify-no-changes --report ./style-report.json -v d
+ timeout-minutes: 5
+ retry-codes: 139
+
+ # For some unknown reason this step sometimes fails with exit code 139 (segfault?),
+ # so in that case we'll try again (3 tries max).
+ - name: Run dotnet format analyzers
+ uses: TSRBerry/unstable-commands@v1
+ with:
+ commands: dotnet format analyzers --severity info --verify-no-changes --report ./analyzers-report.json -v d
+ timeout-minutes: 5
+ retry-codes: 139
+
+ - name: Upload report
+ if: failure()
+ uses: actions/upload-artifact@v4
+ with:
+ name: dotnet-format
+ path: ./*-report.json
+
+ pr_build:
+ uses: ./.github/workflows/build.yml
+ needs: format
+ secrets: inherit
diff --git a/.github/workflows/flatpak.yml b/.github/workflows/flatpak.yml
index 86a80eabf..f529bea03 100644
--- a/.github/workflows/flatpak.yml
+++ b/.github/workflows/flatpak.yml
@@ -12,6 +12,7 @@ concurrency: flatpak-release
jobs:
release:
+ timeout-minutes: ${{ fromJSON(vars.JOB_TIMEOUT) }}
runs-on: ubuntu-latest
env:
@@ -23,11 +24,11 @@ jobs:
RYUJINX_VERSION: "${{ inputs.ryujinx_version }}"
steps:
- - uses: actions/checkout@v3
+ - uses: actions/checkout@v4
with:
path: Ryujinx
- - uses: actions/setup-dotnet@v3
+ - uses: actions/setup-dotnet@v4
with:
global-json-file: Ryujinx/global.json
@@ -37,7 +38,7 @@ jobs:
run: |
echo "git_hash=$(git rev-parse HEAD)" >> $GITHUB_OUTPUT
- - uses: actions/checkout@v3
+ - uses: actions/checkout@v4
with:
repository: flathub/org.ryujinx.Ryujinx
token: ${{ secrets.RYUJINX_BOT_PAT }}
@@ -48,7 +49,9 @@ jobs:
run: python -m pip install PyYAML lxml
- name: Restore Nuget packages
- run: dotnet restore Ryujinx/${{ env.RYUJINX_PROJECT_FILE }}
+ # With .NET 8.0.100, Microsoft.NET.ILLink.Tasks isn't restored by default and only seems to appears when publishing.
+ # So we just publish to grab the dependencies
+ run: dotnet publish -c Release -r linux-x64 Ryujinx/${{ env.RYUJINX_PROJECT_FILE }} --self-contained
- name: Generate nuget_sources.json
shell: python
diff --git a/.github/workflows/nightly_pr_comment.yml b/.github/workflows/nightly_pr_comment.yml
index bc3d1c43f..f59a6be1f 100644
--- a/.github/workflows/nightly_pr_comment.yml
+++ b/.github/workflows/nightly_pr_comment.yml
@@ -1,12 +1,15 @@
name: Comment PR artifacts links
+
on:
workflow_run:
- workflows: ['Build job']
+ workflows: ['Perform checks']
types: [completed]
+
jobs:
pr_comment:
if: github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success'
runs-on: ubuntu-latest
+ timeout-minutes: ${{ fromJSON(vars.JOB_TIMEOUT) }}
steps:
- uses: actions/github-script@v6
with:
@@ -65,4 +68,4 @@ jobs:
} else {
core.info(`Creating a comment`);
await github.rest.issues.createComment({repo, owner, issue_number, body});
- }
+ }
\ No newline at end of file
diff --git a/.github/workflows/pr_triage.yml b/.github/workflows/pr_triage.yml
new file mode 100644
index 000000000..93aa89626
--- /dev/null
+++ b/.github/workflows/pr_triage.yml
@@ -0,0 +1,47 @@
+name: "Pull Request Triage"
+on:
+ pull_request_target:
+ types: [opened, ready_for_review]
+
+jobs:
+ triage:
+ permissions:
+ contents: read
+ pull-requests: write
+
+ runs-on: ubuntu-latest
+
+ steps:
+ # Grab sources to get latest labeler.yml
+ - name: Fetch sources
+ uses: actions/checkout@v4
+ with:
+ # Ensure we pin the source origin as pull_request_target run under forks.
+ fetch-depth: 0
+ repository: Ryujinx/Ryujinx
+ ref: master
+
+ - name: Checkout Ryujinx-Mako
+ uses: actions/checkout@v4
+ with:
+ repository: Ryujinx/Ryujinx-Mako
+ ref: master
+ path: '.ryujinx-mako'
+
+ - name: Setup Ryujinx-Mako
+ uses: ./.ryujinx-mako/.github/actions/setup-mako
+
+ - name: Update labels based on changes
+ uses: actions/labeler@v5
+ with:
+ sync-labels: true
+ dot: true
+
+ - name: Assign reviewers
+ run: |
+ poetry -n -C .ryujinx-mako run ryujinx-mako update-reviewers ${{ github.repository }} ${{ github.event.pull_request.number }} .github/reviewers.yml
+ shell: bash
+ env:
+ MAKO_APP_ID: ${{ secrets.MAKO_APP_ID }}
+ MAKO_PRIVATE_KEY: ${{ secrets.MAKO_PRIVATE_KEY }}
+ MAKO_INSTALLATION_ID: ${{ secrets.MAKO_INSTALLATION_ID }}
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
index 914e5e33e..7a4b13d7d 100644
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -6,9 +6,10 @@ on:
push:
branches: [ master ]
paths-ignore:
- - '.github/*'
- - '.github/ISSUE_TEMPLATE/**'
+ - '.github/**'
- '*.yml'
+ - '*.json'
+ - '*.config'
- 'README.md'
concurrency: release
@@ -22,19 +23,61 @@ env:
RYUJINX_TARGET_RELEASE_CHANNEL_REPO: "release-channel-master"
jobs:
+ tag:
+ name: Create tag
+ runs-on: ubuntu-20.04
+ steps:
+ - name: Get version info
+ id: version_info
+ run: |
+ echo "build_version=${{ env.RYUJINX_BASE_VERSION }}.${{ github.run_number }}" >> $GITHUB_OUTPUT
+ shell: bash
+
+ - name: Create tag
+ uses: actions/github-script@v6
+ with:
+ script: |
+ github.rest.git.createRef({
+ owner: context.repo.owner,
+ repo: context.repo.repo,
+ ref: 'refs/tags/${{ steps.version_info.outputs.build_version }}',
+ sha: context.sha
+ })
+
release:
- runs-on: windows-latest
+ name: Release ${{ matrix.OS_NAME }}
+ runs-on: ${{ matrix.os }}
+ timeout-minutes: ${{ fromJSON(vars.JOB_TIMEOUT) }}
+ strategy:
+ matrix:
+ os: [ ubuntu-latest, windows-latest ]
+ include:
+ - os: ubuntu-latest
+ OS_NAME: Linux x64
+ DOTNET_RUNTIME_IDENTIFIER: linux-x64
+ RELEASE_ZIP_OS_NAME: linux_x64
+
+ - os: windows-latest
+ OS_NAME: Windows x64
+ DOTNET_RUNTIME_IDENTIFIER: win-x64
+ RELEASE_ZIP_OS_NAME: win_x64
steps:
- - uses: actions/checkout@v3
- - uses: actions/setup-dotnet@v3
+ - uses: actions/checkout@v4
+
+ - uses: actions/setup-dotnet@v4
with:
global-json-file: global.json
+
+ - name: Overwrite csc problem matcher
+ run: echo "::add-matcher::.github/csc.json"
+
- name: Get version info
id: version_info
run: |
echo "build_version=${{ env.RYUJINX_BASE_VERSION }}.${{ github.run_number }}" >> $GITHUB_OUTPUT
echo "git_short_hash=$(git rev-parse --short "${{ github.sha }}")" >> $GITHUB_OUTPUT
shell: bash
+
- name: Configure for release
run: |
sed -r --in-place 's/\%\%RYUJINX_BUILD_VERSION\%\%/${{ steps.version_info.outputs.build_version }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
@@ -43,58 +86,48 @@ jobs:
sed -r --in-place 's/\%\%RYUJINX_TARGET_RELEASE_CHANNEL_OWNER\%\%/${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_OWNER }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
sed -r --in-place 's/\%\%RYUJINX_TARGET_RELEASE_CHANNEL_REPO\%\%/${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_REPO }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
shell: bash
+
- name: Create output dir
run: "mkdir release_output"
- - name: Publish Windows
+
+ - name: Publish
run: |
- dotnet publish -c Release -r win10-x64 -o ./publish_windows/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx --self-contained true
- dotnet publish -c Release -r win10-x64 -o ./publish_windows_sdl2_headless/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx.Headless.SDL2 --self-contained true
- dotnet publish -c Release -r win10-x64 -o ./publish_windows_ava/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx.Ava --self-contained true
+ dotnet publish -c Release -r "${{ matrix.DOTNET_RUNTIME_IDENTIFIER }}" -o ./publish_gtk/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx --self-contained true
+ dotnet publish -c Release -r "${{ matrix.DOTNET_RUNTIME_IDENTIFIER }}" -o ./publish_sdl2_headless/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx.Headless.SDL2 --self-contained true
+ dotnet publish -c Release -r "${{ matrix.DOTNET_RUNTIME_IDENTIFIER }}" -o ./publish_ava/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx.Ava --self-contained true
+
- name: Packing Windows builds
+ if: matrix.os == 'windows-latest'
run: |
- pushd publish_windows
+ pushd publish_gtk
7z a ../release_output/ryujinx-${{ steps.version_info.outputs.build_version }}-win_x64.zip publish
popd
- pushd publish_windows_sdl2_headless
+ pushd publish_sdl2_headless
7z a ../release_output/sdl2-ryujinx-headless-${{ steps.version_info.outputs.build_version }}-win_x64.zip publish
popd
- pushd publish_windows_ava
+ pushd publish_ava
7z a ../release_output/test-ava-ryujinx-${{ steps.version_info.outputs.build_version }}-win_x64.zip publish
popd
shell: bash
- - name: Publish Linux
- run: |
- dotnet publish -c Release -r linux-x64 -o ./publish_linux/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx --self-contained true
- dotnet publish -c Release -r linux-x64 -o ./publish_linux_sdl2_headless/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx.Headless.SDL2 --self-contained true
- dotnet publish -c Release -r linux-x64 -o ./publish_linux_ava/publish -p:Version="${{ steps.version_info.outputs.build_version }}" -p:SourceRevisionId="${{ steps.version_info.outputs.git_short_hash }}" -p:DebugType=embedded src/Ryujinx.Ava --self-contained true
-
- name: Packing Linux builds
+ if: matrix.os == 'ubuntu-latest'
run: |
- pushd publish_linux
- tar --exclude "publish/Ryujinx" --exclude "publish/Ryujinx.sh" -cvf ../release_output/ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar publish
- python3 ../distribution/misc/add_tar_exec.py ../release_output/ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar "publish/Ryujinx" "publish/Ryujinx"
- python3 ../distribution/misc/add_tar_exec.py ../release_output/ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar "publish/Ryujinx.sh" "publish/Ryujinx.sh"
- gzip -9 < ../release_output/ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar > ../release_output/ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar.gz
- rm ../release_output/ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar
+ pushd publish_gtk
+ chmod +x publish/Ryujinx.sh publish/Ryujinx
+ tar -czvf ../release_output/ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar.gz publish
popd
- pushd publish_linux_sdl2_headless
- tar --exclude "publish/Ryujinx.Headless.SDL2" --exclude "publish/Ryujinx.sh" -cvf ../release_output/sdl2-ryujinx-headless-${{ steps.version_info.outputs.build_version }}-linux_x64.tar publish
- python3 ../distribution/misc/add_tar_exec.py ../release_output/sdl2-ryujinx-headless-${{ steps.version_info.outputs.build_version }}-linux_x64.tar "publish/Ryujinx.Headless.SDL2" "publish/Ryujinx.Headless.SDL2"
- python3 ../distribution/misc/add_tar_exec.py ../release_output/sdl2-ryujinx-headless-${{ steps.version_info.outputs.build_version }}-linux_x64.tar "publish/Ryujinx.sh" "publish/Ryujinx.sh"
- gzip -9 < ../release_output/sdl2-ryujinx-headless-${{ steps.version_info.outputs.build_version }}-linux_x64.tar > ../release_output/sdl2-ryujinx-headless-${{ steps.version_info.outputs.build_version }}-linux_x64.tar.gz
- rm ../release_output/sdl2-ryujinx-headless-${{ steps.version_info.outputs.build_version }}-linux_x64.tar
+ pushd publish_sdl2_headless
+ chmod +x publish/Ryujinx.sh publish/Ryujinx.Headless.SDL2
+ tar -czvf ../release_output/sdl2-ryujinx-headless-${{ steps.version_info.outputs.build_version }}-linux_x64.tar.gz publish
popd
- pushd publish_linux_ava
- tar --exclude "publish/Ryujinx.Ava" --exclude "publish/Ryujinx.sh" -cvf ../release_output/test-ava-ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar publish
- python3 ../distribution/misc/add_tar_exec.py ../release_output/test-ava-ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar "publish/Ryujinx.Ava" "publish/Ryujinx.Ava"
- python3 ../distribution/misc/add_tar_exec.py ../release_output/test-ava-ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar "publish/Ryujinx.sh" "publish/Ryujinx.sh"
- gzip -9 < ../release_output/test-ava-ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar > ../release_output/test-ava-ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar.gz
- rm ../release_output/test-ava-ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar
+ pushd publish_ava
+ chmod +x publish/Ryujinx.sh publish/Ryujinx.Ava
+ tar -czvf ../release_output/test-ava-ryujinx-${{ steps.version_info.outputs.build_version }}-linux_x64.tar.gz publish
popd
shell: bash
@@ -105,27 +138,81 @@ jobs:
artifacts: "release_output/*.tar.gz,release_output/*.zip"
tag: ${{ steps.version_info.outputs.build_version }}
body: "For more information about this release please check out the official [Changelog](https://github.com/Ryujinx/Ryujinx/wiki/Changelog)."
+ omitBodyDuringUpdate: true
allowUpdates: true
- removeArtifacts: true
replacesArtifacts: true
owner: ${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_OWNER }}
repo: ${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_REPO }}
token: ${{ secrets.RELEASE_TOKEN }}
- - name: Create tag
- uses: actions/github-script@v5
+ macos_release:
+ name: Release MacOS universal
+ runs-on: ubuntu-latest
+ timeout-minutes: ${{ fromJSON(vars.JOB_TIMEOUT) }}
+ steps:
+ - uses: actions/checkout@v4
+
+ - uses: actions/setup-dotnet@v4
with:
- script: |
- github.rest.git.createRef({
- owner: context.repo.owner,
- repo: context.repo.repo,
- ref: 'refs/tags/${{ steps.version_info.outputs.build_version }}',
- sha: context.sha
- })
+ global-json-file: global.json
+
+ - name: Setup LLVM 15
+ run: |
+ wget https://apt.llvm.org/llvm.sh
+ chmod +x llvm.sh
+ sudo ./llvm.sh 15
+
+ - name: Install rcodesign
+ run: |
+ mkdir -p $HOME/.bin
+ gh release download -R indygreg/apple-platform-rs -O apple-codesign.tar.gz -p 'apple-codesign-*-x86_64-unknown-linux-musl.tar.gz'
+ tar -xzvf apple-codesign.tar.gz --wildcards '*/rcodesign' --strip-components=1
+ rm apple-codesign.tar.gz
+ mv rcodesign $HOME/.bin/
+ echo "$HOME/.bin" >> $GITHUB_PATH
+ env:
+ GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+
+ - name: Get version info
+ id: version_info
+ run: |
+ echo "build_version=${{ env.RYUJINX_BASE_VERSION }}.${{ github.run_number }}" >> $GITHUB_OUTPUT
+ echo "git_short_hash=$(git rev-parse --short "${{ github.sha }}")" >> $GITHUB_OUTPUT
+
+ - name: Configure for release
+ run: |
+ sed -r --in-place 's/\%\%RYUJINX_BUILD_VERSION\%\%/${{ steps.version_info.outputs.build_version }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
+ sed -r --in-place 's/\%\%RYUJINX_BUILD_GIT_HASH\%\%/${{ steps.version_info.outputs.git_short_hash }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
+ sed -r --in-place 's/\%\%RYUJINX_TARGET_RELEASE_CHANNEL_NAME\%\%/${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_NAME }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
+ sed -r --in-place 's/\%\%RYUJINX_TARGET_RELEASE_CHANNEL_OWNER\%\%/${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_OWNER }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
+ sed -r --in-place 's/\%\%RYUJINX_TARGET_RELEASE_CHANNEL_REPO\%\%/${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_REPO }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
+ shell: bash
+
+ - name: Publish macOS Ryujinx.Ava
+ run: |
+ ./distribution/macos/create_macos_build_ava.sh . publish_tmp_ava publish_ava ./distribution/macos/entitlements.xml "${{ steps.version_info.outputs.build_version }}" "${{ steps.version_info.outputs.git_short_hash }}" Release
+
+ - name: Publish macOS Ryujinx.Headless.SDL2
+ run: |
+ ./distribution/macos/create_macos_build_headless.sh . publish_tmp_headless publish_headless ./distribution/macos/entitlements.xml "${{ steps.version_info.outputs.build_version }}" "${{ steps.version_info.outputs.git_short_hash }}" Release
+
+ - name: Pushing new release
+ uses: ncipollo/release-action@v1
+ with:
+ name: ${{ steps.version_info.outputs.build_version }}
+ artifacts: "publish_ava/*.tar.gz, publish_headless/*.tar.gz"
+ tag: ${{ steps.version_info.outputs.build_version }}
+ body: "For more information about this release please check out the official [Changelog](https://github.com/Ryujinx/Ryujinx/wiki/Changelog)."
+ omitBodyDuringUpdate: true
+ allowUpdates: true
+ replacesArtifacts: true
+ owner: ${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_OWNER }}
+ repo: ${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_REPO }}
+ token: ${{ secrets.RELEASE_TOKEN }}
flatpak_release:
uses: ./.github/workflows/flatpak.yml
needs: release
with:
ryujinx_version: "1.1.${{ github.run_number }}"
- secrets: inherit
\ No newline at end of file
+ secrets: inherit
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
new file mode 100644
index 000000000..366eb8435
--- /dev/null
+++ b/CONTRIBUTING.md
@@ -0,0 +1,147 @@
+# Contribution to Ryujinx
+
+You can contribute to Ryujinx with PRs, testing of PRs and issues. Contributing code and other implementations is greatly appreciated alongside simply filing issues for problems you encounter.
+Please read the entire document before continuing as it can potentially save everyone involved a significant amount of time.
+
+# Quick Links
+
+* [Code Style Documentation](docs/coding-guidelines/coding-style.md)
+* [Pull Request Guidelines](docs/workflow/pr-guide.md)
+
+## Reporting Issues
+
+We always welcome bug reports, feature proposals and overall feedback. Here are a few tips on how you can make reporting your issue as effective as possible.
+
+### Identify Where to Report
+
+The Ryujinx codebase is distributed across multiple repositories in the [Ryujinx organization](https://github.com/Ryujinx). Depending on the feedback you might want to file the issue on a different repo. Here are a few common repos:
+
+* [Ryujinx/Ryujinx](https://github.com/Ryujinx/Ryujinx) Ryujinx core project files.
+* [Ryujinx/Ryujinx-Games-List](https://github.com/Ryujinx/Ryujinx-Games-List) Ryujinx game compatibility list.
+* [Ryujinx/Ryujinx-Website](https://github.com/Ryujinx/Ryujinx-Website) Ryujinx website source code.
+* [Ryujinx/Ryujinx-Ldn-Website](https://github.com/Ryujinx/Ryujinx-Ldn-Website) Ryujinx LDN website source code.
+
+### Finding Existing Issues
+
+Before filing a new issue, please search our [open issues](https://github.com/Ryujinx/Ryujinx/issues) to check if it already exists.
+
+If you do find an existing issue, please include your own feedback in the discussion. Do consider upvoting (👍 reaction) the original post, as this helps us prioritize popular issues in our backlog.
+
+### Writing a Good Feature Request
+
+Please review any feature requests already opened to both check it has not already been suggested, and to familiarize yourself with the format. When ready to submit a proposal, please use the [Feature Request issue template](https://github.com/Ryujinx/Ryujinx/issues/new?assignees=&labels=&projects=&template=feature_request.yml&title=%5BFeature+Request%5D).
+
+### Writing a Good Bug Report
+
+Good bug reports make it easier for maintainers to verify and root cause the underlying problem. The better a bug report, the faster the problem will be resolved.
+Ideally, a bug report should contain the following information:
+
+* A high-level description of the problem.
+* A _minimal reproduction_, i.e. the smallest time commitment/configuration required to reproduce the wrong behavior. This can be in the form of a small homebrew application, or by providing a save file and reproduction steps for a specific game.
+* A description of the _expected behavior_, contrasted with the _actual behavior_ observed.
+* Information on the environment: OS/distro, CPU, GPU (including driver), RAM etc.
+* A Ryujinx log file of the run instance where the issue occurred. Log files can be found in `[Executable Folder]/Logs` and are named chronologically.
+* Additional information, e.g. is it a regression from previous versions? Are there any known workarounds?
+
+When ready to submit a bug report, please use the [Bug Report issue template](https://github.com/Ryujinx/Ryujinx/issues/new?assignees=&labels=bug&projects=&template=bug_report.yml&title=%5BBug%5D).
+
+## Contributing Changes
+
+Project maintainers will merge changes that both improve the project and meet our standards for code quality.
+
+The [Pull Request Guide](docs/workflow/pr-guide.md) and [License](https://github.com/Ryujinx/Ryujinx/blob/master/LICENSE.txt) docs define additional guidance.
+
+### DOs and DON'Ts
+
+Please do:
+
+* **DO** follow our [coding style](docs/coding-guidelines/coding-style.md) (C# code-specific).
+* **DO** give priority to the current style of the project or file you're changing even if it diverges from the general guidelines.
+* **DO** keep the discussions focused. When a new or related topic comes up
+ it's often better to create new issue than to side track the discussion.
+* **DO** clearly state on an issue that you are going to take on implementing it.
+* **DO** blog and tweet (or whatever) about your contributions, frequently!
+
+Please do not:
+
+* **DON'T** make PRs for style changes.
+* **DON'T** surprise us with big pull requests. Instead, file an issue and talk with us on Discord to start
+ a discussion so we can agree on a direction before you invest a large amount
+ of time.
+* **DON'T** commit code that you didn't write. If you find code that you think is a good fit to add to Ryujinx, file an issue or talk to us on Discord to start a discussion before proceeding.
+* **DON'T** submit PRs that alter licensing related files or headers. If you believe there's a problem with them, file an issue and we'll be happy to discuss it.
+
+### Suggested Workflow
+
+We use and recommend the following workflow:
+
+1. Create or find an issue for your work.
+ - You can skip this step for trivial changes.
+ - Get agreement from the team and the community that your proposed change is a good one if it is of significant size or changes core functionality.
+ - Clearly state that you are going to take on implementing it, if that's the case. You can request that the issue be assigned to you. Note: The issue filer and the implementer don't have to be the same person.
+2. Create a personal fork of the repository on GitHub (if you don't already have one).
+3. In your fork, create a branch off of main (`git checkout -b mybranch`).
+ - Branches are useful since they isolate your changes from incoming changes from upstream. They also enable you to create multiple PRs from the same fork.
+4. Make and commit your changes to your branch.
+ - [Build Instructions](https://github.com/Ryujinx/Ryujinx#building) explains how to build and test.
+ - Commit messages should be clear statements of action and intent.
+6. Build the repository with your changes.
+ - Make sure that the builds are clean.
+ - Make sure that `dotnet format` has been run and any corrections tested and committed.
+7. Create a pull request (PR) against the Ryujinx/Ryujinx repository's **main** branch.
+ - State in the description what issue or improvement your change is addressing.
+ - Check if all the Continuous Integration checks are passing. Refer to [Actions](https://github.com/Ryujinx/Ryujinx/actions) to check for outstanding errors.
+8. Wait for feedback or approval of your changes from the [core development team](https://github.com/orgs/Ryujinx/teams/developers)
+ - Details about the pull request [review procedure](docs/workflow/ci/pr-guide.md).
+9. When the team members have signed off, and all checks are green, your PR will be merged.
+ - The next official build will automatically include your change.
+ - You can delete the branch you used for making the change.
+
+### Good First Issues
+
+The team marks the most straightforward issues as [good first issues](https://github.com/Ryujinx/Ryujinx/issues?q=is%3Aopen+is%3Aissue+label%3A%22good+first+issue%22). This set of issues is the place to start if you are interested in contributing but new to the codebase.
+
+### Commit Messages
+
+Please format commit messages as follows (based on [A Note About Git Commit Messages](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html)):
+
+```
+Summarize change in 50 characters or less
+
+Provide more detail after the first line. Leave one blank line below the
+summary and wrap all lines at 72 characters or less.
+
+If the change fixes an issue, leave another blank line after the final
+paragraph and indicate which issue is fixed in the specific format
+below.
+
+Fix #42
+```
+
+Also do your best to factor commits appropriately, not too large with unrelated things in the same commit, and not too small with the same small change applied N times in N different commits.
+
+### PR - CI Process
+
+The [Ryujinx continuous integration](https://github.com/Ryujinx/Ryujinx/actions) (CI) system will automatically perform the required builds and run tests (including the ones you are expected to run) for PRs. Builds and test runs must be clean or have bugs properly filed against flaky/unexpected failures that are unrelated to your change.
+
+If the CI build fails for any reason, the PR actions tab should be consulted for further information on the failure. There are a few usual suspects for such a failure:
+* `dotnet format` has not been run on the PR and has outstanding stylistic issues.
+* There is an error within the PR that fails a test or errors the compiler.
+* Random failure of the workflow can occasionally result in a CI failure. In this scenario a maintainer will manually restart the job.
+
+### PR Feedback
+
+Ryujinx team and community members will provide feedback on your change. Community feedback is highly valued. You may see the absence of team feedback if the community has already provided good review feedback.
+
+Two Ryujinx team members must review and approve every PR prior to merge. They will often reply with "LGTM, see nit". That means that the PR will be merged once the feedback is resolved. "LGTM" == "looks good to me".
+
+There are lots of thoughts and [approaches](https://github.com/antlr/antlr4-cpp/blob/master/CONTRIBUTING.md#emoji) for how to efficiently discuss changes. It is best to be clear and explicit with your feedback. Please be patient with people who might not understand the finer details about your approach to feedback.
+
+#### Copying Changes from Other Projects
+
+Ryujinx uses some implementations and frameworks from other projects. The following rules must be followed for PRs that include changes from another project:
+
+- The license of the file is [permissive](https://en.wikipedia.org/wiki/Permissive_free_software_licence).
+- The license of the file is left in-tact.
+- The contribution is correctly attributed in the [3rd party notices](https://github.com/Ryujinx/Ryujinx/blob/master/distribution/legal/THIRDPARTY.md) file in the repository, as needed.
+
diff --git a/Directory.Packages.props b/Directory.Packages.props
index 4759c9ba5..c163cb0bf 100644
--- a/Directory.Packages.props
+++ b/Directory.Packages.props
@@ -3,38 +3,41 @@
true
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-
-
-
+
+
+
-
-
+
+
-
-
+
+
+
+
-
-
-
-
+
+
+
+
-
+
+
@@ -43,11 +46,9 @@
-
-
-
-
+
+
+
-
\ No newline at end of file
diff --git a/README.md b/README.md
index 7021abc45..b2f95cc1f 100644
--- a/README.md
+++ b/README.md
@@ -68,7 +68,7 @@ The latest automatic build for Windows, macOS, and Linux can be found on the [Of
If you wish to build the emulator yourself, follow these steps:
### Step 1
-Install the X64 version of [.NET 7.0 (or higher) SDK](https://dotnet.microsoft.com/download/dotnet/7.0).
+Install the X64 version of [.NET 8.0 (or higher) SDK](https://dotnet.microsoft.com/download/dotnet/8.0).
### Step 2
Either use `git clone https://github.com/Ryujinx/Ryujinx` on the command line to clone the repository or use Code --> Download zip button to get the files.
@@ -141,3 +141,5 @@ See [LICENSE.txt](LICENSE.txt) and [THIRDPARTY.md](distribution/legal/THIRDPARTY
- [LibHac](https://github.com/Thealexbarney/LibHac) is used for our file-system.
- [AmiiboAPI](https://www.amiiboapi.com) is used in our Amiibo emulation.
+- [ldn_mitm](https://github.com/spacemeowx2/ldn_mitm) is used for one of our available multiplayer modes.
+- [ShellLink](https://github.com/securifybv/ShellLink) is used for Windows shortcut generation.
diff --git a/Ryujinx.sln b/Ryujinx.sln
index f9b28c1ba..bb196cabc 100644
--- a/Ryujinx.sln
+++ b/Ryujinx.sln
@@ -39,7 +39,7 @@ Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Solution Items", "Solution
EndProject
Project("{9A19103F-16F7-4668-BE54-9A1E7A4F7556}") = "Ryujinx.Memory", "src\Ryujinx.Memory\Ryujinx.Memory.csproj", "{A5E6C691-9E22-4263-8F40-42F002CE66BE}"
EndProject
-Project("{9A19103F-16F7-4668-BE54-9A1E7A4F7556}") = "Ryujinx.Memory.Tests", "src\Ryujinx.Tests.Memory\Ryujinx.Tests.Memory.csproj", "{D1CC5322-7325-4F6B-9625-194B30BE1296}"
+Project("{9A19103F-16F7-4668-BE54-9A1E7A4F7556}") = "Ryujinx.Tests.Memory", "src\Ryujinx.Tests.Memory\Ryujinx.Tests.Memory.csproj", "{D1CC5322-7325-4F6B-9625-194B30BE1296}"
EndProject
Project("{9A19103F-16F7-4668-BE54-9A1E7A4F7556}") = "Ryujinx.Cpu", "src\Ryujinx.Cpu\Ryujinx.Cpu.csproj", "{3DF35E3D-D844-4399-A9A1-A9E923264C17}"
EndProject
@@ -256,4 +256,4 @@ Global
GlobalSection(ExtensibilityGlobals) = postSolution
SolutionGuid = {110169B3-3328-4730-8AB0-BA05BEF75C1A}
EndGlobalSection
-EndGlobal
\ No newline at end of file
+EndGlobal
diff --git a/distribution/legal/THIRDPARTY.md b/distribution/legal/THIRDPARTY.md
index 4cc8b7a45..5caa03771 100644
--- a/distribution/legal/THIRDPARTY.md
+++ b/distribution/legal/THIRDPARTY.md
@@ -681,4 +681,33 @@
END OF TERMS AND CONDITIONS
```
-
\ No newline at end of file
+
+
+# ShellLink (MIT)
+
+ See License
+
+ ```
+ MIT License
+
+ Copyright (c) 2017 Yorick Koster, Securify B.V.
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in all
+ copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ SOFTWARE.
+ ```
+
diff --git a/distribution/linux/Ryujinx.desktop b/distribution/linux/Ryujinx.desktop
index 19cc5d6cc..a4550d104 100644
--- a/distribution/linux/Ryujinx.desktop
+++ b/distribution/linux/Ryujinx.desktop
@@ -3,8 +3,8 @@ Version=1.0
Name=Ryujinx
Type=Application
Icon=Ryujinx
-Exec=env DOTNET_EnableAlternateStackCheck=1 Ryujinx %f
-Comment=A Nintendo Switch Emulator
+Exec=Ryujinx.sh %f
+Comment=Plays Nintendo Switch applications
GenericName=Nintendo Switch Emulator
Terminal=false
Categories=Game;Emulator;
diff --git a/distribution/linux/Ryujinx.sh b/distribution/linux/Ryujinx.sh
index ccb8d65e1..f356cad01 100644
--- a/distribution/linux/Ryujinx.sh
+++ b/distribution/linux/Ryujinx.sh
@@ -1,6 +1,6 @@
#!/bin/sh
-SCRIPT_DIR=$(dirname $(realpath $0))
+SCRIPT_DIR=$(dirname "$(realpath "$0")")
RYUJINX_BIN="Ryujinx"
if [ -f "$SCRIPT_DIR/Ryujinx.Ava" ]; then
@@ -11,4 +11,10 @@ if [ -f "$SCRIPT_DIR/Ryujinx.Headless.SDL2" ]; then
RYUJINX_BIN="Ryujinx.Headless.SDL2"
fi
-env DOTNET_EnableAlternateStackCheck=1 "$SCRIPT_DIR/$RYUJINX_BIN" "$@"
+COMMAND="env DOTNET_EnableAlternateStackCheck=1"
+
+if command -v gamemoderun > /dev/null 2>&1; then
+ COMMAND="$COMMAND gamemoderun"
+fi
+
+$COMMAND "$SCRIPT_DIR/$RYUJINX_BIN" "$@"
\ No newline at end of file
diff --git a/distribution/linux/shortcut-template.desktop b/distribution/linux/shortcut-template.desktop
new file mode 100644
index 000000000..6bee0f8d1
--- /dev/null
+++ b/distribution/linux/shortcut-template.desktop
@@ -0,0 +1,13 @@
+[Desktop Entry]
+Version=1.0
+Name={0}
+Type=Application
+Icon={1}
+Exec={2} %f
+Comment=Nintendo Switch application
+GenericName=Nintendo Switch Emulator
+Terminal=false
+Categories=Game;Emulator;
+Keywords=Switch;Nintendo;Emulator;
+StartupWMClass=Ryujinx
+PrefersNonDefaultGPU=true
diff --git a/distribution/macos/Info.plist b/distribution/macos/Info.plist
index 6c3f7717c..53929f95e 100644
--- a/distribution/macos/Info.plist
+++ b/distribution/macos/Info.plist
@@ -10,14 +10,25 @@
Ryujinx
CFBundleIconFile
Ryujinx.icns
- CFBundleTypeExtensions
-
- nca
- nro
- nso
- nsp
- xci
-
+ CFBundleDocumentTypes
+
+
+ CFBundleTypeExtensions
+
+ nca
+ nro
+ nso
+ nsp
+ xci
+
+ CFBundleTypeName
+ Nintendo Switch File
+ CFBundleTypeRole
+ Viewer
+ LSHandlerRank
+ Default
+
+
CFBundleIdentifier
org.ryujinx.Ryujinx
CFBundleInfoDictionaryVersion
@@ -39,10 +50,120 @@
CSResourcesFileMapped
NSHumanReadableCopyright
- Copyright © 2018 - 2022 Ryujinx Team and Contributors.
+ Copyright © 2018 - 2023 Ryujinx Team and Contributors.
LSApplicationCategoryType
public.app-category.games
LSMinimumSystemVersion
- 11.0
+ 12.0
+ UTExportedTypeDeclarations
+
+
+ UTTypeDescription
+ Extensible Application Markup Language
+ UTTypeConformsTo
+
+ public.xml
+
+ UTTypeIdentifier
+ com.ryujinx.xaml
+ UTTypeTagSpecification
+
+ public.filename-extension
+
+ xaml
+
+
+
+
+ UTTypeDescription
+ Nintendo Submission Package
+ UTTypeConformsTo
+
+ public.data
+
+ UTTypeIdentifier
+ com.ryujinx.nsp
+ UTTypeTagSpecification
+
+ public.filename-extension
+
+ nsp
+
+
+
+
+ UTTypeDescription
+ Nintendo Switch Cartridge
+ UTTypeConformsTo
+
+ public.data
+
+ UTTypeIdentifier
+ com.ryujinx.xci
+ UTTypeTagSpecification
+
+ public.filename-extension
+
+ xci
+
+
+
+
+ UTTypeDescription
+ Nintendo Content Archive
+ UTTypeConformsTo
+
+ public.data
+
+ UTTypeIdentifier
+ com.ryujinx.nca
+ UTTypeTagSpecification
+
+ public.filename-extension
+
+ nca
+
+
+
+
+ UTTypeDescription
+ Nintendo Relocatable Object
+ UTTypeConformsTo
+
+ public.data
+
+ UTTypeIdentifier
+ com.ryujinx.nro
+ UTTypeTagSpecification
+
+ public.filename-extension
+
+ nro
+
+
+
+
+ UTTypeDescription
+ Nintendo Shared Object
+ UTTypeConformsTo
+
+ public.data
+
+ UTTypeIdentifier
+ com.ryujinx.nso
+ UTTypeTagSpecification
+
+ public.filename-extension
+
+ nso
+
+
+
+
+ LSEnvironment
+
+ DOTNET_DefaultStackSize
+ 200000
+
diff --git a/distribution/macos/create_macos_release.sh b/distribution/macos/create_macos_build_ava.sh
similarity index 69%
rename from distribution/macos/create_macos_release.sh
rename to distribution/macos/create_macos_build_ava.sh
index 59eb1efd2..80594a40a 100755
--- a/distribution/macos/create_macos_release.sh
+++ b/distribution/macos/create_macos_build_ava.sh
@@ -2,8 +2,8 @@
set -e
-if [ "$#" -ne 6 ]; then
- echo "usage "
+if [ "$#" -lt 7 ]; then
+ echo "usage "
exit 1
fi
@@ -17,8 +17,16 @@ OUTPUT_DIRECTORY=$(readlink -f "$3")
ENTITLEMENTS_FILE_PATH=$(readlink -f "$4")
VERSION=$5
SOURCE_REVISION_ID=$6
+CONFIGURATION=$7
+EXTRA_ARGS=$8
+
+if [ "$VERSION" == "1.1.0" ];
+then
+ RELEASE_TAR_FILE_NAME=test-ava-ryujinx-$CONFIGURATION-$VERSION+$SOURCE_REVISION_ID-macos_universal.app.tar
+else
+ RELEASE_TAR_FILE_NAME=test-ava-ryujinx-$VERSION-macos_universal.app.tar
+fi
-RELEASE_TAR_FILE_NAME=Ryujinx-$VERSION-macos_universal.app.tar
ARM64_APP_BUNDLE="$TEMP_DIRECTORY/output_arm64/Ryujinx.app"
X64_APP_BUNDLE="$TEMP_DIRECTORY/output_x64/Ryujinx.app"
UNIVERSAL_APP_BUNDLE="$OUTPUT_DIRECTORY/Ryujinx.app"
@@ -27,12 +35,12 @@ EXECUTABLE_SUB_PATH=Contents/MacOS/Ryujinx
rm -rf "$TEMP_DIRECTORY"
mkdir -p "$TEMP_DIRECTORY"
-DOTNET_COMMON_ARGS="-p:DebugType=embedded -p:Version=$VERSION -p:SourceRevisionId=$SOURCE_REVISION_ID --self-contained true"
+DOTNET_COMMON_ARGS=(-p:DebugType=embedded -p:Version="$VERSION" -p:SourceRevisionId="$SOURCE_REVISION_ID" --self-contained true $EXTRA_ARGS)
dotnet restore
-dotnet build -c Release src/Ryujinx.Ava
-dotnet publish -c Release -r osx-arm64 -o "$TEMP_DIRECTORY/publish_arm64" $DOTNET_COMMON_ARGS src/Ryujinx.Ava
-dotnet publish -c Release -r osx-x64 -o "$TEMP_DIRECTORY/publish_x64" $DOTNET_COMMON_ARGS src/Ryujinx.Ava
+dotnet build -c "$CONFIGURATION" src/Ryujinx.Ava
+dotnet publish -c "$CONFIGURATION" -r osx-arm64 -o "$TEMP_DIRECTORY/publish_arm64" "${DOTNET_COMMON_ARGS[@]}" src/Ryujinx.Ava
+dotnet publish -c "$CONFIGURATION" -r osx-x64 -o "$TEMP_DIRECTORY/publish_x64" "${DOTNET_COMMON_ARGS[@]}" src/Ryujinx.Ava
# Get rid of the support library for ARMeilleure for x64 (that's only for arm64)
rm -rf "$TEMP_DIRECTORY/publish_x64/libarmeilleure-jitsupport.dylib"
@@ -68,7 +76,7 @@ else
LIPO=lipo
fi
-# Make it the executable universal
+# Make the executable universal
$LIPO "$ARM64_APP_BUNDLE/$EXECUTABLE_SUB_PATH" "$X64_APP_BUNDLE/$EXECUTABLE_SUB_PATH" -output "$UNIVERSAL_APP_BUNDLE/$EXECUTABLE_SUB_PATH" -create
# Patch up the Info.plist to have appropriate version
@@ -87,19 +95,19 @@ then
# NOTE: Currently require https://github.com/indygreg/apple-platform-rs/pull/44 to work on other OSes.
# cargo install --git "https://github.com/marysaka/apple-platform-rs" --branch "fix/adhoc-app-bundle" apple-codesign --bin "rcodesign"
- echo "Usign rcodesign for ad-hoc signing"
+ echo "Using rcodesign for ad-hoc signing"
rcodesign sign --entitlements-xml-path "$ENTITLEMENTS_FILE_PATH" "$UNIVERSAL_APP_BUNDLE"
else
- echo "Usign codesign for ad-hoc signing"
+ echo "Using codesign for ad-hoc signing"
codesign --entitlements "$ENTITLEMENTS_FILE_PATH" -f --deep -s - "$UNIVERSAL_APP_BUNDLE"
fi
echo "Creating archive"
pushd "$OUTPUT_DIRECTORY"
-tar --exclude "Ryujinx.app/Contents/MacOS/Ryujinx" -cvf $RELEASE_TAR_FILE_NAME Ryujinx.app 1> /dev/null
-python3 "$BASE_DIR/distribution/misc/add_tar_exec.py" $RELEASE_TAR_FILE_NAME "Ryujinx.app/Contents/MacOS/Ryujinx" "Ryujinx.app/Contents/MacOS/Ryujinx"
-gzip -9 < $RELEASE_TAR_FILE_NAME > $RELEASE_TAR_FILE_NAME.gz
-rm $RELEASE_TAR_FILE_NAME
+tar --exclude "Ryujinx.app/Contents/MacOS/Ryujinx" -cvf "$RELEASE_TAR_FILE_NAME" Ryujinx.app 1> /dev/null
+python3 "$BASE_DIR/distribution/misc/add_tar_exec.py" "$RELEASE_TAR_FILE_NAME" "Ryujinx.app/Contents/MacOS/Ryujinx" "Ryujinx.app/Contents/MacOS/Ryujinx"
+gzip -9 < "$RELEASE_TAR_FILE_NAME" > "$RELEASE_TAR_FILE_NAME.gz"
+rm "$RELEASE_TAR_FILE_NAME"
popd
echo "Done"
\ No newline at end of file
diff --git a/distribution/macos/create_macos_build_headless.sh b/distribution/macos/create_macos_build_headless.sh
new file mode 100755
index 000000000..a439aef45
--- /dev/null
+++ b/distribution/macos/create_macos_build_headless.sh
@@ -0,0 +1,111 @@
+#!/bin/bash
+
+set -e
+
+if [ "$#" -lt 7 ]; then
+ echo "usage "
+ exit 1
+fi
+
+mkdir -p "$1"
+mkdir -p "$2"
+mkdir -p "$3"
+
+BASE_DIR=$(readlink -f "$1")
+TEMP_DIRECTORY=$(readlink -f "$2")
+OUTPUT_DIRECTORY=$(readlink -f "$3")
+ENTITLEMENTS_FILE_PATH=$(readlink -f "$4")
+VERSION=$5
+SOURCE_REVISION_ID=$6
+CONFIGURATION=$7
+EXTRA_ARGS=$8
+
+if [ "$VERSION" == "1.1.0" ];
+then
+ RELEASE_TAR_FILE_NAME=sdl2-ryujinx-headless-$CONFIGURATION-$VERSION+$SOURCE_REVISION_ID-macos_universal.tar
+else
+ RELEASE_TAR_FILE_NAME=sdl2-ryujinx-headless-$VERSION-macos_universal.tar
+fi
+
+ARM64_OUTPUT="$TEMP_DIRECTORY/publish_arm64"
+X64_OUTPUT="$TEMP_DIRECTORY/publish_x64"
+UNIVERSAL_OUTPUT="$OUTPUT_DIRECTORY/publish"
+EXECUTABLE_SUB_PATH=Ryujinx.Headless.SDL2
+
+rm -rf "$TEMP_DIRECTORY"
+mkdir -p "$TEMP_DIRECTORY"
+
+DOTNET_COMMON_ARGS=(-p:DebugType=embedded -p:Version="$VERSION" -p:SourceRevisionId="$SOURCE_REVISION_ID" --self-contained true $EXTRA_ARGS)
+
+dotnet restore
+dotnet build -c "$CONFIGURATION" src/Ryujinx.Headless.SDL2
+dotnet publish -c "$CONFIGURATION" -r osx-arm64 -o "$TEMP_DIRECTORY/publish_arm64" "${DOTNET_COMMON_ARGS[@]}" src/Ryujinx.Headless.SDL2
+dotnet publish -c "$CONFIGURATION" -r osx-x64 -o "$TEMP_DIRECTORY/publish_x64" "${DOTNET_COMMON_ARGS[@]}" src/Ryujinx.Headless.SDL2
+
+# Get rid of the support library for ARMeilleure for x64 (that's only for arm64)
+rm -rf "$TEMP_DIRECTORY/publish_x64/libarmeilleure-jitsupport.dylib"
+
+# Get rid of libsoundio from arm64 builds as we don't have a arm64 variant
+# TODO: remove this once done
+rm -rf "$TEMP_DIRECTORY/publish_arm64/libsoundio.dylib"
+
+rm -rf "$OUTPUT_DIRECTORY"
+mkdir -p "$OUTPUT_DIRECTORY"
+
+# Let's copy one of the two different outputs and remove the executable
+cp -R "$ARM64_OUTPUT/" "$UNIVERSAL_OUTPUT"
+rm "$UNIVERSAL_OUTPUT/$EXECUTABLE_SUB_PATH"
+
+# Make it libraries universal
+python3 "$BASE_DIR/distribution/macos/construct_universal_dylib.py" "$ARM64_OUTPUT" "$X64_OUTPUT" "$UNIVERSAL_OUTPUT" "**/*.dylib"
+
+if ! [ -x "$(command -v lipo)" ];
+then
+ if ! [ -x "$(command -v llvm-lipo-14)" ];
+ then
+ LIPO=llvm-lipo
+ else
+ LIPO=llvm-lipo-14
+ fi
+else
+ LIPO=lipo
+fi
+
+# Make the executable universal
+$LIPO "$ARM64_OUTPUT/$EXECUTABLE_SUB_PATH" "$X64_OUTPUT/$EXECUTABLE_SUB_PATH" -output "$UNIVERSAL_OUTPUT/$EXECUTABLE_SUB_PATH" -create
+
+# Now sign it
+if ! [ -x "$(command -v codesign)" ];
+then
+ if ! [ -x "$(command -v rcodesign)" ];
+ then
+ echo "Cannot find rcodesign on your system, please install rcodesign."
+ exit 1
+ fi
+
+ # NOTE: Currently require https://github.com/indygreg/apple-platform-rs/pull/44 to work on other OSes.
+ # cargo install --git "https://github.com/marysaka/apple-platform-rs" --branch "fix/adhoc-app-bundle" apple-codesign --bin "rcodesign"
+ echo "Using rcodesign for ad-hoc signing"
+ for FILE in "$UNIVERSAL_OUTPUT"/*; do
+ if [[ $(file "$FILE") == *"Mach-O"* ]]; then
+ rcodesign sign --entitlements-xml-path "$ENTITLEMENTS_FILE_PATH" "$FILE"
+ fi
+ done
+else
+ echo "Using codesign for ad-hoc signing"
+ for FILE in "$UNIVERSAL_OUTPUT"/*; do
+ if [[ $(file "$FILE") == *"Mach-O"* ]]; then
+ codesign --entitlements "$ENTITLEMENTS_FILE_PATH" -f --deep -s - "$FILE"
+ fi
+ done
+fi
+
+echo "Creating archive"
+pushd "$OUTPUT_DIRECTORY"
+tar --exclude "publish/Ryujinx.Headless.SDL2" -cvf "$RELEASE_TAR_FILE_NAME" publish 1> /dev/null
+python3 "$BASE_DIR/distribution/misc/add_tar_exec.py" "$RELEASE_TAR_FILE_NAME" "publish/Ryujinx.Headless.SDL2" "publish/Ryujinx.Headless.SDL2"
+gzip -9 < "$RELEASE_TAR_FILE_NAME" > "$RELEASE_TAR_FILE_NAME.gz"
+rm "$RELEASE_TAR_FILE_NAME"
+popd
+
+echo "Done"
\ No newline at end of file
diff --git a/distribution/macos/shortcut-launch-script.sh b/distribution/macos/shortcut-launch-script.sh
new file mode 100644
index 000000000..784d780aa
--- /dev/null
+++ b/distribution/macos/shortcut-launch-script.sh
@@ -0,0 +1,8 @@
+#!/bin/sh
+launch_arch="$(uname -m)"
+if [ "$(sysctl -in sysctl.proc_translated)" = "1" ]
+then
+ launch_arch="arm64"
+fi
+
+arch -$launch_arch {0} {1}
diff --git a/distribution/macos/shortcut-template.plist b/distribution/macos/shortcut-template.plist
new file mode 100644
index 000000000..27a9e46a9
--- /dev/null
+++ b/distribution/macos/shortcut-template.plist
@@ -0,0 +1,35 @@
+
+
+
+
+ CFBundleDevelopmentRegion
+ English
+ CFBundleExecutable
+ {0}
+ CFBundleGetInfoString
+ {1}
+ CFBundleIconFile
+ {2}
+ CFBundleInfoDictionaryVersion
+ 6.0
+ CFBundleVersion
+ 1.0
+ NSHighResolutionCapable
+
+ CSResourcesFileMapped
+
+ NSHumanReadableCopyright
+ Copyright © 2018 - 2023 Ryujinx Team and Contributors.
+ LSApplicationCategoryType
+ public.app-category.games
+ LSMinimumSystemVersion
+ 11.0
+ UIPrerenderedIcon
+
+ LSEnvironment
+
+ DOTNET_DefaultStackSize
+ 200000
+
+
+
diff --git a/distribution/macos/updater.sh b/distribution/macos/updater.sh
index b60ac34df..12e4c3aa1 100755
--- a/distribution/macos/updater.sh
+++ b/distribution/macos/updater.sh
@@ -5,7 +5,7 @@ set -e
INSTALL_DIRECTORY=$1
NEW_APP_DIRECTORY=$2
APP_PID=$3
-APP_ARGUMENTS="${@:4}"
+APP_ARGUMENTS=("${@:4}")
error_handler() {
local lineno="$1"
@@ -27,13 +27,31 @@ error_handler() {
trap 'error_handler ${LINENO}' ERR
-# Wait for Ryujinx to exit
-# NOTE: in case no fds are open, lsof could be returning with a process still living.
-# We wait 1s and assume the process stopped after that
-lsof -p $APP_PID +r 1 &>/dev/null
+# Wait for Ryujinx to exit.
+# If the main process is still acitve, we wait for 1 second and check it again.
+# After the fifth time checking, this script exits with status 1.
+
+attempt=0
+while true; do
+ if lsof -p "$APP_PID" +r 1 &>/dev/null || ps -p "$APP_PID" &>/dev/null; then
+ if [ "$attempt" -eq 4 ]; then
+ exit 1
+ fi
+ sleep 1
+ else
+ break
+ fi
+ (( attempt++ ))
+done
+
sleep 1
# Now replace and reopen.
rm -rf "$INSTALL_DIRECTORY"
mv "$NEW_APP_DIRECTORY" "$INSTALL_DIRECTORY"
-open -a "$INSTALL_DIRECTORY" --args "$APP_ARGUMENTS"
+
+if [ "$#" -le 3 ]; then
+ open -a "$INSTALL_DIRECTORY"
+else
+ open -a "$INSTALL_DIRECTORY" --args "${APP_ARGUMENTS[@]}"
+fi
\ No newline at end of file
diff --git a/docs/README.md b/docs/README.md
new file mode 100644
index 000000000..2213086f6
--- /dev/null
+++ b/docs/README.md
@@ -0,0 +1,40 @@
+# Documents Index
+
+This repo includes several documents that explain both high-level and low-level concepts about Ryujinx and its functions. These are very useful for contributors, to get context that can be very difficult to acquire from just reading code.
+
+Intro to Ryujinx
+==================
+
+Ryujinx is an open-source Nintendo Switch emulator, created by gdkchan, written in C#.
+* The CPU emulator, ARMeilleure, emulates an ARMv8 CPU and currently has support for most 64-bit ARMv8 and some of the ARMv7 (and older) instructions.
+* The GPU emulator emulates the Switch's Maxwell GPU using either the OpenGL (version 4.5 minimum), Vulkan, or Metal (via MoltenVK) APIs through a custom build of OpenTK or Silk.NET respectively.
+* Audio output is entirely supported via C# wrappers for SDL2, with OpenAL & libsoundio as fallbacks.
+
+Getting Started
+===============
+
+- [Installing the .NET SDK](https://dotnet.microsoft.com/download)
+- [Official .NET Docs](https://docs.microsoft.com/dotnet/core/)
+
+Contributing (Building, testing, benchmarking, profiling, etc.)
+===============
+
+If you want to contribute a code change to this repo, start here.
+
+- [Contributor Guide](../CONTRIBUTING.md)
+
+Coding Guidelines
+=================
+
+- [C# coding style](coding-guidelines/coding-style.md)
+- [Service Implementation Guidelines - WIP](https://gist.github.com/gdkchan/84ba88cd50efbe58d1babfaa7cd7c455)
+
+Project Docs
+=================
+
+To be added. Many project files will contain basic XML docs for key functions and classes in the meantime.
+
+Other Information
+=================
+
+- N/A
diff --git a/docs/coding-guidelines/coding-style.md b/docs/coding-guidelines/coding-style.md
new file mode 100644
index 000000000..9c84055d6
--- /dev/null
+++ b/docs/coding-guidelines/coding-style.md
@@ -0,0 +1,116 @@
+# C# Coding Style
+
+The general rule we follow is "use Visual Studio defaults".
+Using an IDE that supports the `.editorconfig` standard will make this much simpler.
+
+1. We use [Allman style](http://en.wikipedia.org/wiki/Indent_style#Allman_style) braces, where each brace begins on a new line. A single line statement block can go without braces but the block must be properly indented on its own line and must not be nested in other statement blocks that use braces (See rule 18 for more details). One exception is that a `using` statement is permitted to be nested within another `using` statement by starting on the following line at the same indentation level, even if the nested `using` contains a controlled block.
+2. We use four spaces of indentation (no tabs).
+3. We use `_camelCase` for internal and private fields and use `readonly` where possible. Prefix internal and private instance fields with `_`, static fields with `s_` and thread static fields with `t_`. When used on static fields, `readonly` should come after `static` (e.g. `static readonly` not `readonly static`). Public fields should be used sparingly and should use PascalCasing with no prefix when used.
+4. We avoid `this.` unless absolutely necessary.
+5. We always specify the visibility, even if it's the default (e.g.
+ `private string _foo` not `string _foo`). Visibility should be the first modifier (e.g.
+ `public abstract` not `abstract public`).
+6. Namespace imports should be specified at the top of the file, *outside* of `namespace` declarations.
+7. Avoid more than one empty line at any time. For example, do not have two
+ blank lines between members of a type.
+8. Avoid spurious free spaces.
+ For example avoid `if (someVar == 0)...`, where the dots mark the spurious free spaces.
+ Consider enabling "View White Space (Ctrl+R, Ctrl+W)" or "Edit -> Advanced -> View White Space" if using Visual Studio to aid detection.
+9. If a file happens to differ in style from these guidelines (e.g. private members are named `m_member`
+ rather than `_member`), the existing style in that file takes precedence.
+10. We only use `var` when the type is explicitly named on the right-hand side, typically due to either `new` or an explicit cast, e.g. `var stream = new FileStream(...)` not `var stream = OpenStandardInput()`.
+ - Similarly, target-typed `new()` can only be used when the type is explicitly named on the left-hand side, in a variable definition statement or a field definition statement. e.g. `FileStream stream = new(...);`, but not `stream = new(...);` (where the type was specified on a previous line).
+11. We use language keywords instead of BCL types (e.g. `int, string, float` instead of `Int32, String, Single`, etc) for both type references as well as method calls (e.g. `int.Parse` instead of `Int32.Parse`). See issue [#13976](https://github.com/dotnet/runtime/issues/13976) for examples.
+12. We use PascalCasing to name all our constant local variables and fields. The only exception is for interop code where the constant value should exactly match the name and value of the code you are calling via interop.
+13. We use PascalCasing for all method names, including local functions.
+14. We use ```nameof(...)``` instead of ```"..."``` whenever possible and relevant.
+15. Fields should be specified at the top within type declarations.
+16. When including non-ASCII characters in the source code use Unicode escape sequences (\uXXXX) instead of literal characters. Literal non-ASCII characters occasionally get garbled by a tool or editor.
+17. When using labels (for goto), indent the label one less than the current indentation.
+18. When using a single-statement if, we follow these conventions:
+ - Never use single-line form (for example: `if (source == null) throw new ArgumentNullException("source");`)
+ - Using braces is always accepted, and required if any block of an `if`/`else if`/.../`else` compound statement uses braces or if a single statement body spans multiple lines.
+ - Braces may be omitted only if the body of *every* block associated with an `if`/`else if`/.../`else` compound statement is placed on a single line.
+19. Make all internal and private types static or sealed unless derivation from them is required. As with any implementation detail, they can be changed if/when derivation is required in the future.
+20. XML docs should be used when writing interfaces or when a class/method is deemed sufficient in scope or complexity.
+21. So-called [Magic Numbers](https://en.wikipedia.org/wiki/Magic_number_(programming)) should be defined as named constants before use (for example `for (int i = 56; i < 68; i++)` could read `for (int i = _currentAge; i < _retireAge; i++)`).
+ This may be ignored for trivial or syntactically common statements.
+
+An [EditorConfig](https://editorconfig.org "EditorConfig homepage") file (`.editorconfig`) has been provided at the root of the runtime repository, enabling C# auto-formatting conforming to the above guidelines.
+
+### Example File:
+
+``ShaderCache.cs:``
+
+```C#
+using Ryujinx.Common.Configuration;
+using Ryujinx.Common.Logging;
+using Ryujinx.Graphics.GAL;
+using Ryujinx.Graphics.Gpu.Engine.Threed;
+using Ryujinx.Graphics.Gpu.Engine.Types;
+using Ryujinx.Graphics.Gpu.Image;
+using Ryujinx.Graphics.Gpu.Memory;
+using Ryujinx.Graphics.Gpu.Shader.DiskCache;
+using Ryujinx.Graphics.Shader;
+using Ryujinx.Graphics.Shader.Translation;
+using System;
+using System.Collections.Generic;
+using System.IO;
+using System.Threading;
+
+namespace Ryujinx.Graphics.Gpu.Shader
+{
+ ///
+ /// Memory cache of shader code.
+ ///
+ class ShaderCache : IDisposable
+ {
+ ///
+ /// Default flags used on the shader translation process.
+ ///
+ public const TranslationFlags DefaultFlags = TranslationFlags.DebugMode;
+
+ private readonly struct TranslatedShader
+ {
+ public readonly CachedShaderStage Shader;
+ public readonly ShaderProgram Program;
+
+ public TranslatedShader(CachedShaderStage shader, ShaderProgram program)
+ {
+ Shader = shader;
+ Program = program;
+ }
+ }
+ ...
+
+ ///
+ /// Processes the queue of shaders that must save their binaries to the disk cache.
+ ///
+ public void ProcessShaderCacheQueue()
+ {
+ // Check to see if the binaries for previously compiled shaders are ready, and save them out.
+
+ while (_programsToSaveQueue.TryPeek(out ProgramToSave programToSave))
+ {
+ ProgramLinkStatus result = programToSave.HostProgram.CheckProgramLink(false);
+
+ if (result != ProgramLinkStatus.Incomplete)
+ {
+ if (result == ProgramLinkStatus.Success)
+ {
+ _cacheWriter.AddShader(programToSave.CachedProgram, programToSave.BinaryCode ?? programToSave.HostProgram.GetBinary());
+ }
+
+ _programsToSaveQueue.Dequeue();
+ }
+ else
+ {
+ break;
+ }
+ }
+ }
+ }
+}
+```
+
+For other languages, our current best guidance is consistency. When editing files, keep new code and changes consistent with the style in the files. For new files, it should conform to the style for that component. If there is a completely new component, anything that is reasonably broadly accepted is fine.
diff --git a/docs/workflow/pr-guide.md b/docs/workflow/pr-guide.md
new file mode 100644
index 000000000..cc2c5900b
--- /dev/null
+++ b/docs/workflow/pr-guide.md
@@ -0,0 +1,56 @@
+# Pull Request Guide
+
+## Contributing Rules
+
+All contributions to Ryujinx/Ryujinx repository are made via pull requests (PRs) rather than through direct commits. The pull requests are reviewed and merged by the maintainers after a review and at least two approvals from the core development team.
+
+To merge pull requests, you must have write permissions in the repository.
+
+## Quick Code Review Rules
+
+* Do not mix unrelated changes in one pull request. For example, a code style change should never be mixed with a bug fix.
+* All changes should follow the existing code style. You can read more about our code style at [docs/coding-guidelines](../coding-guidelines/coding-style.md).
+* Adding external dependencies is to be avoided unless not doing so would introduce _significant_ complexity. Any dependency addition should be justified and discussed before merge.
+* Use Draft pull requests for changes you are still working on but want early CI loop feedback. When you think your changes are ready for review, [change the status](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/changing-the-stage-of-a-pull-request) of your pull request.
+* Rebase your changes when required or directly requested. Changes should always be commited on top of the upstream branch, not the other way around.
+* If you are asked to make changes during the review process do them as a new commit.
+* Only resolve GitHub conversations with reviewers once they have been addressed with a commit, or via a mutual agreement.
+
+## Pull Request Ownership
+
+Every pull request will have automatically have labels and reviewers assigned. The label not only indicates the code segment which the change touches but also the area reviewers to be assigned.
+
+If during the code review process a merge conflict occurs, the PR author is responsible for its resolution. Help will be provided if necessary although GitHub makes this easier by allowing simple conflict resolution using the [conflict-editor](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/resolving-a-merge-conflict-on-github).
+
+## Pull Request Builds
+
+When submitting a PR to the `Ryujinx/Ryujinx` repository, various builds will run validating many areas to ensure we keep developer productivity and product quality high. These various workflows can be tracked in the [Actions](https://github.com/Ryujinx/Ryujinx/actions) tab of the repository. If the job continues to completion, the build artifacts will be uploaded and posted as a comment in the PR discussion.
+
+## Review Turnaround Times
+
+Ryujinx is a project that is maintained by volunteers on a completely free-time basis. As such we cannot guarantee any particular timeframe for pull request review and approval. Weeks to months are common for larger (>500 line) PRs but there are some additional best practises to avoid review purgatory.
+
+* Make the reviewers life easier wherever possible. Make use of descriptive commit names, code comments and XML docs where applicable.
+* If there is disagreement on feedback then always lean on the side of the development team and community over any personal opinion.
+* We're human. We miss things. We forget things. If there has been radio silence on your changes for a substantial period of time then do not hesitate to reach out directly either with something simple like "bump" on GitHub or a directly on Discord.
+
+To re-iterate, make the review as easy for us as possible, respond promptly and be comfortable to interact directly with us for anything else.
+
+## Merging Pull Requests
+
+Anyone with write access can merge a pull request manually when the following conditions have been met:
+
+* The PR has been approved by two reviewers and any other objections are addressed.
+ * You can request follow up reviews from the original reviewers if they requested changes.
+* The PR successfully builds and passes all tests in the Continuous Integration (CI) system. In case of failures, refer to the [Actions](https://github.com/Ryujinx/Ryujinx/actions) tab of your PR.
+
+Typically, PRs are merged as one commit (squash merges). It creates a simpler history than a Merge Commit. "Special circumstances" are rare, and typically mean that there are a series of cleanly separated changes that will be too hard to understand if squashed together, or for some reason we want to preserve the ability to dissect them.
+
+## Blocking Pull Request Merging
+
+If for whatever reason you would like to move your pull request back to an in-progress status to avoid merging it in the current form, you can turn the PR into a draft PR by selecting the option under the reviewers section. Alternatively, you can do that by adding [WIP] prefix to the pull request title.
+
+## Old Pull Request Policy
+
+From time to time we will review older PRs and check them for relevance. If we find the PR is inactive or no longer applies, we will close it. As the PR owner, you can simply reopen it if you feel your closed PR needs our attention.
+
diff --git a/global.json b/global.json
index 39ccef0d0..391ba3c2a 100644
--- a/global.json
+++ b/global.json
@@ -1,6 +1,6 @@
{
"sdk": {
- "version": "7.0.200",
+ "version": "8.0.100",
"rollForward": "latestFeature"
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/ARMeilleure.csproj b/src/ARMeilleure/ARMeilleure.csproj
index fa5551154..550e50c26 100644
--- a/src/ARMeilleure/ARMeilleure.csproj
+++ b/src/ARMeilleure/ARMeilleure.csproj
@@ -1,7 +1,7 @@
- net7.0
+ net8.0
true
diff --git a/src/ARMeilleure/Allocators.cs b/src/ARMeilleure/Allocators.cs
index deabf9a26..fba302657 100644
--- a/src/ARMeilleure/Allocators.cs
+++ b/src/ARMeilleure/Allocators.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Common;
+using ARMeilleure.Common;
using System;
using System.Runtime.CompilerServices;
@@ -23,10 +23,7 @@ static class Allocators
[MethodImpl(MethodImplOptions.AggressiveInlining)]
private static ArenaAllocator GetAllocator(ref ArenaAllocator alloc, uint pageSize, uint pageCount)
{
- if (alloc == null)
- {
- alloc = new ArenaAllocator(pageSize, pageCount);
- }
+ alloc ??= new ArenaAllocator(pageSize, pageCount);
return alloc;
}
diff --git a/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs b/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs
index fdd4d0241..00ffd1958 100644
--- a/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs
@@ -221,7 +221,7 @@ private static (Operand, Multiplier) GetIndexOp(ref Operand baseOp, OperandType
2 => Multiplier.x4,
3 => Multiplier.x8,
4 => Multiplier.x16,
- _ => Multiplier.x1
+ _ => Multiplier.x1,
};
baseOp = indexOnSrc2 ? src1 : src2;
diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs b/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs
index db27a8104..5db898591 100644
--- a/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs
@@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.Arm64
{
enum ArmCondition
{
- Eq = 0,
- Ne = 1,
+ Eq = 0,
+ Ne = 1,
GeUn = 2,
LtUn = 3,
- Mi = 4,
- Pl = 5,
- Vs = 6,
- Vc = 7,
+ Mi = 4,
+ Pl = 5,
+ Vs = 6,
+ Vc = 7,
GtUn = 8,
LeUn = 9,
- Ge = 10,
- Lt = 11,
- Gt = 12,
- Le = 13,
- Al = 14,
- Nv = 15
+ Ge = 10,
+ Lt = 11,
+ Gt = 12,
+ Le = 13,
+ Al = 14,
+ Nv = 15,
}
static class ComparisonArm64Extensions
@@ -29,6 +29,7 @@ public static ArmCondition ToArmCondition(this Comparison comp)
{
return comp switch
{
+#pragma warning disable IDE0055 // Disable formatting
Comparison.Equal => ArmCondition.Eq,
Comparison.NotEqual => ArmCondition.Ne,
Comparison.Greater => ArmCondition.Gt,
@@ -39,8 +40,9 @@ public static ArmCondition ToArmCondition(this Comparison comp)
Comparison.Less => ArmCondition.Lt,
Comparison.GreaterOrEqualUI => ArmCondition.GeUn,
Comparison.LessUI => ArmCondition.LtUn,
+#pragma warning restore IDE0055
- _ => throw new ArgumentException(null, nameof(comp))
+ _ => throw new ArgumentException(null, nameof(comp)),
};
}
}
diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs b/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs
index 062a6d0b7..20ccfd4ba 100644
--- a/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs
@@ -9,6 +9,6 @@ enum ArmExtensionType
Sxtb = 4,
Sxth = 5,
Sxtw = 6,
- Sxtx = 7
+ Sxtx = 7,
}
}
diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs b/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs
index d223a1464..f32407c43 100644
--- a/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs
@@ -6,6 +6,6 @@ enum ArmShiftType
Lsl = 0,
Lsr = 1,
Asr = 2,
- Ror = 3
+ Ror = 3,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs
index 0ec0be7cb..41684faf2 100644
--- a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs
@@ -188,7 +188,7 @@ public void Fmov(Operand rd, Operand rn, bool topHalf)
uint rmode = topHalf ? 1u << 19 : 0u;
uint ftype = rd.Type == OperandType.FP64 || rn.Type == OperandType.FP64 ? 1u << 22 : 0u;
- uint sf = rd.Type == OperandType.I64 || rn.Type == OperandType.I64 ? SfFlag : 0u;
+ uint sf = rd.Type == OperandType.I64 || rn.Type == OperandType.I64 ? SfFlag : 0u;
WriteUInt32(0x1e260000u | (opcode << 16) | rmode | ftype | sf | EncodeReg(rd) | (EncodeReg(rn) << 5));
}
@@ -992,7 +992,7 @@ private static uint GetLdpStpInstruction(uint intInst, uint vecInst, int imm, Op
{
OperandType.FP32 => 0,
OperandType.FP64 => 1,
- _ => 2
+ _ => 2,
};
instruction = vecInst | ((uint)opc << 30);
@@ -1124,10 +1124,11 @@ public static int GetScaleForType(OperandType type)
OperandType.FP32 => 2,
OperandType.FP64 => 3,
OperandType.V128 => 4,
- _ => throw new ArgumentException($"Invalid type {type}.")
+ _ => throw new ArgumentException($"Invalid type {type}."),
};
}
+#pragma warning disable IDE0051 // Remove unused private member
private void WriteInt16(short value)
{
WriteUInt16((ushort)value);
@@ -1142,6 +1143,7 @@ private void WriteByte(byte value)
{
_stream.WriteByte(value);
}
+#pragma warning restore IDE0051
private void WriteUInt16(ushort value)
{
diff --git a/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs b/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs
index fda8d7867..a487c2ed3 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs
@@ -93,4 +93,4 @@ public static int GetVecReturnRegister()
return 0;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs
index 8d1e597ba..1f0148d5e 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs
@@ -88,4 +88,4 @@ public static bool TryEncodeBitMask(ulong value, out int immN, out int immS, out
return true;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs
index 0dd5355f4..12ebabddd 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs
@@ -14,7 +14,7 @@ class CodeGenContext
private const int CbnzInstLength = 4;
private const int LdrLitInstLength = 4;
- private Stream _stream;
+ private readonly Stream _stream;
public int StreamOffset => (int)_stream.Length;
@@ -32,7 +32,7 @@ class CodeGenContext
private readonly Dictionary _visitedBlocks;
private readonly Dictionary> _pendingBranches;
- private struct ConstantPoolEntry
+ private readonly struct ConstantPoolEntry
{
public readonly int Offset;
public readonly Symbol Symbol;
@@ -58,7 +58,7 @@ public ConstantPoolEntry(int offset, Symbol symbol)
private readonly bool _relocatable;
- public CodeGenContext(AllocationResult allocResult, int maxCallArgs, int blocksCount, bool relocatable)
+ public CodeGenContext(AllocationResult allocResult, int maxCallArgs, bool relocatable)
{
_stream = MemoryStreamManager.Shared.GetStream();
@@ -93,10 +93,10 @@ public void EnterBlock(BasicBlock block)
if (_pendingBranches.TryGetValue(block, out var list))
{
- foreach (var tuple in list)
+ foreach ((ArmCondition condition, long branchPos) in list)
{
- _stream.Seek(tuple.BranchPos, SeekOrigin.Begin);
- WriteBranch(tuple.Condition, target);
+ _stream.Seek(branchPos, SeekOrigin.Begin);
+ WriteBranch(condition, target);
}
_stream.Seek(target, SeekOrigin.Begin);
@@ -284,4 +284,4 @@ private void WriteUInt64(ulong value)
_stream.WriteByte((byte)(value >> 56));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs
index fc4fa976e..2df86671a 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs
@@ -10,7 +10,6 @@
using System.Collections.Generic;
using System.Diagnostics;
using System.Numerics;
-
using static ARMeilleure.IntermediateRepresentation.Operand;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -31,15 +30,16 @@ private enum AccessSize
{
Byte,
Hword,
- Auto
+ Auto,
}
- private static Action[] _instTable;
+ private static readonly Action[] _instTable;
static CodeGenerator()
{
_instTable = new Action[EnumUtils.GetCount(typeof(Instruction))];
+#pragma warning disable IDE0055 // Disable formatting
Add(Instruction.Add, GenerateAdd);
Add(Instruction.BitwiseAnd, GenerateBitwiseAnd);
Add(Instruction.BitwiseExclusiveOr, GenerateBitwiseExclusiveOr);
@@ -48,7 +48,7 @@ static CodeGenerator()
Add(Instruction.BranchIf, GenerateBranchIf);
Add(Instruction.ByteSwap, GenerateByteSwap);
Add(Instruction.Call, GenerateCall);
- //Add(Instruction.Clobber, GenerateClobber);
+ // Add(Instruction.Clobber, GenerateClobber);
Add(Instruction.Compare, GenerateCompare);
Add(Instruction.CompareAndSwap, GenerateCompareAndSwap);
Add(Instruction.CompareAndSwap16, GenerateCompareAndSwap16);
@@ -100,6 +100,7 @@ static CodeGenerator()
Add(Instruction.ZeroExtend16, GenerateZeroExtend16);
Add(Instruction.ZeroExtend32, GenerateZeroExtend32);
Add(Instruction.ZeroExtend8, GenerateZeroExtend8);
+#pragma warning restore IDE0055
static void Add(Instruction inst, Action func)
{
@@ -131,7 +132,7 @@ public static CompiledFunction Generate(CompilerContext cctx)
StackAllocator stackAlloc = new();
- PreAllocator.RunPass(cctx, stackAlloc, out int maxCallArgs);
+ PreAllocator.RunPass(cctx, out int maxCallArgs);
Logger.EndPass(PassName.PreAllocation, cfg);
@@ -168,11 +169,9 @@ public static CompiledFunction Generate(CompilerContext cctx)
Logger.StartPass(PassName.CodeGeneration);
- //Console.Error.WriteLine(IRDumper.GetDump(cfg));
-
bool relocatable = (cctx.Options & CompilerOptions.Relocatable) != 0;
- CodeGenContext context = new(allocResult, maxCallArgs, cfg.Blocks.Count, relocatable);
+ CodeGenContext context = new(allocResult, maxCallArgs, relocatable);
UnwindInfo unwindInfo = WritePrologue(context);
@@ -294,7 +293,7 @@ private static void GenerateBitwiseExclusiveOr(CodeGenContext context, Operation
private static void GenerateBitwiseNot(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
ValidateUnOp(dest, source);
@@ -332,7 +331,7 @@ private static void GenerateBranchIf(CodeGenContext context, Operation operation
private static void GenerateByteSwap(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
ValidateUnOp(dest, source);
@@ -366,15 +365,15 @@ private static void GenerateCompareAndSwap(CodeGenContext context, Operation ope
{
if (operation.SourcesCount == 5) // CompareAndSwap128 has 5 sources, compared to CompareAndSwap64/32's 3.
{
- Operand actualLow = operation.GetDestination(0);
- Operand actualHigh = operation.GetDestination(1);
- Operand temp0 = operation.GetDestination(2);
- Operand temp1 = operation.GetDestination(3);
- Operand address = operation.GetSource(0);
- Operand expectedLow = operation.GetSource(1);
+ Operand actualLow = operation.GetDestination(0);
+ Operand actualHigh = operation.GetDestination(1);
+ Operand temp0 = operation.GetDestination(2);
+ Operand temp1 = operation.GetDestination(3);
+ Operand address = operation.GetSource(0);
+ Operand expectedLow = operation.GetSource(1);
Operand expectedHigh = operation.GetSource(2);
- Operand desiredLow = operation.GetSource(3);
- Operand desiredHigh = operation.GetSource(4);
+ Operand desiredLow = operation.GetSource(3);
+ Operand desiredHigh = operation.GetSource(4);
GenerateAtomicDcas(
context,
@@ -390,11 +389,11 @@ private static void GenerateCompareAndSwap(CodeGenContext context, Operation ope
}
else
{
- Operand actual = operation.GetDestination(0);
- Operand result = operation.GetDestination(1);
- Operand address = operation.GetSource(0);
+ Operand actual = operation.GetDestination(0);
+ Operand result = operation.GetDestination(1);
+ Operand address = operation.GetSource(0);
Operand expected = operation.GetSource(1);
- Operand desired = operation.GetSource(2);
+ Operand desired = operation.GetSource(2);
GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Auto);
}
@@ -402,22 +401,22 @@ private static void GenerateCompareAndSwap(CodeGenContext context, Operation ope
private static void GenerateCompareAndSwap16(CodeGenContext context, Operation operation)
{
- Operand actual = operation.GetDestination(0);
- Operand result = operation.GetDestination(1);
- Operand address = operation.GetSource(0);
+ Operand actual = operation.GetDestination(0);
+ Operand result = operation.GetDestination(1);
+ Operand address = operation.GetSource(0);
Operand expected = operation.GetSource(1);
- Operand desired = operation.GetSource(2);
+ Operand desired = operation.GetSource(2);
GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Hword);
}
private static void GenerateCompareAndSwap8(CodeGenContext context, Operation operation)
{
- Operand actual = operation.GetDestination(0);
- Operand result = operation.GetDestination(1);
- Operand address = operation.GetSource(0);
+ Operand actual = operation.GetDestination(0);
+ Operand result = operation.GetDestination(1);
+ Operand address = operation.GetSource(0);
Operand expected = operation.GetSource(1);
- Operand desired = operation.GetSource(2);
+ Operand desired = operation.GetSource(2);
GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Byte);
}
@@ -446,13 +445,13 @@ private static void GenerateConditionalSelect(CodeGenContext context, Operation
Debug.Assert(dest.Type.IsInteger());
Debug.Assert(src1.Type == OperandType.I32);
- context.Assembler.Cmp (src1, Const(src1.Type, 0));
+ context.Assembler.Cmp(src1, Const(src1.Type, 0));
context.Assembler.Csel(dest, src2, src3, ArmCondition.Ne);
}
private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64);
@@ -462,7 +461,7 @@ private static void GenerateConvertI64ToI32(CodeGenContext context, Operation op
private static void GenerateConvertToFP(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
@@ -481,7 +480,7 @@ private static void GenerateConvertToFP(CodeGenContext context, Operation operat
private static void GenerateConvertToFPUI(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
@@ -493,7 +492,7 @@ private static void GenerateConvertToFPUI(CodeGenContext context, Operation oper
private static void GenerateCopy(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
EnsureSameType(dest, source);
@@ -525,7 +524,7 @@ private static void GenerateCopy(CodeGenContext context, Operation operation)
private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
EnsureSameType(dest, source);
@@ -537,9 +536,9 @@ private static void GenerateCountLeadingZeros(CodeGenContext context, Operation
private static void GenerateDivide(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand dividend = operation.GetSource(0);
- Operand divisor = operation.GetSource(1);
+ Operand divisor = operation.GetSource(1);
ValidateBinOp(dest, dividend, divisor);
@@ -555,9 +554,9 @@ private static void GenerateDivide(CodeGenContext context, Operation operation)
private static void GenerateDivideUI(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand dividend = operation.GetSource(0);
- Operand divisor = operation.GetSource(1);
+ Operand divisor = operation.GetSource(1);
ValidateBinOp(dest, dividend, divisor);
@@ -566,7 +565,7 @@ private static void GenerateDivideUI(CodeGenContext context, Operation operation
private static void GenerateLoad(CodeGenContext context, Operation operation)
{
- Operand value = operation.Destination;
+ Operand value = operation.Destination;
Operand address = operation.GetSource(0);
context.Assembler.Ldr(value, address);
@@ -574,7 +573,7 @@ private static void GenerateLoad(CodeGenContext context, Operation operation)
private static void GenerateLoad16(CodeGenContext context, Operation operation)
{
- Operand value = operation.Destination;
+ Operand value = operation.Destination;
Operand address = operation.GetSource(0);
Debug.Assert(value.Type.IsInteger());
@@ -584,7 +583,7 @@ private static void GenerateLoad16(CodeGenContext context, Operation operation)
private static void GenerateLoad8(CodeGenContext context, Operation operation)
{
- Operand value = operation.Destination;
+ Operand value = operation.Destination;
Operand address = operation.GetSource(0);
Debug.Assert(value.Type.IsInteger());
@@ -643,7 +642,7 @@ private static void GenerateMultiply64HighUI(CodeGenContext context, Operation o
private static void GenerateNegate(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
ValidateUnOp(dest, source);
@@ -730,7 +729,7 @@ private static void GenerateShiftRightUI(CodeGenContext context, Operation opera
private static void GenerateSignExtend16(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -740,7 +739,7 @@ private static void GenerateSignExtend16(CodeGenContext context, Operation opera
private static void GenerateSignExtend32(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -750,7 +749,7 @@ private static void GenerateSignExtend32(CodeGenContext context, Operation opera
private static void GenerateSignExtend8(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -760,7 +759,7 @@ private static void GenerateSignExtend8(CodeGenContext context, Operation operat
private static void GenerateFill(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand offset = operation.GetSource(0);
Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -801,7 +800,7 @@ private static void GenerateSpillArg(CodeGenContext context, Operation operation
private static void GenerateStackAlloc(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand offset = operation.GetSource(0);
Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -813,7 +812,7 @@ private static void GenerateStackAlloc(CodeGenContext context, Operation operati
private static void GenerateStore(CodeGenContext context, Operation operation)
{
- Operand value = operation.GetSource(1);
+ Operand value = operation.GetSource(1);
Operand address = operation.GetSource(0);
context.Assembler.Str(value, address);
@@ -821,7 +820,7 @@ private static void GenerateStore(CodeGenContext context, Operation operation)
private static void GenerateStore16(CodeGenContext context, Operation operation)
{
- Operand value = operation.GetSource(1);
+ Operand value = operation.GetSource(1);
Operand address = operation.GetSource(0);
Debug.Assert(value.Type.IsInteger());
@@ -831,7 +830,7 @@ private static void GenerateStore16(CodeGenContext context, Operation operation)
private static void GenerateStore8(CodeGenContext context, Operation operation)
{
- Operand value = operation.GetSource(1);
+ Operand value = operation.GetSource(1);
Operand address = operation.GetSource(0);
Debug.Assert(value.Type.IsInteger());
@@ -878,7 +877,7 @@ private static void GenerateTailcall(CodeGenContext context, Operation operation
private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
if (dest != default)
@@ -1024,7 +1023,7 @@ private static void GenerateVectorZero(CodeGenContext context, Operation operati
private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1034,7 +1033,7 @@ private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation
private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1044,7 +1043,7 @@ private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation
private static void GenerateZeroExtend16(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1054,7 +1053,7 @@ private static void GenerateZeroExtend16(CodeGenContext context, Operation opera
private static void GenerateZeroExtend32(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1070,7 +1069,7 @@ private static void GenerateZeroExtend32(CodeGenContext context, Operation opera
private static void GenerateZeroExtend8(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1080,7 +1079,7 @@ private static void GenerateZeroExtend8(CodeGenContext context, Operation operat
private static UnwindInfo WritePrologue(CodeGenContext context)
{
- List pushEntries = new List();
+ List pushEntries = new();
Operand rsp = Register(SpRegister);
@@ -1570,11 +1569,13 @@ private static void EnsureSameType(Operand op1, Operand op2, Operand op3)
Debug.Assert(op1.Type == op3.Type);
}
+#pragma warning disable IDE0051 // Remove unused private member
private static void EnsureSameType(Operand op1, Operand op2, Operand op3, Operand op4)
{
Debug.Assert(op1.Type == op2.Type);
Debug.Assert(op1.Type == op3.Type);
Debug.Assert(op1.Type == op4.Type);
}
+#pragma warning restore IDE0051
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs
index aaa00bb65..b87370557 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs
@@ -179,6 +179,35 @@ public static void GenerateOperation(CodeGenContext context, Operation operation
(uint)operation.GetSource(2).AsInt32());
break;
+ case IntrinsicType.Vector128Unary:
+ GenerateVectorUnary(
+ context,
+ 1,
+ 0,
+ info.Inst,
+ operation.Destination,
+ operation.GetSource(0));
+ break;
+ case IntrinsicType.Vector128Binary:
+ GenerateVectorBinary(
+ context,
+ 1,
+ 0,
+ info.Inst,
+ operation.Destination,
+ operation.GetSource(0),
+ operation.GetSource(1));
+ break;
+ case IntrinsicType.Vector128BinaryRd:
+ GenerateVectorUnary(
+ context,
+ 1,
+ 0,
+ info.Inst,
+ operation.Destination,
+ operation.GetSource(1));
+ break;
+
case IntrinsicType.VectorUnary:
GenerateVectorUnary(
context,
@@ -659,4 +688,4 @@ private static void GenerateVectorInsertByElem(
context.Assembler.WriteInstruction(instruction, rd, rn);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs b/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
index 99ff299e9..86afc2b4d 100644
--- a/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
@@ -1,7 +1,4 @@
using System;
-using System.Linq;
-using System.Reflection;
-using System.Runtime.CompilerServices;
using System.Runtime.InteropServices;
using System.Runtime.Intrinsics.Arm;
using System.Runtime.Versioning;
@@ -35,7 +32,7 @@ static HardwareCapabilities()
}
}
-#region Linux
+ #region Linux
private const ulong AT_HWCAP = 16;
private const ulong AT_HWCAP2 = 26;
@@ -46,88 +43,88 @@ static HardwareCapabilities()
[Flags]
public enum LinuxFeatureFlagsHwCap : ulong
{
- Fp = 1 << 0,
- Asimd = 1 << 1,
- Evtstrm = 1 << 2,
- Aes = 1 << 3,
- Pmull = 1 << 4,
- Sha1 = 1 << 5,
- Sha2 = 1 << 6,
- Crc32 = 1 << 7,
- Atomics = 1 << 8,
- FpHp = 1 << 9,
- AsimdHp = 1 << 10,
- CpuId = 1 << 11,
- AsimdRdm = 1 << 12,
- Jscvt = 1 << 13,
- Fcma = 1 << 14,
- Lrcpc = 1 << 15,
- DcpOp = 1 << 16,
- Sha3 = 1 << 17,
- Sm3 = 1 << 18,
- Sm4 = 1 << 19,
- AsimdDp = 1 << 20,
- Sha512 = 1 << 21,
- Sve = 1 << 22,
- AsimdFhm = 1 << 23,
- Dit = 1 << 24,
- Uscat = 1 << 25,
- Ilrcpc = 1 << 26,
- FlagM = 1 << 27,
- Ssbs = 1 << 28,
- Sb = 1 << 29,
- Paca = 1 << 30,
- Pacg = 1UL << 31
+ Fp = 1 << 0,
+ Asimd = 1 << 1,
+ Evtstrm = 1 << 2,
+ Aes = 1 << 3,
+ Pmull = 1 << 4,
+ Sha1 = 1 << 5,
+ Sha2 = 1 << 6,
+ Crc32 = 1 << 7,
+ Atomics = 1 << 8,
+ FpHp = 1 << 9,
+ AsimdHp = 1 << 10,
+ CpuId = 1 << 11,
+ AsimdRdm = 1 << 12,
+ Jscvt = 1 << 13,
+ Fcma = 1 << 14,
+ Lrcpc = 1 << 15,
+ DcpOp = 1 << 16,
+ Sha3 = 1 << 17,
+ Sm3 = 1 << 18,
+ Sm4 = 1 << 19,
+ AsimdDp = 1 << 20,
+ Sha512 = 1 << 21,
+ Sve = 1 << 22,
+ AsimdFhm = 1 << 23,
+ Dit = 1 << 24,
+ Uscat = 1 << 25,
+ Ilrcpc = 1 << 26,
+ FlagM = 1 << 27,
+ Ssbs = 1 << 28,
+ Sb = 1 << 29,
+ Paca = 1 << 30,
+ Pacg = 1UL << 31,
}
[Flags]
public enum LinuxFeatureFlagsHwCap2 : ulong
{
- Dcpodp = 1 << 0,
- Sve2 = 1 << 1,
- SveAes = 1 << 2,
- SvePmull = 1 << 3,
- SveBitperm = 1 << 4,
- SveSha3 = 1 << 5,
- SveSm4 = 1 << 6,
- FlagM2 = 1 << 7,
- Frint = 1 << 8,
- SveI8mm = 1 << 9,
- SveF32mm = 1 << 10,
- SveF64mm = 1 << 11,
- SveBf16 = 1 << 12,
- I8mm = 1 << 13,
- Bf16 = 1 << 14,
- Dgh = 1 << 15,
- Rng = 1 << 16,
- Bti = 1 << 17,
- Mte = 1 << 18,
- Ecv = 1 << 19,
- Afp = 1 << 20,
- Rpres = 1 << 21,
- Mte3 = 1 << 22,
- Sme = 1 << 23,
- Sme_i16i64 = 1 << 24,
- Sme_f64f64 = 1 << 25,
- Sme_i8i32 = 1 << 26,
- Sme_f16f32 = 1 << 27,
- Sme_b16f32 = 1 << 28,
- Sme_f32f32 = 1 << 29,
- Sme_fa64 = 1 << 30,
- Wfxt = 1UL << 31,
- Ebf16 = 1UL << 32,
- Sve_Ebf16 = 1UL << 33,
- Cssc = 1UL << 34,
- Rprfm = 1UL << 35,
- Sve2p1 = 1UL << 36
+ Dcpodp = 1 << 0,
+ Sve2 = 1 << 1,
+ SveAes = 1 << 2,
+ SvePmull = 1 << 3,
+ SveBitperm = 1 << 4,
+ SveSha3 = 1 << 5,
+ SveSm4 = 1 << 6,
+ FlagM2 = 1 << 7,
+ Frint = 1 << 8,
+ SveI8mm = 1 << 9,
+ SveF32mm = 1 << 10,
+ SveF64mm = 1 << 11,
+ SveBf16 = 1 << 12,
+ I8mm = 1 << 13,
+ Bf16 = 1 << 14,
+ Dgh = 1 << 15,
+ Rng = 1 << 16,
+ Bti = 1 << 17,
+ Mte = 1 << 18,
+ Ecv = 1 << 19,
+ Afp = 1 << 20,
+ Rpres = 1 << 21,
+ Mte3 = 1 << 22,
+ Sme = 1 << 23,
+ Sme_i16i64 = 1 << 24,
+ Sme_f64f64 = 1 << 25,
+ Sme_i8i32 = 1 << 26,
+ Sme_f16f32 = 1 << 27,
+ Sme_b16f32 = 1 << 28,
+ Sme_f32f32 = 1 << 29,
+ Sme_fa64 = 1 << 30,
+ Wfxt = 1UL << 31,
+ Ebf16 = 1UL << 32,
+ Sve_Ebf16 = 1UL << 33,
+ Cssc = 1UL << 34,
+ Rprfm = 1UL << 35,
+ Sve2p1 = 1UL << 36,
}
public static LinuxFeatureFlagsHwCap LinuxFeatureInfoHwCap { get; } = 0;
public static LinuxFeatureFlagsHwCap2 LinuxFeatureInfoHwCap2 { get; } = 0;
-#endregion
+ #endregion
-#region macOS
+ #region macOS
[LibraryImport("libSystem.dylib", SetLastError = true)]
private static unsafe partial int sysctlbyname([MarshalAs(UnmanagedType.LPStr)] string name, out int oldValue, ref ulong oldSize, IntPtr newValue, ulong newValueSize);
@@ -143,7 +140,7 @@ private static bool CheckSysctlName(string name)
return false;
}
- private static string[] _sysctlNames = new string[]
+ private static readonly string[] _sysctlNames = new string[]
{
"hw.optional.floatingpoint",
"hw.optional.AdvSIMD",
@@ -153,26 +150,26 @@ private static bool CheckSysctlName(string name)
"hw.optional.arm.FEAT_LSE",
"hw.optional.armv8_crc32",
"hw.optional.arm.FEAT_SHA1",
- "hw.optional.arm.FEAT_SHA256"
+ "hw.optional.arm.FEAT_SHA256",
};
[Flags]
public enum MacOsFeatureFlags
{
- Fp = 1 << 0,
+ Fp = 1 << 0,
AdvSimd = 1 << 1,
- Fp16 = 1 << 2,
- Aes = 1 << 3,
- Pmull = 1 << 4,
- Lse = 1 << 5,
- Crc32 = 1 << 6,
- Sha1 = 1 << 7,
- Sha256 = 1 << 8
+ Fp16 = 1 << 2,
+ Aes = 1 << 3,
+ Pmull = 1 << 4,
+ Lse = 1 << 5,
+ Crc32 = 1 << 6,
+ Sha1 = 1 << 7,
+ Sha256 = 1 << 8,
}
public static MacOsFeatureFlags MacOsFeatureInfo { get; } = 0;
-#endregion
+ #endregion
public static bool SupportsAdvSimd => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Asimd) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.AdvSimd);
public static bool SupportsAes => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Aes) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Aes);
diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs
index 8695db903..956fc778d 100644
--- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs
@@ -1,8 +1,8 @@
namespace ARMeilleure.CodeGen.Arm64
{
- struct IntrinsicInfo
+ readonly struct IntrinsicInfo
{
- public uint Inst { get; }
+ public uint Inst { get; }
public IntrinsicType Type { get; }
public IntrinsicInfo(uint inst, IntrinsicType type)
@@ -11,4 +11,4 @@ public IntrinsicInfo(uint inst, IntrinsicType type)
Type = type;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs
index a309d56d9..dbd5bdd10 100644
--- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs
@@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.Arm64
{
static class IntrinsicTable
{
- private static IntrinsicInfo[] _intrinTable;
+ private static readonly IntrinsicInfo[] _intrinTable;
static IntrinsicTable()
{
_intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))];
+#pragma warning disable IDE0055 // Disable formatting
Add(Intrinsic.Arm64AbsS, new IntrinsicInfo(0x5e20b800u, IntrinsicType.ScalarUnary));
Add(Intrinsic.Arm64AbsV, new IntrinsicInfo(0x0e20b800u, IntrinsicType.VectorUnary));
Add(Intrinsic.Arm64AddhnV, new IntrinsicInfo(0x0e204000u, IntrinsicType.VectorTernaryRd));
@@ -19,8 +20,8 @@ static IntrinsicTable()
Add(Intrinsic.Arm64AddvV, new IntrinsicInfo(0x0e31b800u, IntrinsicType.VectorUnary));
Add(Intrinsic.Arm64AddS, new IntrinsicInfo(0x5e208400u, IntrinsicType.ScalarBinary));
Add(Intrinsic.Arm64AddV, new IntrinsicInfo(0x0e208400u, IntrinsicType.VectorBinary));
- Add(Intrinsic.Arm64AesdV, new IntrinsicInfo(0x4e285800u, IntrinsicType.Vector128Unary));
- Add(Intrinsic.Arm64AeseV, new IntrinsicInfo(0x4e284800u, IntrinsicType.Vector128Unary));
+ Add(Intrinsic.Arm64AesdV, new IntrinsicInfo(0x4e285800u, IntrinsicType.Vector128BinaryRd));
+ Add(Intrinsic.Arm64AeseV, new IntrinsicInfo(0x4e284800u, IntrinsicType.Vector128BinaryRd));
Add(Intrinsic.Arm64AesimcV, new IntrinsicInfo(0x4e287800u, IntrinsicType.Vector128Unary));
Add(Intrinsic.Arm64AesmcV, new IntrinsicInfo(0x4e286800u, IntrinsicType.Vector128Unary));
Add(Intrinsic.Arm64AndV, new IntrinsicInfo(0x0e201c00u, IntrinsicType.VectorBinaryBitwise));
@@ -448,6 +449,7 @@ static IntrinsicTable()
Add(Intrinsic.Arm64XtnV, new IntrinsicInfo(0x0e212800u, IntrinsicType.VectorUnary));
Add(Intrinsic.Arm64Zip1V, new IntrinsicInfo(0x0e003800u, IntrinsicType.VectorBinary));
Add(Intrinsic.Arm64Zip2V, new IntrinsicInfo(0x0e007800u, IntrinsicType.VectorBinary));
+#pragma warning restore IDE0055
}
private static void Add(Intrinsic intrin, IntrinsicInfo info)
@@ -460,4 +462,4 @@ public static IntrinsicInfo GetInfo(Intrinsic intrin)
return _intrinTable[(int)intrin];
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs
index 800eca93c..7538575c9 100644
--- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs
@@ -23,6 +23,10 @@ enum IntrinsicType
ScalarTernaryShlRd,
ScalarTernaryShrRd,
+ Vector128Unary,
+ Vector128Binary,
+ Vector128BinaryRd,
+
VectorUnary,
VectorUnaryBitwise,
VectorUnaryByElem,
@@ -50,10 +54,7 @@ enum IntrinsicType
VectorTernaryShlRd,
VectorTernaryShrRd,
- Vector128Unary,
- Vector128Binary,
-
GetRegister,
- SetRegister
+ SetRegister,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs
index 6ea9d2397..f66bb66e6 100644
--- a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs
@@ -1,4 +1,3 @@
-using ARMeilleure.CodeGen.RegisterAllocators;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System;
@@ -31,7 +30,7 @@ public bool TryGetValue(ulong value, OperandType type, out Operand local)
}
}
- public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out int maxCallArgs)
+ public static void RunPass(CompilerContext cctx, out int maxCallArgs)
{
maxCallArgs = -1;
@@ -41,7 +40,7 @@ public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out
for (BasicBlock block = cctx.Cfg.Blocks.First; block != null; block = block.ListNext)
{
- ConstantDict constants = new ConstantDict();
+ ConstantDict constants = new();
Operation nextNode;
@@ -92,7 +91,7 @@ public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out
InsertReturnCopy(block.Operations, node);
break;
case Instruction.Tailcall:
- InsertTailcallCopies(constants, block.Operations, stackAlloc, node, node);
+ InsertTailcallCopies(constants, block.Operations, node, node);
break;
}
}
@@ -138,10 +137,7 @@ private static void InsertConstantRegCopies(ConstantDict constants, IntrusiveLis
{
src2 = node.GetSource(1);
- Operand temp = src1;
-
- src1 = src2;
- src2 = temp;
+ (src2, src1) = (src1, src2);
node.SetSource(0, src1);
node.SetSource(1, src2);
@@ -265,9 +261,9 @@ private static void InsertCallCopies(ConstantDict constants, IntrusiveList sources = new List
+ List sources = new()
{
- operation.GetSource(0)
+ operation.GetSource(0),
};
int argsCount = operation.SourcesCount - 1;
@@ -302,10 +298,10 @@ private static void InsertCallCopies(ConstantDict constants, IntrusiveList nodes,
- StackAllocator stackAlloc,
Operation node,
Operation operation)
{
- List sources = new List
+ List sources = new()
{
- operation.GetSource(0)
+ operation.GetSource(0),
};
int argsCount = operation.SourcesCount - 1;
@@ -403,7 +397,7 @@ private static void InsertTailcallCopies(
if (source.Type == OperandType.V128 && passOnReg)
{
// V128 is a struct, we pass each half on a GPR if possible.
- Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
+ Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0)));
@@ -519,7 +513,7 @@ private static void InsertReturnCopy(IntrusiveList nodes, Operation n
if (source.Type == OperandType.V128)
{
- Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
+ Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0)));
@@ -746,6 +740,7 @@ private static bool IsSameOperandDestSrc1(Intrinsic intrinsic)
info.Type == IntrinsicType.ScalarTernaryFPRdByElem ||
info.Type == IntrinsicType.ScalarTernaryShlRd ||
info.Type == IntrinsicType.ScalarTernaryShrRd ||
+ info.Type == IntrinsicType.Vector128BinaryRd ||
info.Type == IntrinsicType.VectorBinaryRd ||
info.Type == IntrinsicType.VectorInsertByElem ||
info.Type == IntrinsicType.VectorTernaryRd ||
diff --git a/src/ARMeilleure/CodeGen/CompiledFunction.cs b/src/ARMeilleure/CodeGen/CompiledFunction.cs
index 0560bf2e9..3844cbfc9 100644
--- a/src/ARMeilleure/CodeGen/CompiledFunction.cs
+++ b/src/ARMeilleure/CodeGen/CompiledFunction.cs
@@ -35,9 +35,9 @@ readonly struct CompiledFunction
/// Relocation info
internal CompiledFunction(byte[] code, UnwindInfo unwindInfo, RelocInfo relocInfo)
{
- Code = code;
+ Code = code;
UnwindInfo = unwindInfo;
- RelocInfo = relocInfo;
+ RelocInfo = relocInfo;
}
///
@@ -65,4 +65,4 @@ public T MapWithPointer(out IntPtr codePointer)
return Marshal.GetDelegateForFunctionPointer(codePointer);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs b/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs
index a27bfded2..d103bc395 100644
--- a/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs
+++ b/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs
@@ -35,4 +35,4 @@ public override string ToString()
return $"({nameof(Position)} = {Position}, {nameof(Symbol)} = {Symbol})";
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs b/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs
index caaf08e3d..01ff0347b 100644
--- a/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs
+++ b/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs
@@ -29,4 +29,4 @@ public RelocInfo(RelocEntry[] entries)
_entries = entries;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Linking/Symbol.cs b/src/ARMeilleure/CodeGen/Linking/Symbol.cs
index 39e0c3eb1..5559afe09 100644
--- a/src/ARMeilleure/CodeGen/Linking/Symbol.cs
+++ b/src/ARMeilleure/CodeGen/Linking/Symbol.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.CodeGen.Linking
{
diff --git a/src/ARMeilleure/CodeGen/Linking/SymbolType.cs b/src/ARMeilleure/CodeGen/Linking/SymbolType.cs
index b05b69692..29011a762 100644
--- a/src/ARMeilleure/CodeGen/Linking/SymbolType.cs
+++ b/src/ARMeilleure/CodeGen/Linking/SymbolType.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.CodeGen.Linking
+namespace ARMeilleure.CodeGen.Linking
{
///
/// Types of .
@@ -23,6 +23,6 @@ enum SymbolType : byte
///
/// Refers to a special symbol which is handled by .
///
- Special
+ Special,
}
}
diff --git a/src/ARMeilleure/CodeGen/Optimizations/BlockPlacement.cs b/src/ARMeilleure/CodeGen/Optimizations/BlockPlacement.cs
index 9e243d378..5f0e37721 100644
--- a/src/ARMeilleure/CodeGen/Optimizations/BlockPlacement.cs
+++ b/src/ARMeilleure/CodeGen/Optimizations/BlockPlacement.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.IntermediateRepresentation;
+using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System.Diagnostics;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
diff --git a/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs b/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs
index c5a22a537..be3dff58c 100644
--- a/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs
+++ b/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs
@@ -164,7 +164,7 @@ public static void RunPass(Operation operation)
}
break;
- case Instruction.Multiply:
+ case Instruction.Multiply:
if (type == OperandType.I32)
{
EvaluateBinaryI32(operation, (x, y) => x * y);
@@ -343,4 +343,4 @@ private static void EvaluateBinaryI64(Operation operation, Func buffer, Operation copyOp)
{
// Propagate copy source operand to all uses of the destination operand.
- Operand dest = copyOp.Destination;
+ Operand dest = copyOp.Destination;
Operand source = copyOp.GetSource(0);
Span uses = dest.GetUses(ref buffer);
@@ -249,4 +249,4 @@ private static bool IsPropagableCopy(Operation operation)
return operation.Destination.Type == operation.GetSource(0).Type;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs b/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs
index a439d6424..53a7f3ede 100644
--- a/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs
+++ b/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs
@@ -171,13 +171,12 @@ private static bool IsConstEqual(Operand operand, ulong comparand)
private static ulong AllOnes(OperandType type)
{
- switch (type)
+ return type switch
{
- case OperandType.I32: return ~0U;
- case OperandType.I64: return ~0UL;
- }
-
- throw new ArgumentException("Invalid operand type \"" + type + "\".");
+ OperandType.I32 => ~0U,
+ OperandType.I64 => ~0UL,
+ _ => throw new ArgumentException("Invalid operand type \"" + type + "\"."),
+ };
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Optimizations/TailMerge.cs b/src/ARMeilleure/CodeGen/Optimizations/TailMerge.cs
index e94df159c..e63c4da0d 100644
--- a/src/ARMeilleure/CodeGen/Optimizations/TailMerge.cs
+++ b/src/ARMeilleure/CodeGen/Optimizations/TailMerge.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.IntermediateRepresentation;
+using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.IntermediateRepresentation.Operation.Factory;
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs
index 43e5c7e2c..7b9c2f77f 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs
@@ -4,7 +4,7 @@ readonly struct AllocationResult
{
public int IntUsedRegisters { get; }
public int VecUsedRegisters { get; }
- public int SpillRegionSize { get; }
+ public int SpillRegionSize { get; }
public AllocationResult(
int intUsedRegisters,
@@ -13,7 +13,7 @@ public AllocationResult(
{
IntUsedRegisters = intUsedRegisters;
VecUsedRegisters = vecUsedRegisters;
- SpillRegionSize = spillRegionSize;
+ SpillRegionSize = spillRegionSize;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs
index 587b1a024..af10330ba 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs
@@ -1,7 +1,6 @@
using ARMeilleure.IntermediateRepresentation;
using System;
using System.Collections.Generic;
-
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
using static ARMeilleure.IntermediateRepresentation.Operation.Factory;
@@ -13,16 +12,16 @@ private class ParallelCopy
{
private readonly struct Copy
{
- public Register Dest { get; }
+ public Register Dest { get; }
public Register Source { get; }
public OperandType Type { get; }
public Copy(Register dest, Register source, OperandType type)
{
- Dest = dest;
+ Dest = dest;
Source = source;
- Type = type;
+ Type = type;
}
}
@@ -42,19 +41,19 @@ public void AddCopy(Register dest, Register source, OperandType type)
public void Sequence(List sequence)
{
- Dictionary locations = new Dictionary();
- Dictionary sources = new Dictionary();
+ Dictionary locations = new();
+ Dictionary sources = new();
- Dictionary types = new Dictionary();
+ Dictionary types = new();
- Queue pendingQueue = new Queue();
- Queue readyQueue = new Queue();
+ Queue pendingQueue = new();
+ Queue readyQueue = new();
foreach (Copy copy in _copies)
{
locations[copy.Source] = copy.Source;
- sources[copy.Dest] = copy.Source;
- types[copy.Dest] = copy.Type;
+ sources[copy.Dest] = copy.Source;
+ types[copy.Dest] = copy.Type;
pendingQueue.Enqueue(copy.Dest);
}
@@ -91,7 +90,7 @@ public void Sequence(List sequence)
}
}
- copyDest = current;
+ copyDest = current;
origSource = sources[copyDest];
copySource = locations[origSource];
@@ -186,10 +185,7 @@ public void AddSplit(LiveInterval left, LiveInterval right)
private void AddSplitFill(LiveInterval left, LiveInterval right, OperandType type)
{
- if (_fillQueue == null)
- {
- _fillQueue = new Queue();
- }
+ _fillQueue ??= new Queue();
Operand register = GetRegister(right.Register, type);
Operand offset = Const(left.SpillOffset);
@@ -201,10 +197,7 @@ private void AddSplitFill(LiveInterval left, LiveInterval right, OperandType typ
private void AddSplitSpill(LiveInterval left, LiveInterval right, OperandType type)
{
- if (_spillQueue == null)
- {
- _spillQueue = new Queue();
- }
+ _spillQueue ??= new Queue();
Operand offset = Const(right.SpillOffset);
Operand register = GetRegister(left.Register, type);
@@ -216,10 +209,7 @@ private void AddSplitSpill(LiveInterval left, LiveInterval right, OperandType ty
private void AddSplitCopy(LiveInterval left, LiveInterval right, OperandType type)
{
- if (_parallelCopy == null)
- {
- _parallelCopy = new ParallelCopy();
- }
+ _parallelCopy ??= new ParallelCopy();
_parallelCopy.AddCopy(right.Register, left.Register, type);
@@ -228,7 +218,7 @@ private void AddSplitCopy(LiveInterval left, LiveInterval right, OperandType typ
public Operation[] Sequence()
{
- List sequence = new List();
+ List sequence = new();
if (_spillQueue != null)
{
@@ -256,4 +246,4 @@ private static Operand GetRegister(Register reg, OperandType type)
return Register(reg.Index, reg.Type, type);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs
index 25952c775..5f1d6ce89 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs
@@ -20,7 +20,7 @@ private readonly struct BlockInfo
public BlockInfo(bool hasCall, int intFixedRegisters, int vecFixedRegisters)
{
- HasCall = hasCall;
+ HasCall = hasCall;
IntFixedRegisters = intFixedRegisters;
VecFixedRegisters = vecFixedRegisters;
}
@@ -39,7 +39,7 @@ private struct LocalInfo
private int _first;
private int _last;
- public bool IsBlockLocal => _first == _last;
+ public readonly bool IsBlockLocal => _first == _last;
public LocalInfo(OperandType type, int uses, int blkIndex)
{
@@ -53,7 +53,7 @@ public LocalInfo(OperandType type, int uses, int blkIndex)
SpillOffset = default;
_first = -1;
- _last = -1;
+ _last = -1;
SetBlockIndex(blkIndex);
}
@@ -348,17 +348,17 @@ Operand AllocateRegister(Operand local)
if (dest.Type.IsInteger())
{
intLocalFreeRegisters &= ~(1 << selectedReg);
- intUsedRegisters |= 1 << selectedReg;
+ intUsedRegisters |= 1 << selectedReg;
}
else
{
vecLocalFreeRegisters &= ~(1 << selectedReg);
- vecUsedRegisters |= 1 << selectedReg;
+ vecUsedRegisters |= 1 << selectedReg;
}
}
else
{
- info.Register = default;
+ info.Register = default;
info.SpillOffset = Const(stackAlloc.Allocate(dest.Type.GetSizeInBytes()));
}
}
@@ -382,7 +382,7 @@ Operand AllocateRegister(Operand local)
: GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg);
info.Sequence = sequence;
- info.Temp = temp;
+ info.Temp = temp;
}
dest = temp;
@@ -408,7 +408,7 @@ Operand AllocateRegister(Operand local)
private static int SelectSpillTemps(int mask0, int mask1)
{
int selection = 0;
- int count = 0;
+ int count = 0;
while (count < MaxIROperands && mask0 != 0)
{
@@ -451,4 +451,4 @@ private static int UsesCount(Operand local)
return local.AssignmentsCount + local.UsesCount;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs
index 8f236c253..7d4ce2ea6 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs
@@ -9,4 +9,4 @@ AllocationResult RunPass(
StackAllocator stackAlloc,
RegisterMasks regMasks);
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs
index d80157afb..f156e0886 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs
@@ -14,7 +14,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
// http://www.christianwimmer.at/Publications/Wimmer04a/Wimmer04a.pdf
class LinearScanAllocator : IRegisterAllocator
{
- private const int InstructionGap = 2;
+ private const int InstructionGap = 2;
private const int InstructionGapMask = InstructionGap - 1;
private HashSet _blockEdges;
@@ -33,7 +33,7 @@ private class AllocationContext
public StackAllocator StackAlloc { get; }
- public BitMap Active { get; }
+ public BitMap Active { get; }
public BitMap Inactive { get; }
public int IntUsedRegisters { get; set; }
@@ -47,9 +47,9 @@ private class AllocationContext
public AllocationContext(StackAllocator stackAlloc, RegisterMasks masks, int intervalsCount)
{
StackAlloc = stackAlloc;
- Masks = masks;
+ Masks = masks;
- Active = new BitMap(Allocators.Default, intervalsCount);
+ Active = new BitMap(Allocators.Default, intervalsCount);
Inactive = new BitMap(Allocators.Default, intervalsCount);
PopulateFreePositions(RegisterType.Integer, out _intFreePositions, out _intFreePositionsCount);
@@ -443,7 +443,7 @@ private static int GetHighestValueIndex(Span span)
if (highest < current)
{
- highest = current;
+ highest = current;
selected = index;
if (current == int.MaxValue)
@@ -485,9 +485,9 @@ private void SplitAndSpillOverlappingIntervals(AllocationContext context, LiveIn
private void SplitAndSpillOverlappingInterval(
AllocationContext context,
- LiveInterval current,
- LiveInterval interval,
- int registersCount)
+ LiveInterval current,
+ LiveInterval interval,
+ int registersCount)
{
// If there's a next use after the start of the current interval,
// we need to split the spilled interval twice, and re-insert it
@@ -530,8 +530,8 @@ private void SplitAndSpillOverlappingInterval(
private void InsertInterval(LiveInterval interval, int registersCount)
{
Debug.Assert(interval.UsesCount != 0, "Trying to insert a interval without uses.");
- Debug.Assert(!interval.IsEmpty, "Trying to insert a empty interval.");
- Debug.Assert(!interval.IsSpilled, "Trying to insert a spilled interval.");
+ Debug.Assert(!interval.IsEmpty, "Trying to insert a empty interval.");
+ Debug.Assert(!interval.IsSpilled, "Trying to insert a spilled interval.");
int startIndex = registersCount * 2;
@@ -545,9 +545,9 @@ private void InsertInterval(LiveInterval interval, int registersCount)
_intervals.Insert(insertIndex, interval);
}
- private void Spill(AllocationContext context, LiveInterval interval)
+ private static void Spill(AllocationContext context, LiveInterval interval)
{
- Debug.Assert(!interval.IsFixed, "Trying to spill a fixed interval.");
+ Debug.Assert(!interval.IsFixed, "Trying to spill a fixed interval.");
Debug.Assert(interval.UsesCount == 0, "Trying to spill a interval with uses.");
// We first check if any of the siblings were spilled, if so we can reuse
@@ -561,7 +561,7 @@ private void Spill(AllocationContext context, LiveInterval interval)
private void InsertSplitCopies()
{
- Dictionary copyResolvers = new Dictionary();
+ Dictionary copyResolvers = new();
CopyResolver GetCopyResolver(int position)
{
@@ -668,18 +668,15 @@ bool IsSplitEdgeBlock(BasicBlock block)
continue;
}
- int lEnd = _blockRanges[block.Index].End - 1;
+ int lEnd = _blockRanges[block.Index].End - 1;
int rStart = _blockRanges[succIndex].Start;
- LiveInterval left = interval.GetSplitChild(lEnd);
+ LiveInterval left = interval.GetSplitChild(lEnd);
LiveInterval right = interval.GetSplitChild(rStart);
if (left != default && right != default && left != right)
{
- if (copyResolver == null)
- {
- copyResolver = new CopyResolver();
- }
+ copyResolver ??= new CopyResolver();
copyResolver.AddSplit(left, right);
}
@@ -856,14 +853,14 @@ private void BuildIntervals(ControlFlowGraph cfg, AllocationContext context)
int mapSize = _intervals.Count;
- BitMap[] blkLiveGen = new BitMap[cfg.Blocks.Count];
+ BitMap[] blkLiveGen = new BitMap[cfg.Blocks.Count];
BitMap[] blkLiveKill = new BitMap[cfg.Blocks.Count];
// Compute local live sets.
for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
{
- BitMap liveGen = new BitMap(Allocators.Default, mapSize);
- BitMap liveKill = new BitMap(Allocators.Default, mapSize);
+ BitMap liveGen = new(Allocators.Default, mapSize);
+ BitMap liveKill = new(Allocators.Default, mapSize);
for (Operation node = block.Operations.First; node != default; node = node.ListNext)
{
@@ -910,17 +907,17 @@ void VisitDestination(Operand dest)
}
}
- blkLiveGen [block.Index] = liveGen;
+ blkLiveGen[block.Index] = liveGen;
blkLiveKill[block.Index] = liveKill;
}
// Compute global live sets.
- BitMap[] blkLiveIn = new BitMap[cfg.Blocks.Count];
+ BitMap[] blkLiveIn = new BitMap[cfg.Blocks.Count];
BitMap[] blkLiveOut = new BitMap[cfg.Blocks.Count];
for (int index = 0; index < cfg.Blocks.Count; index++)
{
- blkLiveIn [index] = new BitMap(Allocators.Default, mapSize);
+ blkLiveIn[index] = new BitMap(Allocators.Default, mapSize);
blkLiveOut[index] = new BitMap(Allocators.Default, mapSize);
}
@@ -945,9 +942,9 @@ void VisitDestination(Operand dest)
BitMap liveIn = blkLiveIn[block.Index];
- liveIn.Set (liveOut);
+ liveIn.Set(liveOut);
liveIn.Clear(blkLiveKill[block.Index]);
- liveIn.Set (blkLiveGen [block.Index]);
+ liveIn.Set(blkLiveGen[block.Index]);
}
}
while (modified);
@@ -969,7 +966,7 @@ void VisitDestination(Operand dest)
int instCount = Math.Max(block.Operations.Count, 1);
int blockStart = operationPos - instCount * InstructionGap;
- int blockEnd = operationPos;
+ int blockEnd = operationPos;
_blockRanges[block.Index] = new LiveRange(blockStart, blockEnd);
@@ -1061,7 +1058,7 @@ private void AddIntervalCallerSavedReg(int mask, int operationPos, RegisterType
{
int regIndex = BitOperations.TrailingZeroCount(mask);
- Register callerSavedReg = new Register(regIndex, regType);
+ Register callerSavedReg = new(regIndex, regType);
LiveInterval interval = _intervals[GetRegisterId(callerSavedReg)];
@@ -1098,4 +1095,4 @@ private static bool IsLocalOrRegister(OperandKind kind)
kind == OperandKind.Register;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs
index d739ad281..333d3951b 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs
@@ -240,8 +240,10 @@ public int NextUseAfter(int position)
public LiveInterval Split(int position)
{
- LiveInterval result = new(Local, Parent);
- result.End = End;
+ LiveInterval result = new(Local, Parent)
+ {
+ End = End,
+ };
LiveRange prev = PrevRange;
LiveRange curr = CurrRange;
@@ -393,4 +395,4 @@ IEnumerable GetRanges()
return string.Join(", ", GetRanges());
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs
index 06b979ead..84b892f42 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
@@ -8,8 +8,8 @@ unsafe struct LiveIntervalList
private int _count;
private int _capacity;
- public int Count => _count;
- public Span Span => new(_items, _count);
+ public readonly int Count => _count;
+ public readonly Span Span => new(_items, _count);
public void Add(LiveInterval interval)
{
@@ -37,4 +37,4 @@ public void Add(LiveInterval interval)
_count++;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs
index e38b5190d..412d597e8 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs
@@ -71,4 +71,4 @@ public override string ToString()
return $"[{Start}, {End})";
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs
index bc948f95f..e6972cf0f 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs
@@ -5,8 +5,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
{
readonly struct RegisterMasks
{
- public int IntAvailableRegisters { get; }
- public int VecAvailableRegisters { get; }
+ public int IntAvailableRegisters { get; }
+ public int VecAvailableRegisters { get; }
public int IntCallerSavedRegisters { get; }
public int VecCallerSavedRegisters { get; }
public int IntCalleeSavedRegisters { get; }
@@ -22,13 +22,13 @@ public RegisterMasks(
int vecCalleeSavedRegisters,
int registersCount)
{
- IntAvailableRegisters = intAvailableRegisters;
- VecAvailableRegisters = vecAvailableRegisters;
+ IntAvailableRegisters = intAvailableRegisters;
+ VecAvailableRegisters = vecAvailableRegisters;
IntCallerSavedRegisters = intCallerSavedRegisters;
VecCallerSavedRegisters = vecCallerSavedRegisters;
IntCalleeSavedRegisters = intCalleeSavedRegisters;
VecCalleeSavedRegisters = vecCalleeSavedRegisters;
- RegistersCount = registersCount;
+ RegistersCount = registersCount;
}
public int GetAvailableRegisters(RegisterType type)
@@ -47,4 +47,4 @@ public int GetAvailableRegisters(RegisterType type)
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs
index 038312fed..13995bc8d 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs
@@ -22,4 +22,4 @@ public int Allocate(int sizeInBytes)
return offset;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs
index c89f0854d..806002f83 100644
--- a/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs
+++ b/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.CodeGen.RegisterAllocators
{
@@ -6,15 +6,15 @@ unsafe struct UseList
{
private int* _items;
private int _capacity;
- private int _count;
- public int Count => _count;
- public int FirstUse => _count > 0 ? _items[_count - 1] : LiveInterval.NotFound;
- public Span Span => new(_items, _count);
+ public int Count { get; private set; }
+
+ public readonly int FirstUse => Count > 0 ? _items[Count - 1] : LiveInterval.NotFound;
+ public readonly Span Span => new(_items, Count);
public void Add(int position)
{
- if (_count + 1 > _capacity)
+ if (Count + 1 > _capacity)
{
var oldSpan = Span;
@@ -28,7 +28,7 @@ public void Add(int position)
// Use positions are usually inserted in descending order, so inserting in descending order is faster,
// since the number of half exchanges is reduced.
- int i = _count - 1;
+ int i = Count - 1;
while (i >= 0 && _items[i] < position)
{
@@ -36,19 +36,19 @@ public void Add(int position)
}
_items[i + 1] = position;
- _count++;
+ Count++;
}
- public int NextUse(int position)
+ public readonly int NextUse(int position)
{
int index = NextUseIndex(position);
return index != LiveInterval.NotFound ? _items[index] : LiveInterval.NotFound;
}
- public int NextUseIndex(int position)
+ public readonly int NextUseIndex(int position)
{
- int i = _count - 1;
+ int i = Count - 1;
if (i == -1 || position > _items[0])
{
@@ -69,16 +69,18 @@ public UseList Split(int position)
// Since the list is in descending order, the new split list takes the front of the list and the current
// list takes the back of the list.
- UseList result = new();
- result._count = index + 1;
- result._capacity = result._count;
+ UseList result = new()
+ {
+ Count = index + 1,
+ };
+ result._capacity = result.Count;
result._items = _items;
- _count = _count - result._count;
- _capacity = _count;
- _items = _items + result._count;
+ Count -= result.Count;
+ _capacity = Count;
+ _items += result.Count;
return result;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs
index 3d0bc21d5..127b84231 100644
--- a/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs
+++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs
@@ -13,4 +13,4 @@ public UnwindInfo(UnwindPushEntry[] pushEntries, int prologSize)
PrologSize = prologSize;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs
index 4a8288a28..2045019a3 100644
--- a/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs
+++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs
@@ -2,10 +2,10 @@ namespace ARMeilleure.CodeGen.Unwinding
{
enum UnwindPseudoOp
{
- PushReg = 0,
- SetFrame = 1,
+ PushReg = 0,
+ SetFrame = 1,
AllocStack = 2,
- SaveReg = 3,
- SaveXmm128 = 4
+ SaveReg = 3,
+ SaveXmm128 = 4,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs
index fd8ea402b..507ace598 100644
--- a/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs
+++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs
@@ -17,4 +17,4 @@ public UnwindPushEntry(UnwindPseudoOp pseudoOp, int prologOffset, int regIndex =
StackOffsetOrAllocSize = stackOffsetOrAllocSize;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/Assembler.cs b/src/ARMeilleure/CodeGen/X86/Assembler.cs
index 67736a31f..55bf07248 100644
--- a/src/ARMeilleure/CodeGen/X86/Assembler.cs
+++ b/src/ARMeilleure/CodeGen/X86/Assembler.cs
@@ -15,7 +15,7 @@ partial class Assembler
private const int OpModRMBits = 24;
- private const byte RexPrefix = 0x40;
+ private const byte RexPrefix = 0x40;
private const byte RexWPrefix = 0x48;
private const byte LockPrefix = 0xf0;
@@ -799,7 +799,7 @@ private void WriteInstruction(Operand dest, Operand source, OperandType type, X8
{
JumpIndex = _jumps.Count - 1,
Position = (int)_stream.Position,
- Symbol = source.Symbol
+ Symbol = source.Symbol,
});
}
@@ -959,7 +959,7 @@ private void WriteOpCode(
}
}
- bool needsSibByte = false;
+ bool needsSibByte = false;
bool needsDisplacement = false;
int sib = 0;
@@ -971,7 +971,7 @@ private void WriteOpCode(
X86Register baseRegLow = (X86Register)(baseReg.Index & 0b111);
- needsSibByte = memOp.Index != default || baseRegLow == X86Register.Rsp;
+ needsSibByte = memOp.Index != default || baseRegLow == X86Register.Rsp;
needsDisplacement = memOp.Displacement != 0 || baseRegLow == X86Register.Rbp;
if (needsDisplacement)
@@ -1049,7 +1049,7 @@ private void WriteOpCode(
InstructionFlags.Prefix66 => 1,
InstructionFlags.PrefixF3 => 2,
InstructionFlags.PrefixF2 => 3,
- _ => 0
+ _ => 0,
};
if (src1 != default)
@@ -1081,11 +1081,19 @@ private void WriteOpCode(
switch (opCodeHigh)
{
- case 0xf: vexByte1 |= 1; break;
- case 0xf38: vexByte1 |= 2; break;
- case 0xf3a: vexByte1 |= 3; break;
+ case 0xf:
+ vexByte1 |= 1;
+ break;
+ case 0xf38:
+ vexByte1 |= 2;
+ break;
+ case 0xf3a:
+ vexByte1 |= 3;
+ break;
- default: Debug.Assert(false, $"Failed to VEX encode opcode 0x{opCode:X}."); break;
+ default:
+ Debug.Assert(false, $"Failed to VEX encode opcode 0x{opCode:X}.");
+ break;
}
vexByte2 |= (rexPrefix & 8) << 4;
@@ -1191,11 +1199,19 @@ private void WriteEvexInst(
switch ((ushort)(opCode >> 8))
{
- case 0xf00: mm = 0b01; break;
- case 0xf38: mm = 0b10; break;
- case 0xf3a: mm = 0b11; break;
+ case 0xf00:
+ mm = 0b01;
+ break;
+ case 0xf38:
+ mm = 0b10;
+ break;
+ case 0xf3a:
+ mm = 0b11;
+ break;
- default: Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}."); break;
+ default:
+ Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}.");
+ break;
}
WriteByte(
@@ -1217,7 +1233,7 @@ private void WriteEvexInst(
InstructionFlags.Prefix66 => 0b01,
InstructionFlags.PrefixF3 => 0b10,
InstructionFlags.PrefixF2 => 0b11,
- _ => 0
+ _ => 0,
};
WriteByte(
(byte)(
@@ -1233,11 +1249,19 @@ private void WriteEvexInst(
byte ll = 0b00;
switch (registerWidth)
{
- case 128: ll = 0b00; break;
- case 256: ll = 0b01; break;
- case 512: ll = 0b10; break;
+ case 128:
+ ll = 0b00;
+ break;
+ case 256:
+ ll = 0b01;
+ break;
+ case 512:
+ ll = 0b10;
+ break;
- default: Debug.Fail($"Invalid EVEX vector register width {registerWidth}."); break;
+ default:
+ Debug.Fail($"Invalid EVEX vector register width {registerWidth}.");
+ break;
}
// Embedded broadcast in the case of a memory operand
bool bcast = broadcast;
@@ -1315,10 +1339,7 @@ void SetRegisterHighBit(Register reg, int bit)
ref Jump jump = ref jumps[i];
// If jump target not resolved yet, resolve it.
- if (jump.JumpTarget == null)
- {
- jump.JumpTarget = _labels[jump.JumpLabel];
- }
+ jump.JumpTarget ??= _labels[jump.JumpLabel];
long jumpTarget = jump.JumpTarget.Value;
long offset = jumpTarget - jump.JumpPosition;
@@ -1556,4 +1577,4 @@ private void WriteUInt64(ulong value)
_stream.WriteByte((byte)(value >> 56));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs b/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs
index e6a2ff07f..8910e8891 100644
--- a/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs
+++ b/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs
@@ -1,4 +1,5 @@
-using System;
+using System;
+using System.Diagnostics.CodeAnalysis;
namespace ARMeilleure.CodeGen.X86
{
@@ -12,47 +13,48 @@ public static bool SupportsVexPrefix(X86Instruction inst)
private const int BadOp = 0;
[Flags]
+ [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
private enum InstructionFlags
{
- None = 0,
- RegOnly = 1 << 0,
- Reg8Src = 1 << 1,
+ None = 0,
+ RegOnly = 1 << 0,
+ Reg8Src = 1 << 1,
Reg8Dest = 1 << 2,
- RexW = 1 << 3,
- Vex = 1 << 4,
- Evex = 1 << 5,
+ RexW = 1 << 3,
+ Vex = 1 << 4,
+ Evex = 1 << 5,
- PrefixBit = 16,
+ PrefixBit = 16,
PrefixMask = 7 << PrefixBit,
- Prefix66 = 1 << PrefixBit,
- PrefixF3 = 2 << PrefixBit,
- PrefixF2 = 4 << PrefixBit
+ Prefix66 = 1 << PrefixBit,
+ PrefixF3 = 2 << PrefixBit,
+ PrefixF2 = 4 << PrefixBit,
}
private readonly struct InstructionInfo
{
- public int OpRMR { get; }
- public int OpRMImm8 { get; }
+ public int OpRMR { get; }
+ public int OpRMImm8 { get; }
public int OpRMImm32 { get; }
- public int OpRImm64 { get; }
- public int OpRRM { get; }
+ public int OpRImm64 { get; }
+ public int OpRRM { get; }
public InstructionFlags Flags { get; }
public InstructionInfo(
- int opRMR,
- int opRMImm8,
- int opRMImm32,
- int opRImm64,
- int opRRM,
+ int opRMR,
+ int opRMImm8,
+ int opRMImm32,
+ int opRImm64,
+ int opRRM,
InstructionFlags flags)
{
- OpRMR = opRMR;
- OpRMImm8 = opRMImm8;
+ OpRMR = opRMR;
+ OpRMImm8 = opRMImm8;
OpRMImm32 = opRMImm32;
- OpRImm64 = opRImm64;
- OpRRM = opRRM;
- Flags = flags;
+ OpRImm64 = opRImm64;
+ OpRRM = opRRM;
+ Flags = flags;
}
}
@@ -62,6 +64,7 @@ static Assembler()
{
_instTable = new InstructionInfo[(int)X86Instruction.Count];
+#pragma warning disable IDE0055 // Disable formatting
// Name RM/R RM/I8 RM/I32 R/I64 R/RM Flags
Add(X86Instruction.Add, new InstructionInfo(0x00000001, 0x00000083, 0x00000081, BadOp, 0x00000003, InstructionFlags.None));
Add(X86Instruction.Addpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f58, InstructionFlags.Vex | InstructionFlags.Prefix66));
@@ -285,6 +288,7 @@ static Assembler()
Add(X86Instruction.Xor, new InstructionInfo(0x00000031, 0x06000083, 0x06000081, BadOp, 0x00000033, InstructionFlags.None));
Add(X86Instruction.Xorpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex | InstructionFlags.Prefix66));
Add(X86Instruction.Xorps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex));
+#pragma warning restore IDE0055
static void Add(X86Instruction inst, in InstructionInfo info)
{
diff --git a/src/ARMeilleure/CodeGen/X86/CallConvName.cs b/src/ARMeilleure/CodeGen/X86/CallConvName.cs
index be3676282..6208da1ec 100644
--- a/src/ARMeilleure/CodeGen/X86/CallConvName.cs
+++ b/src/ARMeilleure/CodeGen/X86/CallConvName.cs
@@ -3,6 +3,6 @@ namespace ARMeilleure.CodeGen.X86
enum CallConvName
{
SystemV,
- Windows
+ Windows,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/CallingConvention.cs b/src/ARMeilleure/CodeGen/X86/CallingConvention.cs
index 953fef5b0..8433aaea9 100644
--- a/src/ARMeilleure/CodeGen/X86/CallingConvention.cs
+++ b/src/ARMeilleure/CodeGen/X86/CallingConvention.cs
@@ -20,6 +20,7 @@ public static int GetIntCallerSavedRegisters()
{
if (GetCurrentCallConv() == CallConvName.Windows)
{
+#pragma warning disable IDE0055 // Disable formatting
return (1 << (int)X86Register.Rax) |
(1 << (int)X86Register.Rcx) |
(1 << (int)X86Register.Rdx) |
@@ -39,6 +40,7 @@ public static int GetIntCallerSavedRegisters()
(1 << (int)X86Register.R9) |
(1 << (int)X86Register.R10) |
(1 << (int)X86Register.R11);
+#pragma warning restore IDE0055
}
}
@@ -90,22 +92,32 @@ public static X86Register GetIntArgumentRegister(int index)
{
switch (index)
{
- case 0: return X86Register.Rcx;
- case 1: return X86Register.Rdx;
- case 2: return X86Register.R8;
- case 3: return X86Register.R9;
+ case 0:
+ return X86Register.Rcx;
+ case 1:
+ return X86Register.Rdx;
+ case 2:
+ return X86Register.R8;
+ case 3:
+ return X86Register.R9;
}
}
else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
{
switch (index)
{
- case 0: return X86Register.Rdi;
- case 1: return X86Register.Rsi;
- case 2: return X86Register.Rdx;
- case 3: return X86Register.Rcx;
- case 4: return X86Register.R8;
- case 5: return X86Register.R9;
+ case 0:
+ return X86Register.Rdi;
+ case 1:
+ return X86Register.Rsi;
+ case 2:
+ return X86Register.Rdx;
+ case 3:
+ return X86Register.Rcx;
+ case 4:
+ return X86Register.R8;
+ case 5:
+ return X86Register.R9;
}
}
@@ -155,4 +167,4 @@ public static CallConvName GetCurrentCallConv()
: CallConvName.SystemV;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenCommon.cs b/src/ARMeilleure/CodeGen/X86/CodeGenCommon.cs
index 237ecee4e..ae83ea80c 100644
--- a/src/ARMeilleure/CodeGen/X86/CodeGenCommon.cs
+++ b/src/ARMeilleure/CodeGen/X86/CodeGenCommon.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.IntermediateRepresentation;
+using ARMeilleure.IntermediateRepresentation;
namespace ARMeilleure.CodeGen.X86
{
diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs b/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs
index 899487241..d4d4c2058 100644
--- a/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs
+++ b/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs
@@ -30,7 +30,7 @@ public CodeGenContext(AllocationResult allocResult, int maxCallArgs, int blocksC
Assembler = new Assembler(_stream, relocatable);
CallArgsRegionSize = GetCallArgsRegionSize(allocResult, maxCallArgs, out int xmmSaveRegionSize);
- XmmSaveRegionSize = xmmSaveRegionSize;
+ XmmSaveRegionSize = xmmSaveRegionSize;
}
private static int GetCallArgsRegionSize(AllocationResult allocResult, int maxCallArgs, out int xmmSaveRegionSize)
@@ -102,4 +102,4 @@ private Operand GetLabel(BasicBlock block)
return label;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs
index e7179b517..9e94a077f 100644
--- a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs
+++ b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs
@@ -17,7 +17,7 @@ namespace ARMeilleure.CodeGen.X86
static class CodeGenerator
{
private const int RegistersCount = 16;
- private const int PageSize = 0x1000;
+ private const int PageSize = 0x1000;
private const int StackGuardSize = 0x2000;
private static readonly Action[] _instTable;
@@ -26,6 +26,7 @@ static CodeGenerator()
{
_instTable = new Action[EnumUtils.GetCount(typeof(Instruction))];
+#pragma warning disable IDE0055 // Disable formatting
Add(Instruction.Add, GenerateAdd);
Add(Instruction.BitwiseAnd, GenerateBitwiseAnd);
Add(Instruction.BitwiseExclusiveOr, GenerateBitwiseExclusiveOr);
@@ -85,6 +86,7 @@ static CodeGenerator()
Add(Instruction.ZeroExtend16, GenerateZeroExtend16);
Add(Instruction.ZeroExtend32, GenerateZeroExtend32);
Add(Instruction.ZeroExtend8, GenerateZeroExtend8);
+#pragma warning restore IDE0055
static void Add(Instruction inst, Action func)
{
@@ -203,290 +205,290 @@ private static void GenerateOperation(CodeGenContext context, Operation operatio
switch (info.Type)
{
case IntrinsicType.Comis_:
- {
- Operand dest = operation.Destination;
- Operand src1 = operation.GetSource(0);
- Operand src2 = operation.GetSource(1);
-
- switch (operation.Intrinsic)
{
- case Intrinsic.X86Comisdeq:
- context.Assembler.Comisd(src1, src2);
- context.Assembler.Setcc(dest, X86Condition.Equal);
- break;
-
- case Intrinsic.X86Comisdge:
- context.Assembler.Comisd(src1, src2);
- context.Assembler.Setcc(dest, X86Condition.AboveOrEqual);
- break;
-
- case Intrinsic.X86Comisdlt:
- context.Assembler.Comisd(src1, src2);
- context.Assembler.Setcc(dest, X86Condition.Below);
- break;
-
- case Intrinsic.X86Comisseq:
- context.Assembler.Comiss(src1, src2);
- context.Assembler.Setcc(dest, X86Condition.Equal);
- break;
-
- case Intrinsic.X86Comissge:
- context.Assembler.Comiss(src1, src2);
- context.Assembler.Setcc(dest, X86Condition.AboveOrEqual);
- break;
-
- case Intrinsic.X86Comisslt:
- context.Assembler.Comiss(src1, src2);
- context.Assembler.Setcc(dest, X86Condition.Below);
- break;
- }
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
- context.Assembler.Movzx8(dest, dest, OperandType.I32);
+ switch (operation.Intrinsic)
+ {
+ case Intrinsic.X86Comisdeq:
+ context.Assembler.Comisd(src1, src2);
+ context.Assembler.Setcc(dest, X86Condition.Equal);
+ break;
+
+ case Intrinsic.X86Comisdge:
+ context.Assembler.Comisd(src1, src2);
+ context.Assembler.Setcc(dest, X86Condition.AboveOrEqual);
+ break;
+
+ case Intrinsic.X86Comisdlt:
+ context.Assembler.Comisd(src1, src2);
+ context.Assembler.Setcc(dest, X86Condition.Below);
+ break;
+
+ case Intrinsic.X86Comisseq:
+ context.Assembler.Comiss(src1, src2);
+ context.Assembler.Setcc(dest, X86Condition.Equal);
+ break;
+
+ case Intrinsic.X86Comissge:
+ context.Assembler.Comiss(src1, src2);
+ context.Assembler.Setcc(dest, X86Condition.AboveOrEqual);
+ break;
+
+ case Intrinsic.X86Comisslt:
+ context.Assembler.Comiss(src1, src2);
+ context.Assembler.Setcc(dest, X86Condition.Below);
+ break;
+ }
- break;
- }
+ context.Assembler.Movzx8(dest, dest, OperandType.I32);
+
+ break;
+ }
case IntrinsicType.Mxcsr:
- {
- Operand offset = operation.GetSource(0);
+ {
+ Operand offset = operation.GetSource(0);
- Debug.Assert(offset.Kind == OperandKind.Constant);
- Debug.Assert(offset.Type == OperandType.I32);
+ Debug.Assert(offset.Kind == OperandKind.Constant);
+ Debug.Assert(offset.Type == OperandType.I32);
- int offs = offset.AsInt32() + context.CallArgsRegionSize;
+ int offs = offset.AsInt32() + context.CallArgsRegionSize;
- Operand rsp = Register(X86Register.Rsp);
- Operand memOp = MemoryOp(OperandType.I32, rsp, default, Multiplier.x1, offs);
+ Operand rsp = Register(X86Register.Rsp);
+ Operand memOp = MemoryOp(OperandType.I32, rsp, default, Multiplier.x1, offs);
- Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding);
+ Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding);
- if (operation.Intrinsic == Intrinsic.X86Ldmxcsr)
- {
- Operand bits = operation.GetSource(1);
- Debug.Assert(bits.Type == OperandType.I32);
+ if (operation.Intrinsic == Intrinsic.X86Ldmxcsr)
+ {
+ Operand bits = operation.GetSource(1);
+ Debug.Assert(bits.Type == OperandType.I32);
- context.Assembler.Mov(memOp, bits, OperandType.I32);
- context.Assembler.Ldmxcsr(memOp);
- }
- else if (operation.Intrinsic == Intrinsic.X86Stmxcsr)
- {
- Operand dest = operation.Destination;
- Debug.Assert(dest.Type == OperandType.I32);
+ context.Assembler.Mov(memOp, bits, OperandType.I32);
+ context.Assembler.Ldmxcsr(memOp);
+ }
+ else if (operation.Intrinsic == Intrinsic.X86Stmxcsr)
+ {
+ Operand dest = operation.Destination;
+ Debug.Assert(dest.Type == OperandType.I32);
- context.Assembler.Stmxcsr(memOp);
- context.Assembler.Mov(dest, memOp, OperandType.I32);
- }
+ context.Assembler.Stmxcsr(memOp);
+ context.Assembler.Mov(dest, memOp, OperandType.I32);
+ }
- break;
- }
+ break;
+ }
case IntrinsicType.PopCount:
- {
- Operand dest = operation.Destination;
- Operand source = operation.GetSource(0);
+ {
+ Operand dest = operation.Destination;
+ Operand source = operation.GetSource(0);
- EnsureSameType(dest, source);
+ EnsureSameType(dest, source);
- Debug.Assert(dest.Type.IsInteger());
+ Debug.Assert(dest.Type.IsInteger());
- context.Assembler.Popcnt(dest, source, dest.Type);
+ context.Assembler.Popcnt(dest, source, dest.Type);
- break;
- }
+ break;
+ }
case IntrinsicType.Unary:
- {
- Operand dest = operation.Destination;
- Operand source = operation.GetSource(0);
+ {
+ Operand dest = operation.Destination;
+ Operand source = operation.GetSource(0);
- EnsureSameType(dest, source);
+ EnsureSameType(dest, source);
- Debug.Assert(!dest.Type.IsInteger());
+ Debug.Assert(!dest.Type.IsInteger());
- context.Assembler.WriteInstruction(info.Inst, dest, source);
+ context.Assembler.WriteInstruction(info.Inst, dest, source);
- break;
- }
+ break;
+ }
case IntrinsicType.UnaryToGpr:
- {
- Operand dest = operation.Destination;
- Operand source = operation.GetSource(0);
+ {
+ Operand dest = operation.Destination;
+ Operand source = operation.GetSource(0);
- Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger());
+ Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger());
- if (operation.Intrinsic == Intrinsic.X86Cvtsi2si)
- {
- if (dest.Type == OperandType.I32)
+ if (operation.Intrinsic == Intrinsic.X86Cvtsi2si)
{
- context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a)
+ if (dest.Type == OperandType.I32)
+ {
+ context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a)
+ }
+ else /* if (dest.Type == OperandType.I64) */
+ {
+ context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a)
+ }
}
- else /* if (dest.Type == OperandType.I64) */
+ else
{
- context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a)
+ context.Assembler.WriteInstruction(info.Inst, dest, source, dest.Type);
}
- }
- else
- {
- context.Assembler.WriteInstruction(info.Inst, dest, source, dest.Type);
- }
- break;
- }
+ break;
+ }
case IntrinsicType.Binary:
- {
- Operand dest = operation.Destination;
- Operand src1 = operation.GetSource(0);
- Operand src2 = operation.GetSource(1);
+ {
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
- EnsureSameType(dest, src1);
+ EnsureSameType(dest, src1);
- if (!HardwareCapabilities.SupportsVexEncoding)
- {
- EnsureSameReg(dest, src1);
- }
+ if (!HardwareCapabilities.SupportsVexEncoding)
+ {
+ EnsureSameReg(dest, src1);
+ }
- Debug.Assert(!dest.Type.IsInteger());
- Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant);
+ Debug.Assert(!dest.Type.IsInteger());
+ Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant);
- context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
+ context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
- break;
- }
+ break;
+ }
case IntrinsicType.BinaryGpr:
- {
- Operand dest = operation.Destination;
- Operand src1 = operation.GetSource(0);
- Operand src2 = operation.GetSource(1);
+ {
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
- EnsureSameType(dest, src1);
+ EnsureSameType(dest, src1);
- if (!HardwareCapabilities.SupportsVexEncoding)
- {
- EnsureSameReg(dest, src1);
- }
+ if (!HardwareCapabilities.SupportsVexEncoding)
+ {
+ EnsureSameReg(dest, src1);
+ }
- Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger());
+ Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger());
- context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type);
+ context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type);
- break;
- }
+ break;
+ }
case IntrinsicType.Crc32:
- {
- Operand dest = operation.Destination;
- Operand src1 = operation.GetSource(0);
- Operand src2 = operation.GetSource(1);
+ {
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
- EnsureSameReg(dest, src1);
+ EnsureSameReg(dest, src1);
- Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger());
+ Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger());
- context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type);
+ context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type);
- break;
- }
+ break;
+ }
case IntrinsicType.BinaryImm:
- {
- Operand dest = operation.Destination;
- Operand src1 = operation.GetSource(0);
- Operand src2 = operation.GetSource(1);
+ {
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
- EnsureSameType(dest, src1);
+ EnsureSameType(dest, src1);
- if (!HardwareCapabilities.SupportsVexEncoding)
- {
- EnsureSameReg(dest, src1);
- }
+ if (!HardwareCapabilities.SupportsVexEncoding)
+ {
+ EnsureSameReg(dest, src1);
+ }
- Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant);
+ Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant);
- context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte());
+ context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte());
- break;
- }
+ break;
+ }
case IntrinsicType.Ternary:
- {
- Operand dest = operation.Destination;
- Operand src1 = operation.GetSource(0);
- Operand src2 = operation.GetSource(1);
- Operand src3 = operation.GetSource(2);
+ {
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
+ Operand src3 = operation.GetSource(2);
- EnsureSameType(dest, src1, src2, src3);
+ EnsureSameType(dest, src1, src2, src3);
- Debug.Assert(!dest.Type.IsInteger());
+ Debug.Assert(!dest.Type.IsInteger());
- if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding)
- {
- context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3);
- }
- else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding)
- {
- context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3);
- }
- else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding)
- {
- context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3);
- }
- else
- {
- EnsureSameReg(dest, src1);
+ if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding)
+ {
+ context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3);
+ }
+ else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding)
+ {
+ context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3);
+ }
+ else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding)
+ {
+ context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3);
+ }
+ else
+ {
+ EnsureSameReg(dest, src1);
- Debug.Assert(src3.GetRegister().Index == 0);
+ Debug.Assert(src3.GetRegister().Index == 0);
- context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
- }
+ context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
+ }
- break;
- }
+ break;
+ }
case IntrinsicType.TernaryImm:
- {
- Operand dest = operation.Destination;
- Operand src1 = operation.GetSource(0);
- Operand src2 = operation.GetSource(1);
- Operand src3 = operation.GetSource(2);
+ {
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
+ Operand src3 = operation.GetSource(2);
- EnsureSameType(dest, src1, src2);
+ EnsureSameType(dest, src1, src2);
- if (!HardwareCapabilities.SupportsVexEncoding)
- {
- EnsureSameReg(dest, src1);
- }
+ if (!HardwareCapabilities.SupportsVexEncoding)
+ {
+ EnsureSameReg(dest, src1);
+ }
- Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant);
+ Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant);
- context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte());
+ context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte());
- break;
- }
+ break;
+ }
case IntrinsicType.Fma:
- {
- Operand dest = operation.Destination;
- Operand src1 = operation.GetSource(0);
- Operand src2 = operation.GetSource(1);
- Operand src3 = operation.GetSource(2);
+ {
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
+ Operand src3 = operation.GetSource(2);
- Debug.Assert(HardwareCapabilities.SupportsVexEncoding);
+ Debug.Assert(HardwareCapabilities.SupportsVexEncoding);
- Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register);
- Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory);
+ Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register);
+ Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory);
- EnsureSameType(dest, src1, src2, src3);
- Debug.Assert(dest.Type == OperandType.V128);
+ EnsureSameType(dest, src1, src2, src3);
+ Debug.Assert(dest.Type == OperandType.V128);
- Debug.Assert(dest.Value == src1.Value);
+ Debug.Assert(dest.Value == src1.Value);
- context.Assembler.WriteInstruction(info.Inst, dest, src2, src3);
+ context.Assembler.WriteInstruction(info.Inst, dest, src2, src3);
- break;
- }
+ break;
+ }
}
}
else
@@ -592,7 +594,7 @@ private static void GenerateBitwiseExclusiveOr(CodeGenContext context, Operation
private static void GenerateBitwiseNot(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
ValidateUnOp(dest, source);
@@ -630,7 +632,7 @@ private static void GenerateBranchIf(CodeGenContext context, Operation operation
private static void GenerateByteSwap(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
ValidateUnOp(dest, source);
@@ -761,19 +763,19 @@ private static void GenerateConditionalSelect(CodeGenContext context, Operation
Operand src2 = operation.GetSource(1);
Operand src3 = operation.GetSource(2);
- EnsureSameReg (dest, src3);
+ EnsureSameReg(dest, src3);
EnsureSameType(dest, src2, src3);
Debug.Assert(dest.Type.IsInteger());
Debug.Assert(src1.Type == OperandType.I32);
- context.Assembler.Test (src1, src1, src1.Type);
+ context.Assembler.Test(src1, src1, src1.Type);
context.Assembler.Cmovcc(dest, src2, dest.Type, X86Condition.NotEqual);
}
private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64);
@@ -783,7 +785,7 @@ private static void GenerateConvertI64ToI32(CodeGenContext context, Operation op
private static void GenerateConvertToFP(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
@@ -794,7 +796,7 @@ private static void GenerateConvertToFP(CodeGenContext context, Operation operat
if (source.Type.IsInteger())
{
- context.Assembler.Xorps (dest, dest, dest);
+ context.Assembler.Xorps(dest, dest, dest);
context.Assembler.Cvtsi2ss(dest, dest, source, source.Type);
}
else /* if (source.Type == OperandType.FP64) */
@@ -810,7 +812,7 @@ private static void GenerateConvertToFP(CodeGenContext context, Operation operat
if (source.Type.IsInteger())
{
- context.Assembler.Xorps (dest, dest, dest);
+ context.Assembler.Xorps(dest, dest, dest);
context.Assembler.Cvtsi2sd(dest, dest, source, source.Type);
}
else /* if (source.Type == OperandType.FP32) */
@@ -824,7 +826,7 @@ private static void GenerateConvertToFP(CodeGenContext context, Operation operat
private static void GenerateCopy(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
EnsureSameType(dest, source);
@@ -837,7 +839,7 @@ private static void GenerateCopy(CodeGenContext context, Operation operation)
return;
}
- if (dest.Kind == OperandKind.Register &&
+ if (dest.Kind == OperandKind.Register &&
source.Kind == OperandKind.Constant && source.Value == 0)
{
// Assemble "mov reg, 0" as "xor reg, reg" as the later is more efficient.
@@ -855,7 +857,7 @@ private static void GenerateCopy(CodeGenContext context, Operation operation)
private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
EnsureSameType(dest, source);
@@ -888,9 +890,9 @@ private static void GenerateCountLeadingZeros(CodeGenContext context, Operation
private static void GenerateDivide(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand dividend = operation.GetSource(0);
- Operand divisor = operation.GetSource(1);
+ Operand divisor = operation.GetSource(1);
if (!dest.Type.IsInteger())
{
@@ -938,7 +940,7 @@ private static void GenerateDivideUI(CodeGenContext context, Operation operation
private static void GenerateFill(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand offset = operation.GetSource(0);
Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -954,7 +956,7 @@ private static void GenerateFill(CodeGenContext context, Operation operation)
private static void GenerateLoad(CodeGenContext context, Operation operation)
{
- Operand value = operation.Destination;
+ Operand value = operation.Destination;
Operand address = Memory(operation.GetSource(0), value.Type);
GenerateLoad(context, address, value);
@@ -962,7 +964,7 @@ private static void GenerateLoad(CodeGenContext context, Operation operation)
private static void GenerateLoad16(CodeGenContext context, Operation operation)
{
- Operand value = operation.Destination;
+ Operand value = operation.Destination;
Operand address = Memory(operation.GetSource(0), value.Type);
Debug.Assert(value.Type.IsInteger());
@@ -972,7 +974,7 @@ private static void GenerateLoad16(CodeGenContext context, Operation operation)
private static void GenerateLoad8(CodeGenContext context, Operation operation)
{
- Operand value = operation.Destination;
+ Operand value = operation.Destination;
Operand address = Memory(operation.GetSource(0), value.Type);
Debug.Assert(value.Type.IsInteger());
@@ -1039,7 +1041,7 @@ private static void GenerateMultiply64HighUI(CodeGenContext context, Operation o
private static void GenerateNegate(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
ValidateUnOp(dest, source);
@@ -1102,7 +1104,7 @@ private static void GenerateShiftRightUI(CodeGenContext context, Operation opera
private static void GenerateSignExtend16(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1112,7 +1114,7 @@ private static void GenerateSignExtend16(CodeGenContext context, Operation opera
private static void GenerateSignExtend32(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1122,7 +1124,7 @@ private static void GenerateSignExtend32(CodeGenContext context, Operation opera
private static void GenerateSignExtend8(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1158,7 +1160,7 @@ private static void GenerateSpill(CodeGenContext context, Operation operation, i
private static void GenerateStackAlloc(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand offset = operation.GetSource(0);
Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -1174,7 +1176,7 @@ private static void GenerateStackAlloc(CodeGenContext context, Operation operati
private static void GenerateStore(CodeGenContext context, Operation operation)
{
- Operand value = operation.GetSource(1);
+ Operand value = operation.GetSource(1);
Operand address = Memory(operation.GetSource(0), value.Type);
GenerateStore(context, address, value);
@@ -1182,7 +1184,7 @@ private static void GenerateStore(CodeGenContext context, Operation operation)
private static void GenerateStore16(CodeGenContext context, Operation operation)
{
- Operand value = operation.GetSource(1);
+ Operand value = operation.GetSource(1);
Operand address = Memory(operation.GetSource(0), value.Type);
Debug.Assert(value.Type.IsInteger());
@@ -1192,7 +1194,7 @@ private static void GenerateStore16(CodeGenContext context, Operation operation)
private static void GenerateStore8(CodeGenContext context, Operation operation)
{
- Operand value = operation.GetSource(1);
+ Operand value = operation.GetSource(1);
Operand address = Memory(operation.GetSource(0), value.Type);
Debug.Assert(value.Type.IsInteger());
@@ -1231,7 +1233,7 @@ private static void GenerateTailcall(CodeGenContext context, Operation operation
private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(!dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1278,7 +1280,7 @@ private static void GenerateVectorExtract(CodeGenContext context, Operation oper
mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8);
context.Assembler.Pshufd(src1, src1, (byte)mask0);
- context.Assembler.Movd (dest, src1);
+ context.Assembler.Movd(dest, src1);
context.Assembler.Pshufd(src1, src1, (byte)mask1);
}
}
@@ -1294,11 +1296,11 @@ private static void GenerateVectorExtract(CodeGenContext context, Operation oper
}
else
{
- const byte mask = 0b01_00_11_10;
+ const byte Mask = 0b01_00_11_10;
- context.Assembler.Pshufd(src1, src1, mask);
- context.Assembler.Movq (dest, src1);
- context.Assembler.Pshufd(src1, src1, mask);
+ context.Assembler.Pshufd(src1, src1, Mask);
+ context.Assembler.Movq(dest, src1);
+ context.Assembler.Pshufd(src1, src1, Mask);
}
}
else
@@ -1308,7 +1310,7 @@ private static void GenerateVectorExtract(CodeGenContext context, Operation oper
(index == 1 && dest.Type == OperandType.FP64))
{
context.Assembler.Movhlps(dest, dest, src1);
- context.Assembler.Movq (dest, dest);
+ context.Assembler.Movq(dest, dest);
}
else
{
@@ -1455,11 +1457,11 @@ void InsertIntSse2(int words)
int mask0 = 0b11_10_01_00;
int mask1 = 0b11_10_01_00;
- mask0 = BitUtils.RotateRight(mask0, index * 2, 8);
+ mask0 = BitUtils.RotateRight(mask0, index * 2, 8);
mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8);
context.Assembler.Pshufd(src1, src1, (byte)mask0); // Lane to be inserted in position 0.
- context.Assembler.Movss (dest, src1, src2); // dest[127:0] = src1[127:32] | src2[31:0]
+ context.Assembler.Movss(dest, src1, src2); // dest[127:0] = src1[127:32] | src2[31:0]
context.Assembler.Pshufd(dest, dest, (byte)mask1); // Inserted lane in original position.
if (dest.GetRegister() != src1.GetRegister())
@@ -1555,7 +1557,7 @@ private static void GenerateVectorZero(CodeGenContext context, Operation operati
private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1565,7 +1567,7 @@ private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation
private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1575,7 +1577,7 @@ private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation
private static void GenerateZeroExtend16(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1585,7 +1587,7 @@ private static void GenerateZeroExtend16(CodeGenContext context, Operation opera
private static void GenerateZeroExtend32(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1601,7 +1603,7 @@ private static void GenerateZeroExtend32(CodeGenContext context, Operation opera
private static void GenerateZeroExtend8(CodeGenContext context, Operation operation)
{
- Operand dest = operation.Destination;
+ Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1613,13 +1615,25 @@ private static void GenerateLoad(CodeGenContext context, Operand address, Operan
{
switch (value.Type)
{
- case OperandType.I32: context.Assembler.Mov (value, address, OperandType.I32); break;
- case OperandType.I64: context.Assembler.Mov (value, address, OperandType.I64); break;
- case OperandType.FP32: context.Assembler.Movd (value, address); break;
- case OperandType.FP64: context.Assembler.Movq (value, address); break;
- case OperandType.V128: context.Assembler.Movdqu(value, address); break;
-
- default: Debug.Assert(false); break;
+ case OperandType.I32:
+ context.Assembler.Mov(value, address, OperandType.I32);
+ break;
+ case OperandType.I64:
+ context.Assembler.Mov(value, address, OperandType.I64);
+ break;
+ case OperandType.FP32:
+ context.Assembler.Movd(value, address);
+ break;
+ case OperandType.FP64:
+ context.Assembler.Movq(value, address);
+ break;
+ case OperandType.V128:
+ context.Assembler.Movdqu(value, address);
+ break;
+
+ default:
+ Debug.Assert(false);
+ break;
}
}
@@ -1627,13 +1641,25 @@ private static void GenerateStore(CodeGenContext context, Operand address, Opera
{
switch (value.Type)
{
- case OperandType.I32: context.Assembler.Mov (address, value, OperandType.I32); break;
- case OperandType.I64: context.Assembler.Mov (address, value, OperandType.I64); break;
- case OperandType.FP32: context.Assembler.Movd (address, value); break;
- case OperandType.FP64: context.Assembler.Movq (address, value); break;
- case OperandType.V128: context.Assembler.Movdqu(address, value); break;
-
- default: Debug.Assert(false); break;
+ case OperandType.I32:
+ context.Assembler.Mov(address, value, OperandType.I32);
+ break;
+ case OperandType.I64:
+ context.Assembler.Mov(address, value, OperandType.I64);
+ break;
+ case OperandType.FP32:
+ context.Assembler.Movd(address, value);
+ break;
+ case OperandType.FP64:
+ context.Assembler.Movq(address, value);
+ break;
+ case OperandType.V128:
+ context.Assembler.Movdqu(address, value);
+ break;
+
+ default:
+ Debug.Assert(false);
+ break;
}
}
@@ -1670,21 +1696,21 @@ private static bool MatchOperation(Operation node, Instruction inst, OperandType
[Conditional("DEBUG")]
private static void ValidateUnOp(Operand dest, Operand source)
{
- EnsureSameReg (dest, source);
+ EnsureSameReg(dest, source);
EnsureSameType(dest, source);
}
[Conditional("DEBUG")]
private static void ValidateBinOp(Operand dest, Operand src1, Operand src2)
{
- EnsureSameReg (dest, src1);
+ EnsureSameReg(dest, src1);
EnsureSameType(dest, src1, src2);
}
[Conditional("DEBUG")]
private static void ValidateShift(Operand dest, Operand src1, Operand src2)
{
- EnsureSameReg (dest, src1);
+ EnsureSameReg(dest, src1);
EnsureSameType(dest, src1);
Debug.Assert(dest.Type.IsInteger() && src2.Type == OperandType.I32);
@@ -1722,7 +1748,7 @@ private static void EnsureSameType(Operand op1, Operand op2, Operand op3, Operan
private static UnwindInfo WritePrologue(CodeGenContext context)
{
- List pushEntries = new List();
+ List pushEntries = new();
Operand rsp = Register(X86Register.Rsp);
@@ -1827,11 +1853,11 @@ private static void GenerateInlineStackProbe(CodeGenContext context, int size)
// that the OS will map all pages that we'll use. We do that by
// doing a dummy read on those pages, forcing a page fault and
// the OS to map them. If they are already mapped, nothing happens.
- const int pageMask = PageSize - 1;
+ const int PageMask = PageSize - 1;
- size = (size + pageMask) & ~pageMask;
+ size = (size + PageMask) & ~PageMask;
- Operand rsp = Register(X86Register.Rsp);
+ Operand rsp = Register(X86Register.Rsp);
Operand temp = Register(CallingConvention.GetIntReturnRegister());
for (int offset = PageSize; offset < size; offset += PageSize)
@@ -1862,4 +1888,4 @@ private static Operand Xmm(X86Register register)
return Operand.Factory.Register((int)register, RegisterType.Vector, OperandType.V128);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs b/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs
index 07cdcd096..4f6f1e87b 100644
--- a/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs
+++ b/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs
@@ -47,7 +47,7 @@ private static uint GetXcr0Eax()
0xc3, // ret
};
- using MemoryBlock memGetXcr0 = new MemoryBlock((ulong)asmGetXcr0.Length);
+ using MemoryBlock memGetXcr0 = new((ulong)asmGetXcr0.Length);
memGetXcr0.Write(0, asmGetXcr0);
@@ -62,7 +62,7 @@ private static uint GetXcr0Eax()
public enum FeatureFlags1Edx
{
Sse = 1 << 25,
- Sse2 = 1 << 26
+ Sse2 = 1 << 26,
}
[Flags]
@@ -79,7 +79,7 @@ public enum FeatureFlags1Ecx
Xsave = 1 << 26,
Osxsave = 1 << 27,
Avx = 1 << 28,
- F16c = 1 << 29
+ F16c = 1 << 29,
}
[Flags]
@@ -90,7 +90,7 @@ public enum FeatureFlags7Ebx
Avx512dq = 1 << 17,
Sha = 1 << 29,
Avx512bw = 1 << 30,
- Avx512vl = 1 << 31
+ Avx512vl = 1 << 31,
}
[Flags]
@@ -106,7 +106,7 @@ public enum Xcr0FlagsEax
YmmHi128 = 1 << 2,
Opmask = 1 << 5,
ZmmHi256 = 1 << 6,
- Hi16Zmm = 1 << 7
+ Hi16Zmm = 1 << 7,
}
public static FeatureFlags1Edx FeatureInfo1Edx { get; }
@@ -141,4 +141,4 @@ public enum Xcr0FlagsEax
public static bool SupportsVexEncoding => SupportsAvx && !ForceLegacySse;
public static bool SupportsEvexEncoding => SupportsAvx512F && !ForceLegacySse;
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs
index 302bf4d3c..16054c616 100644
--- a/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs
+++ b/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs
@@ -3,7 +3,7 @@ namespace ARMeilleure.CodeGen.X86
readonly struct IntrinsicInfo
{
public X86Instruction Inst { get; }
- public IntrinsicType Type { get; }
+ public IntrinsicType Type { get; }
public IntrinsicInfo(X86Instruction inst, IntrinsicType type)
{
@@ -11,4 +11,4 @@ public IntrinsicInfo(X86Instruction inst, IntrinsicType type)
Type = type;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs
index e3d94b7ae..daa1f8f60 100644
--- a/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs
+++ b/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs
@@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.X86
{
static class IntrinsicTable
{
- private static IntrinsicInfo[] _intrinTable;
+ private static readonly IntrinsicInfo[] _intrinTable;
static IntrinsicTable()
{
_intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))];
+#pragma warning disable IDE0055 // Disable formatting
Add(Intrinsic.X86Addpd, new IntrinsicInfo(X86Instruction.Addpd, IntrinsicType.Binary));
Add(Intrinsic.X86Addps, new IntrinsicInfo(X86Instruction.Addps, IntrinsicType.Binary));
Add(Intrinsic.X86Addsd, new IntrinsicInfo(X86Instruction.Addsd, IntrinsicType.Binary));
@@ -185,6 +186,7 @@ static IntrinsicTable()
Add(Intrinsic.X86Vpternlogd, new IntrinsicInfo(X86Instruction.Vpternlogd, IntrinsicType.TernaryImm));
Add(Intrinsic.X86Xorpd, new IntrinsicInfo(X86Instruction.Xorpd, IntrinsicType.Binary));
Add(Intrinsic.X86Xorps, new IntrinsicInfo(X86Instruction.Xorps, IntrinsicType.Binary));
+#pragma warning restore IDE0055
}
private static void Add(Intrinsic intrin, IntrinsicInfo info)
@@ -197,4 +199,4 @@ public static IntrinsicInfo GetInfo(Intrinsic intrin)
return _intrinTable[(int)intrin];
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs
index 5a9c14afa..7c3ef354d 100644
--- a/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs
+++ b/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs
@@ -13,6 +13,6 @@ enum IntrinsicType
Crc32,
Ternary,
TernaryImm,
- Fma
+ Fma,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/Mxcsr.cs b/src/ARMeilleure/CodeGen/X86/Mxcsr.cs
index c61eac31a..719afe59e 100644
--- a/src/ARMeilleure/CodeGen/X86/Mxcsr.cs
+++ b/src/ARMeilleure/CodeGen/X86/Mxcsr.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.CodeGen.X86
{
@@ -10,6 +10,6 @@ enum Mxcsr
Rlo = 1 << 13, // Round Mode low bit.
Um = 1 << 11, // Underflow Mask.
Dm = 1 << 8, // Denormal Mask.
- Daz = 1 << 6 // Denormals Are Zero.
+ Daz = 1 << 6, // Denormals Are Zero.
}
}
diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocator.cs b/src/ARMeilleure/CodeGen/X86/PreAllocator.cs
index cb742d67f..590c35c7b 100644
--- a/src/ARMeilleure/CodeGen/X86/PreAllocator.cs
+++ b/src/ARMeilleure/CodeGen/X86/PreAllocator.cs
@@ -104,11 +104,11 @@ public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out
case Instruction.Tailcall:
if (callConv == CallConvName.Windows)
{
- PreAllocatorWindows.InsertTailcallCopies(block.Operations, stackAlloc, node);
+ PreAllocatorWindows.InsertTailcallCopies(block.Operations, node);
}
else
{
- PreAllocatorSystemV.InsertTailcallCopies(block.Operations, stackAlloc, node);
+ PreAllocatorSystemV.InsertTailcallCopies(block.Operations, node);
}
break;
@@ -177,10 +177,7 @@ protected static void InsertConstantRegCopies(IntrusiveList nodes, Op
{
src2 = node.GetSource(1);
- Operand temp = src1;
-
- src1 = src2;
- src2 = temp;
+ (src2, src1) = (src1, src2);
node.SetSource(0, src1);
node.SetSource(1, src2);
@@ -228,151 +225,151 @@ protected static void InsertConstrainedRegCopies(IntrusiveList nodes,
case Instruction.CompareAndSwap:
case Instruction.CompareAndSwap16:
case Instruction.CompareAndSwap8:
- {
- OperandType type = node.GetSource(1).Type;
-
- if (type == OperandType.V128)
{
- // Handle the many restrictions of the compare and exchange (16 bytes) instruction:
- // - The expected value should be in RDX:RAX.
- // - The new value to be written should be in RCX:RBX.
- // - The value at the memory location is loaded to RDX:RAX.
- void SplitOperand(Operand source, Operand lr, Operand hr)
+ OperandType type = node.GetSource(1).Type;
+
+ if (type == OperandType.V128)
{
- nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0)));
- nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1)));
- }
+ // Handle the many restrictions of the compare and exchange (16 bytes) instruction:
+ // - The expected value should be in RDX:RAX.
+ // - The new value to be written should be in RCX:RBX.
+ // - The value at the memory location is loaded to RDX:RAX.
+ void SplitOperand(Operand source, Operand lr, Operand hr)
+ {
+ nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0)));
+ nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1)));
+ }
- Operand rax = Gpr(X86Register.Rax, OperandType.I64);
- Operand rbx = Gpr(X86Register.Rbx, OperandType.I64);
- Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
- Operand rdx = Gpr(X86Register.Rdx, OperandType.I64);
+ Operand rax = Gpr(X86Register.Rax, OperandType.I64);
+ Operand rbx = Gpr(X86Register.Rbx, OperandType.I64);
+ Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
+ Operand rdx = Gpr(X86Register.Rdx, OperandType.I64);
- SplitOperand(node.GetSource(1), rax, rdx);
- SplitOperand(node.GetSource(2), rbx, rcx);
+ SplitOperand(node.GetSource(1), rax, rdx);
+ SplitOperand(node.GetSource(2), rbx, rcx);
- Operation operation = node;
+ Operation operation = node;
- node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax));
- nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1)));
+ node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax));
+ nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1)));
- operation.SetDestinations(new Operand[] { rdx, rax });
- operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx });
- }
- else
- {
- // Handle the many restrictions of the compare and exchange (32/64) instruction:
- // - The expected value should be in (E/R)AX.
- // - The value at the memory location is loaded to (E/R)AX.
- Operand expected = node.GetSource(1);
- Operand newValue = node.GetSource(2);
+ operation.SetDestinations(new Operand[] { rdx, rax });
+ operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx });
+ }
+ else
+ {
+ // Handle the many restrictions of the compare and exchange (32/64) instruction:
+ // - The expected value should be in (E/R)AX.
+ // - The value at the memory location is loaded to (E/R)AX.
+ Operand expected = node.GetSource(1);
+ Operand newValue = node.GetSource(2);
- Operand rax = Gpr(X86Register.Rax, expected.Type);
+ Operand rax = Gpr(X86Register.Rax, expected.Type);
- nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected));
+ nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected));
- // We need to store the new value into a temp, since it may
- // be a constant, and this instruction does not support immediate operands.
- Operand temp = Local(newValue.Type);
+ // We need to store the new value into a temp, since it may
+ // be a constant, and this instruction does not support immediate operands.
+ Operand temp = Local(newValue.Type);
- nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue));
+ nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue));
- node.SetSources(new Operand[] { node.GetSource(0), rax, temp });
+ node.SetSources(new Operand[] { node.GetSource(0), rax, temp });
- nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
+ nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
- node.Destination = rax;
- }
+ node.Destination = rax;
+ }
- break;
- }
+ break;
+ }
case Instruction.Divide:
case Instruction.DivideUI:
- {
- // Handle the many restrictions of the division instructions:
- // - The dividend is always in RDX:RAX.
- // - The result is always in RAX.
- // - Additionally it also writes the remainder in RDX.
- if (dest.Type.IsInteger())
{
- Operand src1 = node.GetSource(0);
+ // Handle the many restrictions of the division instructions:
+ // - The dividend is always in RDX:RAX.
+ // - The result is always in RAX.
+ // - Additionally it also writes the remainder in RDX.
+ if (dest.Type.IsInteger())
+ {
+ Operand src1 = node.GetSource(0);
- Operand rax = Gpr(X86Register.Rax, src1.Type);
- Operand rdx = Gpr(X86Register.Rdx, src1.Type);
+ Operand rax = Gpr(X86Register.Rax, src1.Type);
+ Operand rdx = Gpr(X86Register.Rdx, src1.Type);
- nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
- nodes.AddBefore(node, Operation(Instruction.Clobber, rdx));
+ nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
+ nodes.AddBefore(node, Operation(Instruction.Clobber, rdx));
- nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
+ nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
- node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) });
- node.Destination = rax;
- }
+ node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) });
+ node.Destination = rax;
+ }
- break;
- }
+ break;
+ }
case Instruction.Extended:
- {
- bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd ||
+ {
+ bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd ||
node.Intrinsic == Intrinsic.X86Blendvps ||
node.Intrinsic == Intrinsic.X86Pblendvb;
- // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported.
- // SHA256RNDS2 always has an implied XMM0 as a last operand.
- if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2)
- {
- Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128);
+ // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported.
+ // SHA256RNDS2 always has an implied XMM0 as a last operand.
+ if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2)
+ {
+ Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128);
- nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2)));
+ nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2)));
- node.SetSource(2, xmm0);
- }
+ node.SetSource(2, xmm0);
+ }
- break;
- }
+ break;
+ }
case Instruction.Multiply64HighSI:
case Instruction.Multiply64HighUI:
- {
- // Handle the many restrictions of the i64 * i64 = i128 multiply instructions:
- // - The multiplicand is always in RAX.
- // - The lower 64-bits of the result is always in RAX.
- // - The higher 64-bits of the result is always in RDX.
- Operand src1 = node.GetSource(0);
+ {
+ // Handle the many restrictions of the i64 * i64 = i128 multiply instructions:
+ // - The multiplicand is always in RAX.
+ // - The lower 64-bits of the result is always in RAX.
+ // - The higher 64-bits of the result is always in RDX.
+ Operand src1 = node.GetSource(0);
- Operand rax = Gpr(X86Register.Rax, src1.Type);
- Operand rdx = Gpr(X86Register.Rdx, src1.Type);
+ Operand rax = Gpr(X86Register.Rax, src1.Type);
+ Operand rdx = Gpr(X86Register.Rdx, src1.Type);
- nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
+ nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
- node.SetSource(0, rax);
+ node.SetSource(0, rax);
- nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx));
+ nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx));
- node.SetDestinations(new Operand[] { rdx, rax });
+ node.SetDestinations(new Operand[] { rdx, rax });
- break;
- }
+ break;
+ }
case Instruction.RotateRight:
case Instruction.ShiftLeft:
case Instruction.ShiftRightSI:
case Instruction.ShiftRightUI:
- {
- // The shift register is always implied to be CL (low 8-bits of RCX or ECX).
- if (node.GetSource(1).Kind == OperandKind.LocalVariable)
{
- Operand rcx = Gpr(X86Register.Rcx, OperandType.I32);
+ // The shift register is always implied to be CL (low 8-bits of RCX or ECX).
+ if (node.GetSource(1).Kind == OperandKind.LocalVariable)
+ {
+ Operand rcx = Gpr(X86Register.Rcx, OperandType.I32);
- nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1)));
+ nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1)));
- node.SetSource(1, rcx);
- }
+ node.SetSource(1, rcx);
+ }
- break;
- }
+ break;
+ }
}
}
@@ -459,7 +456,7 @@ private static void GenerateConvertToFPUI(IntrusiveList nodes, Operat
// Unsigned integer to FP conversions are not supported on X86.
// We need to turn them into signed integer to FP conversions, and
// adjust the final result.
- Operand dest = node.Destination;
+ Operand dest = node.Destination;
Operand source = node.GetSource(0);
Debug.Assert(source.Type.IsInteger(), $"Invalid source type \"{source.Type}\".");
@@ -472,8 +469,8 @@ private static void GenerateConvertToFPUI(IntrusiveList nodes, Operat
// and then use the 64-bits signed conversion instructions.
Operand zex = Local(OperandType.I64);
- node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source));
- node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex));
+ node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source));
+ nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex));
}
else /* if (source.Type == OperandType.I64) */
{
@@ -487,15 +484,15 @@ private static void GenerateConvertToFPUI(IntrusiveList nodes, Operat
// --- This can be done efficiently by adding the result to itself.
// -- Then, we need to add the least significant bit that was shifted out.
// --- We can convert the least significant bit to float, and add it to the result.
- Operand lsb = Local(OperandType.I64);
+ Operand lsb = Local(OperandType.I64);
Operand half = Local(OperandType.I64);
Operand lsbF = Local(dest.Type);
- node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source));
+ node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source));
node = nodes.AddAfter(node, Operation(Instruction.Copy, half, source));
- node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L)));
+ node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L)));
node = nodes.AddAfter(node, Operation(Instruction.ShiftRightUI, half, half, Const(1)));
node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, lsbF, lsb));
@@ -513,7 +510,7 @@ private static void GenerateNegate(IntrusiveList nodes, Operation nod
// There's no SSE FP negate instruction, so we need to transform that into
// a XOR of the value to be negated with a mask with the highest bit set.
// This also produces -0 for a negation of the value 0.
- Operand dest = node.Destination;
+ Operand dest = node.Destination;
Operand source = node.GetSource(0);
Debug.Assert(dest.Type == OperandType.FP32 ||
@@ -569,14 +566,14 @@ private static void GenerateVectorInsert8(IntrusiveList nodes, Operat
if ((index & 1) != 0)
{
node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp1, temp1));
- node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8)));
- node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
+ node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8)));
+ node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
}
else
{
node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp2, temp2));
- node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00)));
- node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
+ node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00)));
+ node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
}
Operation vinsOp = Operation(Instruction.VectorInsert16, dest, src1, temp1, Const(index >> 1));
@@ -709,16 +706,11 @@ private static bool IsVexSameOperandDestSrc1(Operation operation)
private static bool HasConstSrc1(Instruction inst)
{
- switch (inst)
+ return inst switch
{
- case Instruction.Copy:
- case Instruction.LoadArgument:
- case Instruction.Spill:
- case Instruction.SpillArg:
- return true;
- }
-
- return false;
+ Instruction.Copy or Instruction.LoadArgument or Instruction.Spill or Instruction.SpillArg => true,
+ _ => false,
+ };
}
private static bool HasConstSrc2(Instruction inst)
@@ -762,15 +754,15 @@ private static bool IsCommutative(Operation operation)
case Instruction.BranchIf:
case Instruction.Compare:
- {
- Operand comp = operation.GetSource(2);
+ {
+ Operand comp = operation.GetSource(2);
- Debug.Assert(comp.Kind == OperandKind.Constant);
+ Debug.Assert(comp.Kind == OperandKind.Constant);
- var compType = (Comparison)comp.AsInt32();
+ var compType = (Comparison)comp.AsInt32();
- return compType == Comparison.Equal || compType == Comparison.NotEqual;
- }
+ return compType == Comparison.Equal || compType == Comparison.NotEqual;
+ }
}
return false;
@@ -793,4 +785,4 @@ private static bool IsXmmIntrinsic(Operation operation)
return info.Type != IntrinsicType.Crc32;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs b/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs
index a84d5050d..e754cb09b 100644
--- a/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs
+++ b/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs
@@ -1,4 +1,3 @@
-using ARMeilleure.CodeGen.RegisterAllocators;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System;
@@ -15,9 +14,9 @@ public static void InsertCallCopies(IntrusiveList nodes, Operation no
{
Operand dest = node.Destination;
- List sources = new List
+ List sources = new()
{
- node.GetSource(0)
+ node.GetSource(0),
};
int argsCount = node.SourcesCount - 1;
@@ -52,10 +51,10 @@ public static void InsertCallCopies(IntrusiveList nodes, Operation no
if (source.Type == OperandType.V128 && passOnReg)
{
// V128 is a struct, we pass each half on a GPR if possible.
- Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
+ Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
- nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0)));
+ nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0)));
nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg2, source, Const(1)));
continue;
@@ -91,7 +90,7 @@ public static void InsertCallCopies(IntrusiveList nodes, Operation no
{
if (dest.Type == OperandType.V128)
{
- Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
+ Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
Operation operation = node;
@@ -116,11 +115,11 @@ public static void InsertCallCopies(IntrusiveList nodes, Operation no
}
}
- public static void InsertTailcallCopies(IntrusiveList nodes, StackAllocator stackAlloc, Operation node)
+ public static void InsertTailcallCopies(IntrusiveList nodes, Operation node)
{
- List sources = new List
+ List sources = new()
{
- node.GetSource(0)
+ node.GetSource(0),
};
int argsCount = node.SourcesCount - 1;
@@ -251,11 +250,11 @@ public static Operation InsertLoadArgumentCopy(
// V128 is a struct, we pass each half on a GPR if possible.
Operand pArg = Local(OperandType.V128);
- Operand argLReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount), OperandType.I64);
+ Operand argLReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount), OperandType.I64);
Operand argHReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount + 1), OperandType.I64);
Operation copyL = Operation(Instruction.VectorCreateScalar, pArg, argLReg);
- Operation copyH = Operation(Instruction.VectorInsert, pArg, pArg, argHReg, Const(1));
+ Operation copyH = Operation(Instruction.VectorInsert, pArg, pArg, argHReg, Const(1));
cctx.Cfg.Entry.Operations.AddFirst(copyH);
cctx.Cfg.Entry.Operations.AddFirst(copyL);
@@ -313,7 +312,7 @@ public static void InsertReturnCopy(IntrusiveList nodes, Operation no
if (source.Type == OperandType.V128)
{
- Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
+ Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0)));
@@ -331,4 +330,4 @@ public static void InsertReturnCopy(IntrusiveList nodes, Operation no
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs b/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs
index 45319e6a5..10a2bd129 100644
--- a/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs
+++ b/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs
@@ -155,7 +155,7 @@ int AllocateOnStack(int size)
node.SetSources(sources);
}
- public static void InsertTailcallCopies(IntrusiveList nodes, StackAllocator stackAlloc, Operation node)
+ public static void InsertTailcallCopies(IntrusiveList nodes, Operation node)
{
int argsCount = node.SourcesCount - 1;
int maxArgs = CallingConvention.GetArgumentsOnRegsCount();
@@ -324,4 +324,4 @@ public static void InsertReturnCopy(
node.SetSources(Array.Empty());
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/X86Condition.cs b/src/ARMeilleure/CodeGen/X86/X86Condition.cs
index c82cbdec5..70699a207 100644
--- a/src/ARMeilleure/CodeGen/X86/X86Condition.cs
+++ b/src/ARMeilleure/CodeGen/X86/X86Condition.cs
@@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.X86
{
enum X86Condition
{
- Overflow = 0x0,
- NotOverflow = 0x1,
- Below = 0x2,
- AboveOrEqual = 0x3,
- Equal = 0x4,
- NotEqual = 0x5,
- BelowOrEqual = 0x6,
- Above = 0x7,
- Sign = 0x8,
- NotSign = 0x9,
- ParityEven = 0xa,
- ParityOdd = 0xb,
- Less = 0xc,
+ Overflow = 0x0,
+ NotOverflow = 0x1,
+ Below = 0x2,
+ AboveOrEqual = 0x3,
+ Equal = 0x4,
+ NotEqual = 0x5,
+ BelowOrEqual = 0x6,
+ Above = 0x7,
+ Sign = 0x8,
+ NotSign = 0x9,
+ ParityEven = 0xa,
+ ParityOdd = 0xb,
+ Less = 0xc,
GreaterOrEqual = 0xd,
- LessOrEqual = 0xe,
- Greater = 0xf
+ LessOrEqual = 0xe,
+ Greater = 0xf,
}
static class ComparisonX86Extensions
@@ -29,6 +29,7 @@ public static X86Condition ToX86Condition(this Comparison comp)
{
return comp switch
{
+#pragma warning disable IDE0055 // Disable formatting
Comparison.Equal => X86Condition.Equal,
Comparison.NotEqual => X86Condition.NotEqual,
Comparison.Greater => X86Condition.Greater,
@@ -39,9 +40,10 @@ public static X86Condition ToX86Condition(this Comparison comp)
Comparison.Less => X86Condition.Less,
Comparison.GreaterOrEqualUI => X86Condition.AboveOrEqual,
Comparison.LessUI => X86Condition.Below,
+#pragma warning restore IDE0055
- _ => throw new ArgumentException(null, nameof(comp))
+ _ => throw new ArgumentException(null, nameof(comp)),
};
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/X86Instruction.cs b/src/ARMeilleure/CodeGen/X86/X86Instruction.cs
index 9a85c516f..e1979011d 100644
--- a/src/ARMeilleure/CodeGen/X86/X86Instruction.cs
+++ b/src/ARMeilleure/CodeGen/X86/X86Instruction.cs
@@ -226,6 +226,6 @@ enum X86Instruction
Xorpd,
Xorps,
- Count
+ Count,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs b/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs
index 98a19b9a2..690ca5043 100644
--- a/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs
+++ b/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.CodeGen.Optimizations;
+using ARMeilleure.CodeGen.Optimizations;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System.Collections.Generic;
@@ -215,7 +215,7 @@ private static (Operand, Multiplier) GetIndexOp(ref Operand baseOp)
1 => Multiplier.x2,
2 => Multiplier.x4,
3 => Multiplier.x8,
- _ => Multiplier.x1
+ _ => Multiplier.x1,
};
baseOp = indexOnSrc2 ? src1 : src2;
diff --git a/src/ARMeilleure/CodeGen/X86/X86Register.cs b/src/ARMeilleure/CodeGen/X86/X86Register.cs
index 01f63e311..0a6563663 100644
--- a/src/ARMeilleure/CodeGen/X86/X86Register.cs
+++ b/src/ARMeilleure/CodeGen/X86/X86Register.cs
@@ -1,5 +1,8 @@
+using System.Diagnostics.CodeAnalysis;
+
namespace ARMeilleure.CodeGen.X86
{
+ [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
enum X86Register
{
Invalid = -1,
@@ -12,8 +15,8 @@ enum X86Register
Rbp = 5,
Rsi = 6,
Rdi = 7,
- R8 = 8,
- R9 = 9,
+ R8 = 8,
+ R9 = 9,
R10 = 10,
R11 = 11,
R12 = 12,
@@ -21,21 +24,21 @@ enum X86Register
R14 = 14,
R15 = 15,
- Xmm0 = 0,
- Xmm1 = 1,
- Xmm2 = 2,
- Xmm3 = 3,
- Xmm4 = 4,
- Xmm5 = 5,
- Xmm6 = 6,
- Xmm7 = 7,
- Xmm8 = 8,
- Xmm9 = 9,
+ Xmm0 = 0,
+ Xmm1 = 1,
+ Xmm2 = 2,
+ Xmm3 = 3,
+ Xmm4 = 4,
+ Xmm5 = 5,
+ Xmm6 = 6,
+ Xmm7 = 7,
+ Xmm8 = 8,
+ Xmm9 = 9,
Xmm10 = 10,
Xmm11 = 11,
Xmm12 = 12,
Xmm13 = 13,
Xmm14 = 14,
- Xmm15 = 15
+ Xmm15 = 15,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Common/AddressTable.cs b/src/ARMeilleure/Common/AddressTable.cs
index 9db2d00de..fcab3a202 100644
--- a/src/ARMeilleure/Common/AddressTable.cs
+++ b/src/ARMeilleure/Common/AddressTable.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Diagnostics;
+using ARMeilleure.Diagnostics;
using System;
using System.Collections.Generic;
using System.Runtime.InteropServices;
@@ -9,7 +9,7 @@ namespace ARMeilleure.Common
/// Represents a table of guest address to a value.
///
/// Type of the value
- unsafe class AddressTable : IDisposable where TEntry : unmanaged
+ public unsafe class AddressTable : IDisposable where TEntry : unmanaged
{
///
/// Represents a level in an .
diff --git a/src/ARMeilleure/Common/Allocator.cs b/src/ARMeilleure/Common/Allocator.cs
index 247a8e8bc..6905a614f 100644
--- a/src/ARMeilleure/Common/Allocator.cs
+++ b/src/ARMeilleure/Common/Allocator.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.Common
{
diff --git a/src/ARMeilleure/Common/ArenaAllocator.cs b/src/ARMeilleure/Common/ArenaAllocator.cs
index bce6794ad..ce8e33913 100644
--- a/src/ARMeilleure/Common/ArenaAllocator.cs
+++ b/src/ARMeilleure/Common/ArenaAllocator.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
using System.Collections.Generic;
using System.Runtime.CompilerServices;
@@ -82,8 +82,10 @@ public Span AllocateSpan(ulong count) where T : unmanaged
}
else
{
- _page = new PageInfo();
- _page.Pointer = (byte*)NativeAllocator.Instance.Allocate(_pageSize);
+ _page = new PageInfo
+ {
+ Pointer = (byte*)NativeAllocator.Instance.Allocate(_pageSize),
+ };
_pages.Add(_page);
}
@@ -106,7 +108,7 @@ public void Reset()
// Free excess pages that was allocated.
while (_pages.Count > _pageCount)
{
- NativeAllocator.Instance.Free(_pages[_pages.Count - 1].Pointer);
+ NativeAllocator.Instance.Free(_pages[^1].Pointer);
_pages.RemoveAt(_pages.Count - 1);
}
@@ -125,12 +127,13 @@ public void Reset()
// If arena is used frequently, keep pages for longer. Otherwise keep pages for a shorter amount of time.
int now = Environment.TickCount;
- int count = (now - _lastReset) switch {
+ int count = (now - _lastReset) switch
+ {
>= 5000 => 0,
>= 2500 => 50,
>= 1000 => 100,
- >= 10 => 1500,
- _ => 5000
+ >= 10 => 1500,
+ _ => 5000,
};
for (int i = _pages.Count - 1; i >= 0; i--)
diff --git a/src/ARMeilleure/Common/BitMap.cs b/src/ARMeilleure/Common/BitMap.cs
index 27ef031f3..94d47ea59 100644
--- a/src/ARMeilleure/Common/BitMap.cs
+++ b/src/ARMeilleure/Common/BitMap.cs
@@ -138,7 +138,7 @@ private void EnsureCapacity(int size)
var newSpan = new Span(_masks, _count);
oldSpan.CopyTo(newSpan);
- newSpan.Slice(oldSpan.Length).Clear();
+ newSpan[oldSpan.Length..].Clear();
_allocator.Free(oldMask);
}
@@ -176,8 +176,8 @@ public struct Enumerator : IEnumerator
private int _bit;
private readonly BitMap _map;
- public int Current => (int)_index * IntSize + _bit;
- object IEnumerator.Current => Current;
+ public readonly int Current => (int)_index * IntSize + _bit;
+ readonly object IEnumerator.Current => Current;
public Enumerator(BitMap map)
{
@@ -214,9 +214,9 @@ public bool MoveNext()
return true;
}
- public void Reset() { }
+ public readonly void Reset() { }
- public void Dispose() { }
+ public readonly void Dispose() { }
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Common/Counter.cs b/src/ARMeilleure/Common/Counter.cs
index d7210d159..6db9561ca 100644
--- a/src/ARMeilleure/Common/Counter.cs
+++ b/src/ARMeilleure/Common/Counter.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.Common
{
diff --git a/src/ARMeilleure/Common/EntryTable.cs b/src/ARMeilleure/Common/EntryTable.cs
index 6f2057979..625e3f73f 100644
--- a/src/ARMeilleure/Common/EntryTable.cs
+++ b/src/ARMeilleure/Common/EntryTable.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
using System.Collections.Generic;
using System.Numerics;
diff --git a/src/ARMeilleure/Common/NativeAllocator.cs b/src/ARMeilleure/Common/NativeAllocator.cs
index 71c04a9b1..93c48adda 100644
--- a/src/ARMeilleure/Common/NativeAllocator.cs
+++ b/src/ARMeilleure/Common/NativeAllocator.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
using System.Runtime.InteropServices;
namespace ARMeilleure.Common
diff --git a/src/ARMeilleure/Decoders/Block.cs b/src/ARMeilleure/Decoders/Block.cs
index f296d299d..bb88170da 100644
--- a/src/ARMeilleure/Decoders/Block.cs
+++ b/src/ARMeilleure/Decoders/Block.cs
@@ -5,10 +5,10 @@ namespace ARMeilleure.Decoders
{
class Block
{
- public ulong Address { get; set; }
+ public ulong Address { get; set; }
public ulong EndAddress { get; set; }
- public Block Next { get; set; }
+ public Block Next { get; set; }
public Block Branch { get; set; }
public bool Exit { get; set; }
@@ -43,14 +43,14 @@ public void Split(Block rightBlock)
rightBlock.EndAddress = EndAddress;
- rightBlock.Next = Next;
+ rightBlock.Next = Next;
rightBlock.Branch = Branch;
rightBlock.OpCodes.AddRange(OpCodes.GetRange(splitIndex, splitCount));
EndAddress = rightBlock.Address;
- Next = rightBlock;
+ Next = rightBlock;
Branch = null;
OpCodes.RemoveRange(splitIndex, splitCount);
@@ -58,9 +58,9 @@ public void Split(Block rightBlock)
private static int BinarySearch(List opCodes, ulong address)
{
- int left = 0;
+ int left = 0;
int middle = 0;
- int right = opCodes.Count - 1;
+ int right = opCodes.Count - 1;
while (left <= right)
{
@@ -92,10 +92,10 @@ public OpCode GetLastOp()
{
if (OpCodes.Count > 0)
{
- return OpCodes[OpCodes.Count - 1];
+ return OpCodes[^1];
}
return null;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/Condition.cs b/src/ARMeilleure/Decoders/Condition.cs
index 727f897da..961825a10 100644
--- a/src/ARMeilleure/Decoders/Condition.cs
+++ b/src/ARMeilleure/Decoders/Condition.cs
@@ -2,22 +2,22 @@ namespace ARMeilleure.Decoders
{
enum Condition
{
- Eq = 0,
- Ne = 1,
+ Eq = 0,
+ Ne = 1,
GeUn = 2,
LtUn = 3,
- Mi = 4,
- Pl = 5,
- Vs = 6,
- Vc = 7,
+ Mi = 4,
+ Pl = 5,
+ Vs = 6,
+ Vc = 7,
GtUn = 8,
LeUn = 9,
- Ge = 10,
- Lt = 11,
- Gt = 12,
- Le = 13,
- Al = 14,
- Nv = 15
+ Ge = 10,
+ Lt = 11,
+ Gt = 12,
+ Le = 13,
+ Al = 14,
+ Nv = 15,
}
static class ConditionExtensions
@@ -29,4 +29,4 @@ public static Condition Invert(this Condition cond)
return (Condition)((int)cond ^ 1);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/DataOp.cs b/src/ARMeilleure/Decoders/DataOp.cs
index 464d00898..f99fd5e70 100644
--- a/src/ARMeilleure/Decoders/DataOp.cs
+++ b/src/ARMeilleure/Decoders/DataOp.cs
@@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{
enum DataOp
{
- Adr = 0,
+ Adr = 0,
Arithmetic = 1,
- Logical = 2,
- BitField = 3
+ Logical = 2,
+ BitField = 3,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/Decoder.cs b/src/ARMeilleure/Decoders/Decoder.cs
index 426465aaa..66d286928 100644
--- a/src/ARMeilleure/Decoders/Decoder.cs
+++ b/src/ARMeilleure/Decoders/Decoder.cs
@@ -20,11 +20,11 @@ static class Decoder
public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, DecoderMode dMode)
{
- List blocks = new List();
+ List blocks = new();
- Queue workQueue = new Queue();
+ Queue workQueue = new();
- Dictionary visited = new Dictionary();
+ Dictionary visited = new();
Debug.Assert(MaxInstsPerFunctionLowCq <= MaxInstsPerFunction);
@@ -38,7 +38,9 @@ Block GetBlock(ulong blkAddress)
{
block = new Block(blkAddress);
- if ((dMode != DecoderMode.MultipleBlocks && visited.Count >= 1) || opsCount > instructionLimit || !memory.IsMapped(blkAddress))
+ if ((dMode != DecoderMode.MultipleBlocks && visited.Count >= 1) ||
+ opsCount > instructionLimit ||
+ (visited.Count > 0 && !memory.IsMapped(blkAddress)))
{
block.Exit = true;
block.EndAddress = blkAddress;
@@ -163,7 +165,7 @@ public static bool BinarySearch(List blocks, ulong address, out int index
{
index = 0;
- int left = 0;
+ int left = 0;
int right = blocks.Count - 1;
while (left <= right)
@@ -196,9 +198,9 @@ public static bool BinarySearch(List blocks, ulong address, out int index
private static void FillBlock(
IMemoryManager memory,
- ExecutionMode mode,
- Block block,
- ulong limitAddress)
+ ExecutionMode mode,
+ Block block,
+ ulong limitAddress)
{
ulong address = block.Address;
int itBlockSize = 0;
@@ -241,12 +243,12 @@ private static bool IsBranch(OpCode opCode)
private static bool IsUnconditionalBranch(OpCode opCode)
{
return opCode is OpCodeBImmAl ||
- opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
+ opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
}
private static bool IsAarch32UnconditionalBranch(OpCode opCode)
{
- if (!(opCode is OpCode32 op))
+ if (opCode is not OpCode32 op)
{
return false;
}
@@ -290,9 +292,9 @@ private static bool IsAarch32Branch(OpCode opCode)
if (opCode is IOpCode32Mem opMem)
{
- rt = opMem.Rt;
- rn = opMem.Rn;
- wBack = opMem.WBack;
+ rt = opMem.Rt;
+ rn = opMem.Rn;
+ wBack = opMem.WBack;
isLoad = opMem.IsLoad;
// For the dual load, we also need to take into account the
@@ -304,12 +306,12 @@ private static bool IsAarch32Branch(OpCode opCode)
}
else if (opCode is IOpCode32MemMult opMemMult)
{
- const int pcMask = 1 << RegisterAlias.Aarch32Pc;
+ const int PCMask = 1 << RegisterAlias.Aarch32Pc;
- rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
- rn = opMemMult.Rn;
- wBack = opMemMult.PostOffset != 0;
- isLoad = opMemMult.IsLoad;
+ rt = (opMemMult.RegisterMask & PCMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
+ rn = opMemMult.Rn;
+ wBack = opMemMult.PostOffset != 0;
+ isLoad = opMemMult.IsLoad;
}
else
{
@@ -388,4 +390,4 @@ public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, Executio
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/DecoderHelper.cs b/src/ARMeilleure/Decoders/DecoderHelper.cs
index 5227e6a19..35e573955 100644
--- a/src/ARMeilleure/Decoders/DecoderHelper.cs
+++ b/src/ARMeilleure/Decoders/DecoderHelper.cs
@@ -10,7 +10,7 @@ static DecoderHelper()
Imm8ToFP64Table = BuildImm8ToFP64Table();
}
- public static readonly uint[] Imm8ToFP32Table;
+ public static readonly uint[] Imm8ToFP32Table;
public static readonly ulong[] Imm8ToFP64Table;
private static uint[] BuildImm8ToFP32Table()
@@ -40,47 +40,47 @@ private static ulong[] BuildImm8ToFP64Table()
// abcdefgh -> aBbbbbbc defgh000 00000000 00000000 (B = ~b)
private static uint ExpandImm8ToFP32(uint imm)
{
- uint MoveBit(uint bits, int from, int to)
+ static uint MoveBit(uint bits, int from, int to)
{
return ((bits >> from) & 1U) << to;
}
return MoveBit(imm, 7, 31) | MoveBit(~imm, 6, 30) |
- MoveBit(imm, 6, 29) | MoveBit( imm, 6, 28) |
- MoveBit(imm, 6, 27) | MoveBit( imm, 6, 26) |
- MoveBit(imm, 6, 25) | MoveBit( imm, 5, 24) |
- MoveBit(imm, 4, 23) | MoveBit( imm, 3, 22) |
- MoveBit(imm, 2, 21) | MoveBit( imm, 1, 20) |
+ MoveBit(imm, 6, 29) | MoveBit(imm, 6, 28) |
+ MoveBit(imm, 6, 27) | MoveBit(imm, 6, 26) |
+ MoveBit(imm, 6, 25) | MoveBit(imm, 5, 24) |
+ MoveBit(imm, 4, 23) | MoveBit(imm, 3, 22) |
+ MoveBit(imm, 2, 21) | MoveBit(imm, 1, 20) |
MoveBit(imm, 0, 19);
}
// abcdefgh -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = ~b)
private static ulong ExpandImm8ToFP64(ulong imm)
{
- ulong MoveBit(ulong bits, int from, int to)
+ static ulong MoveBit(ulong bits, int from, int to)
{
return ((bits >> from) & 1UL) << to;
}
return MoveBit(imm, 7, 63) | MoveBit(~imm, 6, 62) |
- MoveBit(imm, 6, 61) | MoveBit( imm, 6, 60) |
- MoveBit(imm, 6, 59) | MoveBit( imm, 6, 58) |
- MoveBit(imm, 6, 57) | MoveBit( imm, 6, 56) |
- MoveBit(imm, 6, 55) | MoveBit( imm, 6, 54) |
- MoveBit(imm, 5, 53) | MoveBit( imm, 4, 52) |
- MoveBit(imm, 3, 51) | MoveBit( imm, 2, 50) |
- MoveBit(imm, 1, 49) | MoveBit( imm, 0, 48);
+ MoveBit(imm, 6, 61) | MoveBit(imm, 6, 60) |
+ MoveBit(imm, 6, 59) | MoveBit(imm, 6, 58) |
+ MoveBit(imm, 6, 57) | MoveBit(imm, 6, 56) |
+ MoveBit(imm, 6, 55) | MoveBit(imm, 6, 54) |
+ MoveBit(imm, 5, 53) | MoveBit(imm, 4, 52) |
+ MoveBit(imm, 3, 51) | MoveBit(imm, 2, 50) |
+ MoveBit(imm, 1, 49) | MoveBit(imm, 0, 48);
}
public struct BitMask
{
public long WMask;
public long TMask;
- public int Pos;
- public int Shift;
+ public int Pos;
+ public int Shift;
public bool IsUndefined;
- public static BitMask Invalid => new BitMask { IsUndefined = true };
+ public static BitMask Invalid => new() { IsUndefined = true };
}
public static BitMask DecodeBitMask(int opCode, bool immediate)
@@ -88,7 +88,7 @@ public static BitMask DecodeBitMask(int opCode, bool immediate)
int immS = (opCode >> 10) & 0x3f;
int immR = (opCode >> 16) & 0x3f;
- int n = (opCode >> 22) & 1;
+ int n = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1;
int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6));
@@ -115,7 +115,7 @@ public static BitMask DecodeBitMask(int opCode, bool immediate)
if (r > 0)
{
- wMask = BitUtils.RotateRight(wMask, r, size);
+ wMask = BitUtils.RotateRight(wMask, r, size);
wMask &= BitUtils.FillWithOnes(size);
}
@@ -124,8 +124,8 @@ public static BitMask DecodeBitMask(int opCode, bool immediate)
WMask = BitUtils.Replicate(wMask, size),
TMask = BitUtils.Replicate(tMask, size),
- Pos = immS,
- Shift = immR
+ Pos = immS,
+ Shift = immR,
};
}
@@ -164,4 +164,4 @@ public static bool VectorArgumentsInvalid(bool q, params int[] args)
return false;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/DecoderMode.cs b/src/ARMeilleure/Decoders/DecoderMode.cs
index 553620847..708d5c8fb 100644
--- a/src/ARMeilleure/Decoders/DecoderMode.cs
+++ b/src/ARMeilleure/Decoders/DecoderMode.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
enum DecoderMode
{
@@ -6,4 +6,4 @@ enum DecoderMode
SingleBlock,
SingleInstruction,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode.cs b/src/ARMeilleure/Decoders/IOpCode.cs
index 37ba7a4c6..9d5e3bf7a 100644
--- a/src/ARMeilleure/Decoders/IOpCode.cs
+++ b/src/ARMeilleure/Decoders/IOpCode.cs
@@ -14,4 +14,4 @@ interface IOpCode
OperandType GetOperandType();
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32.cs b/src/ARMeilleure/Decoders/IOpCode32.cs
index 126c10690..578925dee 100644
--- a/src/ARMeilleure/Decoders/IOpCode32.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32.cs
@@ -6,4 +6,4 @@ interface IOpCode32 : IOpCode
uint GetPc();
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32Alu.cs b/src/ARMeilleure/Decoders/IOpCode32Alu.cs
index 69fee164c..a85ef44ad 100644
--- a/src/ARMeilleure/Decoders/IOpCode32Alu.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32Alu.cs
@@ -5,4 +5,4 @@ interface IOpCode32Alu : IOpCode32, IOpCode32HasSetFlags
int Rd { get; }
int Rn { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32AluBf.cs b/src/ARMeilleure/Decoders/IOpCode32AluBf.cs
index 206c2965e..d1fe59039 100644
--- a/src/ARMeilleure/Decoders/IOpCode32AluBf.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32AluBf.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32AluBf
{
diff --git a/src/ARMeilleure/Decoders/IOpCode32AluImm.cs b/src/ARMeilleure/Decoders/IOpCode32AluImm.cs
index 342fb8f6c..b89990187 100644
--- a/src/ARMeilleure/Decoders/IOpCode32AluImm.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32AluImm.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32AluImm : IOpCode32Alu
{
@@ -6,4 +6,4 @@ interface IOpCode32AluImm : IOpCode32Alu
bool IsRotated { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs b/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs
index cd128f657..dd42a70b1 100644
--- a/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs
@@ -4,4 +4,4 @@ interface IOpCode32AluImm16 : IOpCode32Alu
{
int Immediate { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32AluReg.cs b/src/ARMeilleure/Decoders/IOpCode32AluReg.cs
index 1612cc5c9..1a35e664c 100644
--- a/src/ARMeilleure/Decoders/IOpCode32AluReg.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32AluReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32AluReg : IOpCode32Alu
{
diff --git a/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs b/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs
index e899a6592..37a2c1000 100644
--- a/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32AluRsImm : IOpCode32Alu
{
@@ -7,4 +7,4 @@ interface IOpCode32AluRsImm : IOpCode32Alu
ShiftType ShiftType { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs b/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs
index 879db0593..ed9859fc0 100644
--- a/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32AluRsReg : IOpCode32Alu
{
@@ -7,4 +7,4 @@ interface IOpCode32AluRsReg : IOpCode32Alu
ShiftType ShiftType { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32AluUx.cs b/src/ARMeilleure/Decoders/IOpCode32AluUx.cs
index d03c7e219..d390f6b81 100644
--- a/src/ARMeilleure/Decoders/IOpCode32AluUx.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32AluUx.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32AluUx : IOpCode32AluReg
{
diff --git a/src/ARMeilleure/Decoders/IOpCode32BImm.cs b/src/ARMeilleure/Decoders/IOpCode32BImm.cs
index ec7db2c26..8d22d5c40 100644
--- a/src/ARMeilleure/Decoders/IOpCode32BImm.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32BImm.cs
@@ -1,4 +1,4 @@
namespace ARMeilleure.Decoders
{
interface IOpCode32BImm : IOpCode32, IOpCodeBImm { }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32BReg.cs b/src/ARMeilleure/Decoders/IOpCode32BReg.cs
index 097ab4275..9badc9858 100644
--- a/src/ARMeilleure/Decoders/IOpCode32BReg.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32BReg.cs
@@ -4,4 +4,4 @@ interface IOpCode32BReg : IOpCode32
{
int Rm { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32Exception.cs b/src/ARMeilleure/Decoders/IOpCode32Exception.cs
index 8f0fb81a0..c38af9078 100644
--- a/src/ARMeilleure/Decoders/IOpCode32Exception.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32Exception.cs
@@ -1,7 +1,7 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32Exception
{
int Id { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs b/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs
index 71ca6d19c..fd9337d9b 100644
--- a/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs
@@ -1,7 +1,7 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32HasSetFlags
{
bool? SetFlags { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32Mem.cs b/src/ARMeilleure/Decoders/IOpCode32Mem.cs
index 6664ddffd..a34bc0e2a 100644
--- a/src/ARMeilleure/Decoders/IOpCode32Mem.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32Mem.cs
@@ -13,4 +13,4 @@ interface IOpCode32Mem : IOpCode32
int Immediate { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32MemEx.cs b/src/ARMeilleure/Decoders/IOpCode32MemEx.cs
index aca7200a5..5f6b9321e 100644
--- a/src/ARMeilleure/Decoders/IOpCode32MemEx.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32MemEx.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32MemEx : IOpCode32Mem
{
diff --git a/src/ARMeilleure/Decoders/IOpCode32MemMult.cs b/src/ARMeilleure/Decoders/IOpCode32MemMult.cs
index 4b891bc1b..0c5e48f22 100644
--- a/src/ARMeilleure/Decoders/IOpCode32MemMult.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32MemMult.cs
@@ -12,4 +12,4 @@ interface IOpCode32MemMult : IOpCode32
int Offset { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32MemReg.cs b/src/ARMeilleure/Decoders/IOpCode32MemReg.cs
index 7fe1b0229..6a63f7f69 100644
--- a/src/ARMeilleure/Decoders/IOpCode32MemReg.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32MemReg.cs
@@ -1,7 +1,7 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32MemReg : IOpCode32Mem
{
int Rm { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs b/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs
index 65b7ee0b4..3407e98ac 100644
--- a/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs
@@ -5,4 +5,4 @@ interface IOpCode32MemRsImm : IOpCode32Mem
int Rm { get; }
ShiftType ShiftType { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCode32Simd.cs b/src/ARMeilleure/Decoders/IOpCode32Simd.cs
index 687254d92..0dccd2679 100644
--- a/src/ARMeilleure/Decoders/IOpCode32Simd.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32Simd.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32Simd : IOpCode32, IOpCodeSimd { }
}
diff --git a/src/ARMeilleure/Decoders/IOpCode32SimdImm.cs b/src/ARMeilleure/Decoders/IOpCode32SimdImm.cs
index a0cb669c7..a8e646092 100644
--- a/src/ARMeilleure/Decoders/IOpCode32SimdImm.cs
+++ b/src/ARMeilleure/Decoders/IOpCode32SimdImm.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
interface IOpCode32SimdImm : IOpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/IOpCodeAlu.cs b/src/ARMeilleure/Decoders/IOpCodeAlu.cs
index b8c28513d..059769ba9 100644
--- a/src/ARMeilleure/Decoders/IOpCodeAlu.cs
+++ b/src/ARMeilleure/Decoders/IOpCodeAlu.cs
@@ -7,4 +7,4 @@ interface IOpCodeAlu : IOpCode
DataOp DataOp { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCodeAluImm.cs b/src/ARMeilleure/Decoders/IOpCodeAluImm.cs
index 02f4c997b..40a69cc90 100644
--- a/src/ARMeilleure/Decoders/IOpCodeAluImm.cs
+++ b/src/ARMeilleure/Decoders/IOpCodeAluImm.cs
@@ -4,4 +4,4 @@ interface IOpCodeAluImm : IOpCodeAlu
{
long Immediate { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCodeAluRs.cs b/src/ARMeilleure/Decoders/IOpCodeAluRs.cs
index 22540b11a..eec956982 100644
--- a/src/ARMeilleure/Decoders/IOpCodeAluRs.cs
+++ b/src/ARMeilleure/Decoders/IOpCodeAluRs.cs
@@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders
interface IOpCodeAluRs : IOpCodeAlu
{
int Shift { get; }
- int Rm { get; }
+ int Rm { get; }
ShiftType ShiftType { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCodeAluRx.cs b/src/ARMeilleure/Decoders/IOpCodeAluRx.cs
index 9d16be787..e5a8559d8 100644
--- a/src/ARMeilleure/Decoders/IOpCodeAluRx.cs
+++ b/src/ARMeilleure/Decoders/IOpCodeAluRx.cs
@@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders
interface IOpCodeAluRx : IOpCodeAlu
{
int Shift { get; }
- int Rm { get; }
+ int Rm { get; }
IntType IntType { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCodeBImm.cs b/src/ARMeilleure/Decoders/IOpCodeBImm.cs
index 958bff28d..9ce7512a1 100644
--- a/src/ARMeilleure/Decoders/IOpCodeBImm.cs
+++ b/src/ARMeilleure/Decoders/IOpCodeBImm.cs
@@ -4,4 +4,4 @@ interface IOpCodeBImm : IOpCode
{
long Immediate { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCodeCond.cs b/src/ARMeilleure/Decoders/IOpCodeCond.cs
index 9808f7c08..6604f19a2 100644
--- a/src/ARMeilleure/Decoders/IOpCodeCond.cs
+++ b/src/ARMeilleure/Decoders/IOpCodeCond.cs
@@ -4,4 +4,4 @@ interface IOpCodeCond : IOpCode
{
Condition Cond { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCodeLit.cs b/src/ARMeilleure/Decoders/IOpCodeLit.cs
index 74084a457..434e4da88 100644
--- a/src/ARMeilleure/Decoders/IOpCodeLit.cs
+++ b/src/ARMeilleure/Decoders/IOpCodeLit.cs
@@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders
{
interface IOpCodeLit : IOpCode
{
- int Rt { get; }
+ int Rt { get; }
long Immediate { get; }
- int Size { get; }
- bool Signed { get; }
- bool Prefetch { get; }
+ int Size { get; }
+ bool Signed { get; }
+ bool Prefetch { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IOpCodeSimd.cs b/src/ARMeilleure/Decoders/IOpCodeSimd.cs
index 056ef045c..598d9d7f8 100644
--- a/src/ARMeilleure/Decoders/IOpCodeSimd.cs
+++ b/src/ARMeilleure/Decoders/IOpCodeSimd.cs
@@ -4,4 +4,4 @@ interface IOpCodeSimd : IOpCode
{
int Size { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/InstDescriptor.cs b/src/ARMeilleure/Decoders/InstDescriptor.cs
index 577ff3946..c35c754a9 100644
--- a/src/ARMeilleure/Decoders/InstDescriptor.cs
+++ b/src/ARMeilleure/Decoders/InstDescriptor.cs
@@ -4,15 +4,15 @@ namespace ARMeilleure.Decoders
{
readonly struct InstDescriptor
{
- public static InstDescriptor Undefined => new InstDescriptor(InstName.Und, InstEmit.Und);
+ public static InstDescriptor Undefined => new(InstName.Und, InstEmit.Und);
- public InstName Name { get; }
+ public InstName Name { get; }
public InstEmitter Emitter { get; }
public InstDescriptor(InstName name, InstEmitter emitter)
{
- Name = name;
+ Name = name;
Emitter = emitter;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/InstEmitter.cs b/src/ARMeilleure/Decoders/InstEmitter.cs
index a8b526569..43bfcdca3 100644
--- a/src/ARMeilleure/Decoders/InstEmitter.cs
+++ b/src/ARMeilleure/Decoders/InstEmitter.cs
@@ -3,4 +3,4 @@
namespace ARMeilleure.Decoders
{
delegate void InstEmitter(ArmEmitterContext context);
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/IntType.cs b/src/ARMeilleure/Decoders/IntType.cs
index 244e96805..937a569aa 100644
--- a/src/ARMeilleure/Decoders/IntType.cs
+++ b/src/ARMeilleure/Decoders/IntType.cs
@@ -2,13 +2,13 @@ namespace ARMeilleure.Decoders
{
enum IntType
{
- UInt8 = 0,
+ UInt8 = 0,
UInt16 = 1,
UInt32 = 2,
UInt64 = 3,
- Int8 = 4,
- Int16 = 5,
- Int32 = 6,
- Int64 = 7
+ Int8 = 4,
+ Int16 = 5,
+ Int32 = 6,
+ Int64 = 7,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode.cs b/src/ARMeilleure/Decoders/OpCode.cs
index f9aed7924..c8123308b 100644
--- a/src/ARMeilleure/Decoders/OpCode.cs
+++ b/src/ARMeilleure/Decoders/OpCode.cs
@@ -5,8 +5,8 @@ namespace ARMeilleure.Decoders
{
class OpCode : IOpCode
{
- public ulong Address { get; }
- public int RawOpCode { get; }
+ public ulong Address { get; }
+ public int RawOpCode { get; }
public int OpCodeSizeInBytes { get; protected set; } = 4;
@@ -14,13 +14,13 @@ class OpCode : IOpCode
public RegisterSize RegisterSize { get; protected set; }
- public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode);
+ public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new(inst, address, opCode);
public OpCode(InstDescriptor inst, ulong address, int opCode)
{
Instruction = inst;
- Address = address;
- RawOpCode = opCode;
+ Address = address;
+ RawOpCode = opCode;
RegisterSize = RegisterSize.Int64;
}
@@ -30,15 +30,14 @@ public OpCode(InstDescriptor inst, ulong address, int opCode)
public int GetBitsCount()
{
- switch (RegisterSize)
+ return RegisterSize switch
{
- case RegisterSize.Int32: return 32;
- case RegisterSize.Int64: return 64;
- case RegisterSize.Simd64: return 64;
- case RegisterSize.Simd128: return 128;
- }
-
- throw new InvalidOperationException();
+ RegisterSize.Int32 => 32,
+ RegisterSize.Int64 => 64,
+ RegisterSize.Simd64 => 64,
+ RegisterSize.Simd128 => 128,
+ _ => throw new InvalidOperationException(),
+ };
}
public OperandType GetOperandType()
@@ -46,4 +45,4 @@ public OperandType GetOperandType()
return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32.cs b/src/ARMeilleure/Decoders/OpCode32.cs
index c2f14145b..a2be01e9a 100644
--- a/src/ARMeilleure/Decoders/OpCode32.cs
+++ b/src/ARMeilleure/Decoders/OpCode32.cs
@@ -31,4 +31,4 @@ public uint GetPc()
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32Alu.cs b/src/ARMeilleure/Decoders/OpCode32Alu.cs
index 1625aee0a..8634f5ce9 100644
--- a/src/ARMeilleure/Decoders/OpCode32Alu.cs
+++ b/src/ARMeilleure/Decoders/OpCode32Alu.cs
@@ -17,4 +17,4 @@ public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst,
SetFlags = ((opCode >> 20) & 1) != 0;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32AluBf.cs b/src/ARMeilleure/Decoders/OpCode32AluBf.cs
index 0cee34e6d..c34784428 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluBf.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluBf.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32AluBf : OpCode32, IOpCode32AluBf
{
diff --git a/src/ARMeilleure/Decoders/OpCode32AluImm.cs b/src/ARMeilleure/Decoders/OpCode32AluImm.cs
index b5435aaf1..c8b05e6bc 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluImm.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluImm.cs
@@ -20,4 +20,4 @@ public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(ins
IsRotated = shift != 0;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32AluImm16.cs b/src/ARMeilleure/Decoders/OpCode32AluImm16.cs
index e24edeb41..2af35bd51 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluImm16.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluImm16.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32AluImm16 : OpCode32Alu, IOpCode32AluImm16
{
diff --git a/src/ARMeilleure/Decoders/OpCode32AluMla.cs b/src/ARMeilleure/Decoders/OpCode32AluMla.cs
index 2cd2b9dcc..bc5d23908 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluMla.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluMla.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32AluMla : OpCode32, IOpCode32AluMla
{
diff --git a/src/ARMeilleure/Decoders/OpCode32AluReg.cs b/src/ARMeilleure/Decoders/OpCode32AluReg.cs
index 493a977f0..9ef7571cf 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluReg.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32AluReg : OpCode32Alu, IOpCode32AluReg
{
diff --git a/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs b/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs
index c2dee6c9a..4b2c5897a 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs
@@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders
{
class OpCode32AluRsImm : OpCode32Alu, IOpCode32AluRsImm
{
- public int Rm { get; }
+ public int Rm { get; }
public int Immediate { get; }
public ShiftType ShiftType { get; }
@@ -11,10 +11,10 @@ class OpCode32AluRsImm : OpCode32Alu, IOpCode32AluRsImm
public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rm = (opCode >> 0) & 0xf;
+ Rm = (opCode >> 0) & 0xf;
Immediate = (opCode >> 7) & 0x1f;
ShiftType = (ShiftType)((opCode >> 5) & 3);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32AluRsReg.cs b/src/ARMeilleure/Decoders/OpCode32AluRsReg.cs
index 04740d086..6379b3bde 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluRsReg.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluRsReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32AluRsReg : OpCode32Alu, IOpCode32AluRsReg
{
diff --git a/src/ARMeilleure/Decoders/OpCode32AluUmull.cs b/src/ARMeilleure/Decoders/OpCode32AluUmull.cs
index bf80df3ff..44b7ea154 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluUmull.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluUmull.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32AluUmull : OpCode32, IOpCode32AluUmull
{
diff --git a/src/ARMeilleure/Decoders/OpCode32AluUx.cs b/src/ARMeilleure/Decoders/OpCode32AluUx.cs
index 57068675d..68da302fc 100644
--- a/src/ARMeilleure/Decoders/OpCode32AluUx.cs
+++ b/src/ARMeilleure/Decoders/OpCode32AluUx.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.State;
+using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
diff --git a/src/ARMeilleure/Decoders/OpCode32BImm.cs b/src/ARMeilleure/Decoders/OpCode32BImm.cs
index f2959b331..e7f5d6db1 100644
--- a/src/ARMeilleure/Decoders/OpCode32BImm.cs
+++ b/src/ARMeilleure/Decoders/OpCode32BImm.cs
@@ -26,4 +26,4 @@ public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst,
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32BReg.cs b/src/ARMeilleure/Decoders/OpCode32BReg.cs
index d4f5f7601..8939c0de3 100644
--- a/src/ARMeilleure/Decoders/OpCode32BReg.cs
+++ b/src/ARMeilleure/Decoders/OpCode32BReg.cs
@@ -11,4 +11,4 @@ public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst,
Rm = opCode & 0xf;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32Exception.cs b/src/ARMeilleure/Decoders/OpCode32Exception.cs
index b4edcc100..51a535e43 100644
--- a/src/ARMeilleure/Decoders/OpCode32Exception.cs
+++ b/src/ARMeilleure/Decoders/OpCode32Exception.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32Exception : OpCode32, IOpCode32Exception
{
diff --git a/src/ARMeilleure/Decoders/OpCode32Mem.cs b/src/ARMeilleure/Decoders/OpCode32Mem.cs
index ceb1e49f5..8a2421996 100644
--- a/src/ARMeilleure/Decoders/OpCode32Mem.cs
+++ b/src/ARMeilleure/Decoders/OpCode32Mem.cs
@@ -9,9 +9,9 @@ class OpCode32Mem : OpCode32, IOpCode32Mem
public int Immediate { get; protected set; }
- public bool Index { get; }
- public bool Add { get; }
- public bool WBack { get; }
+ public bool Index { get; }
+ public bool Add { get; }
+ public bool WBack { get; }
public bool Unprivileged { get; }
public bool IsLoad { get; }
@@ -24,16 +24,16 @@ public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst,
Rn = (opCode >> 16) & 0xf;
bool isLoad = (opCode & (1 << 20)) != 0;
- bool w = (opCode & (1 << 21)) != 0;
- bool u = (opCode & (1 << 23)) != 0;
- bool p = (opCode & (1 << 24)) != 0;
+ bool w = (opCode & (1 << 21)) != 0;
+ bool u = (opCode & (1 << 23)) != 0;
+ bool p = (opCode & (1 << 24)) != 0;
- Index = p;
- Add = u;
- WBack = !p || w;
+ Index = p;
+ Add = u;
+ WBack = !p || w;
Unprivileged = !p && w;
IsLoad = isLoad || inst.Name == InstName.Ldrd;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32MemImm.cs b/src/ARMeilleure/Decoders/OpCode32MemImm.cs
index 3af4b6f7c..fa10e04ee 100644
--- a/src/ARMeilleure/Decoders/OpCode32MemImm.cs
+++ b/src/ARMeilleure/Decoders/OpCode32MemImm.cs
@@ -9,4 +9,4 @@ public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(ins
Immediate = opCode & 0xfff;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32MemImm8.cs b/src/ARMeilleure/Decoders/OpCode32MemImm8.cs
index 1b8a57de4..248ee8e65 100644
--- a/src/ARMeilleure/Decoders/OpCode32MemImm8.cs
+++ b/src/ARMeilleure/Decoders/OpCode32MemImm8.cs
@@ -12,4 +12,4 @@ public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(in
Immediate = imm4L | (imm4H << 4);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32MemLdEx.cs b/src/ARMeilleure/Decoders/OpCode32MemLdEx.cs
index 520113f46..0f0b37eac 100644
--- a/src/ARMeilleure/Decoders/OpCode32MemLdEx.cs
+++ b/src/ARMeilleure/Decoders/OpCode32MemLdEx.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32MemLdEx : OpCode32Mem, IOpCode32MemEx
{
diff --git a/src/ARMeilleure/Decoders/OpCode32MemMult.cs b/src/ARMeilleure/Decoders/OpCode32MemMult.cs
index 522b96bb9..6e39e3479 100644
--- a/src/ARMeilleure/Decoders/OpCode32MemMult.cs
+++ b/src/ARMeilleure/Decoders/OpCode32MemMult.cs
@@ -7,8 +7,8 @@ class OpCode32MemMult : OpCode32, IOpCode32MemMult
public int Rn { get; }
public int RegisterMask { get; }
- public int Offset { get; }
- public int PostOffset { get; }
+ public int Offset { get; }
+ public int PostOffset { get; }
public bool IsLoad { get; }
@@ -19,9 +19,9 @@ public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(in
Rn = (opCode >> 16) & 0xf;
bool isLoad = (opCode & (1 << 20)) != 0;
- bool w = (opCode & (1 << 21)) != 0;
- bool u = (opCode & (1 << 23)) != 0;
- bool p = (opCode & (1 << 24)) != 0;
+ bool w = (opCode & (1 << 21)) != 0;
+ bool u = (opCode & (1 << 23)) != 0;
+ bool p = (opCode & (1 << 24)) != 0;
RegisterMask = opCode & 0xffff;
@@ -49,4 +49,4 @@ public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(in
IsLoad = isLoad;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32MemReg.cs b/src/ARMeilleure/Decoders/OpCode32MemReg.cs
index 786f37fab..d8f1c29b2 100644
--- a/src/ARMeilleure/Decoders/OpCode32MemReg.cs
+++ b/src/ARMeilleure/Decoders/OpCode32MemReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32MemReg : OpCode32Mem, IOpCode32MemReg
{
diff --git a/src/ARMeilleure/Decoders/OpCode32MemRsImm.cs b/src/ARMeilleure/Decoders/OpCode32MemRsImm.cs
index e1284cf7e..b0e5aa4b9 100644
--- a/src/ARMeilleure/Decoders/OpCode32MemRsImm.cs
+++ b/src/ARMeilleure/Decoders/OpCode32MemRsImm.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32MemRsImm : OpCode32Mem, IOpCode32MemRsImm
{
diff --git a/src/ARMeilleure/Decoders/OpCode32MemStEx.cs b/src/ARMeilleure/Decoders/OpCode32MemStEx.cs
index dcf93b224..180a9b5ac 100644
--- a/src/ARMeilleure/Decoders/OpCode32MemStEx.cs
+++ b/src/ARMeilleure/Decoders/OpCode32MemStEx.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32MemStEx : OpCode32Mem, IOpCode32MemEx
{
diff --git a/src/ARMeilleure/Decoders/OpCode32Mrs.cs b/src/ARMeilleure/Decoders/OpCode32Mrs.cs
index c34a8b997..b681b54c0 100644
--- a/src/ARMeilleure/Decoders/OpCode32Mrs.cs
+++ b/src/ARMeilleure/Decoders/OpCode32Mrs.cs
@@ -2,8 +2,8 @@ namespace ARMeilleure.Decoders
{
class OpCode32Mrs : OpCode32
{
- public bool R { get; }
- public int Rd { get; }
+ public bool R { get; }
+ public int Rd { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mrs(inst, address, opCode);
diff --git a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs
index d897ffd80..dcd06aa01 100644
--- a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs
+++ b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs
@@ -1,14 +1,14 @@
-using ARMeilleure.State;
+using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
class OpCode32MsrReg : OpCode32
{
- public bool R { get; }
- public int Mask { get; }
- public int Rd { get; }
+ public bool R { get; }
+ public int Mask { get; }
+ public int Rd { get; }
public bool Banked { get; }
- public int Rn { get; }
+ public int Rn { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode);
diff --git a/src/ARMeilleure/Decoders/OpCode32Sat.cs b/src/ARMeilleure/Decoders/OpCode32Sat.cs
index 621def27c..35c5cf47a 100644
--- a/src/ARMeilleure/Decoders/OpCode32Sat.cs
+++ b/src/ARMeilleure/Decoders/OpCode32Sat.cs
@@ -21,4 +21,4 @@ public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst,
ShiftType = (ShiftType)((opCode >> 5) & 2);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32Sat16.cs b/src/ARMeilleure/Decoders/OpCode32Sat16.cs
index 51061b079..01f4d3b23 100644
--- a/src/ARMeilleure/Decoders/OpCode32Sat16.cs
+++ b/src/ARMeilleure/Decoders/OpCode32Sat16.cs
@@ -15,4 +15,4 @@ public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode) : base(inst
SatImm = (opCode >> 16) & 0xf;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32Simd.cs b/src/ARMeilleure/Decoders/OpCode32Simd.cs
index 636aa0a82..1e69b2341 100644
--- a/src/ARMeilleure/Decoders/OpCode32Simd.cs
+++ b/src/ARMeilleure/Decoders/OpCode32Simd.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32Simd : OpCode32SimdBase
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdBase.cs b/src/ARMeilleure/Decoders/OpCode32SimdBase.cs
index 4382fc2aa..d0634a0e1 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdBase.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdBase.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.Decoders
{
@@ -24,27 +24,21 @@ abstract class OpCode32SimdBase : OpCode32, IOpCode32Simd
protected int GetQuadwordIndex(int index)
{
- switch (RegisterSize)
+ return RegisterSize switch
{
- case RegisterSize.Simd128:
- case RegisterSize.Simd64:
- return index >> 1;
- }
-
- throw new InvalidOperationException();
+ RegisterSize.Simd128 or RegisterSize.Simd64 => index >> 1,
+ _ => throw new InvalidOperationException(),
+ };
}
protected int GetQuadwordSubindex(int index)
{
- switch (RegisterSize)
+ return RegisterSize switch
{
- case RegisterSize.Simd128:
- return 0;
- case RegisterSize.Simd64:
- return index & 1;
- }
-
- throw new InvalidOperationException();
+ RegisterSize.Simd128 => 0,
+ RegisterSize.Simd64 => index & 1,
+ _ => throw new InvalidOperationException(),
+ };
}
protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdBinary.cs b/src/ARMeilleure/Decoders/OpCode32SimdBinary.cs
index ba190de96..c0c8277a9 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdBinary.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdBinary.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
///
/// A special alias that always runs in 64 bit int, to speed up binary ops a little.
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs b/src/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
index 445e67819..d8bc109e7 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdCmpZ : OpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdCvtFFixed.cs b/src/ARMeilleure/Decoders/OpCode32SimdCvtFFixed.cs
new file mode 100644
index 000000000..200df73ad
--- /dev/null
+++ b/src/ARMeilleure/Decoders/OpCode32SimdCvtFFixed.cs
@@ -0,0 +1,23 @@
+namespace ARMeilleure.Decoders
+{
+ class OpCode32SimdCvtFFixed : OpCode32Simd
+ {
+ public int Fbits { get; protected set; }
+
+ public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFFixed(inst, address, opCode, false);
+ public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFFixed(inst, address, opCode, true);
+
+ public OpCode32SimdCvtFFixed(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
+ {
+ Opc = (opCode >> 8) & 0x1;
+
+ Size = Opc == 1 ? 0 : 2;
+ Fbits = 64 - ((opCode >> 16) & 0x3f);
+
+ if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm))
+ {
+ Instruction = InstDescriptor.Undefined;
+ }
+ }
+ }
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs b/src/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
index 41cf4d884..ee8f94a4e 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdCvtFI : OpCode32SimdS
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs b/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs
index a95b32ab0..d3beb4bfd 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs
@@ -15,8 +15,8 @@ public OpCode32SimdCvtTB(InstDescriptor inst, ulong address, int opCode, bool is
{
IsThumb = isThumb;
- Op = ((opCode >> 16) & 0x1) != 0;
- T = ((opCode >> 7) & 0x1) != 0;
+ Op = ((opCode >> 16) & 0x1) != 0;
+ T = ((opCode >> 7) & 0x1) != 0;
Size = ((opCode >> 8) & 0x1);
RegisterSize = Size == 1 ? RegisterSize.Int64 : RegisterSize.Int32;
@@ -41,4 +41,4 @@ public OpCode32SimdCvtTB(InstDescriptor inst, ulong address, int opCode, bool is
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdDupElem.cs b/src/ARMeilleure/Decoders/OpCode32SimdDupElem.cs
index c455b5b4e..b6cdff088 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdDupElem.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdDupElem.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdDupElem : OpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdDupGP.cs b/src/ARMeilleure/Decoders/OpCode32SimdDupGP.cs
index 31546ea31..57adea5e6 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdDupGP.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdDupGP.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdDupGP : OpCode32, IOpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdExt.cs b/src/ARMeilleure/Decoders/OpCode32SimdExt.cs
index 6dbb5b662..4fe9f25db 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdExt.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdExt.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdExt : OpCode32SimdReg
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdImm.cs b/src/ARMeilleure/Decoders/OpCode32SimdImm.cs
index bf0ca527d..9e931e791 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdImm.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdImm.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdImm : OpCode32SimdBase, IOpCode32SimdImm
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdImm44.cs b/src/ARMeilleure/Decoders/OpCode32SimdImm44.cs
index fa00a935a..55df1ba6e 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdImm44.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdImm44.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdImm44 : OpCode32, IOpCode32SimdImm
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdLong.cs b/src/ARMeilleure/Decoders/OpCode32SimdLong.cs
index 8d64d673a..5c068de16 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdLong.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdLong.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdLong : OpCode32SimdBase
{
@@ -14,9 +14,15 @@ public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode, bool isT
// The value must be a power of 2, otherwise it is the encoding of another instruction.
switch (imm3h)
{
- case 1: Size = 0; break;
- case 2: Size = 1; break;
- case 4: Size = 2; break;
+ case 1:
+ Size = 0;
+ break;
+ case 2:
+ Size = 1;
+ break;
+ case 4:
+ Size = 2;
+ break;
}
U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMemImm.cs b/src/ARMeilleure/Decoders/OpCode32SimdMemImm.cs
index c933a5ad2..86870dfea 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdMemImm.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdMemImm.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdMemImm : OpCode32, IOpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMemMult.cs b/src/ARMeilleure/Decoders/OpCode32SimdMemMult.cs
index a16a03d3b..c3b8670f8 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdMemMult.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdMemMult.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdMemMult : OpCode32
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs b/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
index da88eed27..6a18211c6 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
@@ -1,15 +1,15 @@
-using ARMeilleure.State;
+using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
class OpCode32SimdMemPair : OpCode32, IOpCode32Simd
{
- private static int[] _regsMap =
+ private static readonly int[] _regsMap =
{
1, 1, 4, 2,
1, 1, 3, 1,
1, 1, 2, 1,
- 1, 1, 1, 1
+ 1, 1, 1, 1,
};
public int Vd { get; }
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs b/src/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
index 35dd41c29..5df45000f 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.State;
+using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMovGp.cs b/src/ARMeilleure/Decoders/OpCode32SimdMovGp.cs
index 5afd34883..35b8cc9f1 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdMovGp.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdMovGp.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdMovGp : OpCode32, IOpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs b/src/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
index 2d6931199..4399fb3c0 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdMovGpDouble : OpCode32, IOpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs b/src/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
index 7816665f3..f6fce7d99 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdMovGpElem : OpCode32, IOpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdReg.cs b/src/ARMeilleure/Decoders/OpCode32SimdReg.cs
index 1c46b0e01..eaf17b8c6 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdReg.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdReg : OpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdRegElem.cs b/src/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
index 173c52652..147de44ba 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdRegElem : OpCode32SimdReg
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs b/src/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
index b87ac4130..8aea44cb0 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdRegElemLong : OpCode32SimdRegElem
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdRegLong.cs b/src/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
index 110693835..1349fb479 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdRegLong : OpCode32SimdReg
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdRegS.cs b/src/ARMeilleure/Decoders/OpCode32SimdRegS.cs
index 8168e83fd..2dfb0074d 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdRegS.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdRegS.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdRegS : OpCode32SimdS
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdRegWide.cs b/src/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
index fd2b3bf1d..6f9c639f9 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdRegWide : OpCode32SimdReg
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdRev.cs b/src/ARMeilleure/Decoders/OpCode32SimdRev.cs
index cb64765f4..26d8be2b9 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdRev.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdRev.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdRev : OpCode32SimdCmpZ
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdS.cs b/src/ARMeilleure/Decoders/OpCode32SimdS.cs
index 63c03c019..0bb62cb52 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdS.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdS.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdS : OpCode32, IOpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdSel.cs b/src/ARMeilleure/Decoders/OpCode32SimdSel.cs
index 37fd714a4..a6667ba19 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdSel.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdSel.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdSel : OpCode32SimdRegS
{
@@ -13,11 +13,11 @@ public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode, bool isTh
}
}
- enum OpCode32SimdSelMode : int
+ enum OpCode32SimdSelMode
{
Eq = 0,
Vs,
Ge,
- Gt
+ Gt,
}
}
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdShImm.cs b/src/ARMeilleure/Decoders/OpCode32SimdShImm.cs
index 55ddc3958..040dce6f1 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdShImm.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdShImm.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdShImm : OpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs b/src/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
index 6b1b0ad1e..13d89ca42 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdShImmLong : OpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs b/src/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
index 5351e65ff..ce1e79069 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdShImmNarrow : OpCode32SimdShImm
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdSpecial.cs b/src/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
index 61a9f3870..9b6f47321 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdSpecial : OpCode32
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdSqrte.cs b/src/ARMeilleure/Decoders/OpCode32SimdSqrte.cs
index 5b715535a..8f8fa4b03 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdSqrte.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdSqrte.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdSqrte : OpCode32Simd
{
diff --git a/src/ARMeilleure/Decoders/OpCode32SimdTbl.cs b/src/ARMeilleure/Decoders/OpCode32SimdTbl.cs
index c4fb4b9ce..fcac9e014 100644
--- a/src/ARMeilleure/Decoders/OpCode32SimdTbl.cs
+++ b/src/ARMeilleure/Decoders/OpCode32SimdTbl.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32SimdTbl : OpCode32SimdReg
{
diff --git a/src/ARMeilleure/Decoders/OpCode32System.cs b/src/ARMeilleure/Decoders/OpCode32System.cs
index 89e93349b..f6f5e0f96 100644
--- a/src/ARMeilleure/Decoders/OpCode32System.cs
+++ b/src/ARMeilleure/Decoders/OpCode32System.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCode32System : OpCode32
{
diff --git a/src/ARMeilleure/Decoders/OpCodeAdr.cs b/src/ARMeilleure/Decoders/OpCodeAdr.cs
index 9655c766c..080280404 100644
--- a/src/ARMeilleure/Decoders/OpCodeAdr.cs
+++ b/src/ARMeilleure/Decoders/OpCodeAdr.cs
@@ -6,14 +6,14 @@ class OpCodeAdr : OpCode
public long Immediate { get; }
- public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode);
+ public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode);
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = opCode & 0x1f;
- Immediate = DecoderHelper.DecodeImmS19_2(opCode);
+ Immediate = DecoderHelper.DecodeImmS19_2(opCode);
Immediate |= ((long)opCode >> 29) & 3;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeAlu.cs b/src/ARMeilleure/Decoders/OpCodeAlu.cs
index 4d7f03a71..1619ecd8e 100644
--- a/src/ARMeilleure/Decoders/OpCodeAlu.cs
+++ b/src/ARMeilleure/Decoders/OpCodeAlu.cs
@@ -11,8 +11,8 @@ class OpCodeAlu : OpCode, IOpCodeAlu
public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rd = (opCode >> 0) & 0x1f;
- Rn = (opCode >> 5) & 0x1f;
+ Rd = (opCode >> 0) & 0x1f;
+ Rn = (opCode >> 5) & 0x1f;
DataOp = (DataOp)((opCode >> 24) & 0x3);
RegisterSize = (opCode >> 31) != 0
@@ -20,4 +20,4 @@ public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, ad
: RegisterSize.Int32;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeAluBinary.cs b/src/ARMeilleure/Decoders/OpCodeAluBinary.cs
index e8b10656a..4413581ca 100644
--- a/src/ARMeilleure/Decoders/OpCodeAluBinary.cs
+++ b/src/ARMeilleure/Decoders/OpCodeAluBinary.cs
@@ -11,4 +11,4 @@ public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(in
Rm = (opCode >> 16) & 0x1f;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeAluImm.cs b/src/ARMeilleure/Decoders/OpCodeAluImm.cs
index 91aa95531..0d2f7202f 100644
--- a/src/ARMeilleure/Decoders/OpCodeAluImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeAluImm.cs
@@ -33,8 +33,8 @@ public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst,
}
else
{
- throw new ArgumentException(nameof(opCode));
+ throw new ArgumentException($"Invalid data operation: {DataOp}", nameof(opCode));
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeAluRs.cs b/src/ARMeilleure/Decoders/OpCodeAluRs.cs
index 949833363..47a47e7d0 100644
--- a/src/ARMeilleure/Decoders/OpCodeAluRs.cs
+++ b/src/ARMeilleure/Decoders/OpCodeAluRs.cs
@@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders
class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs
{
public int Shift { get; }
- public int Rm { get; }
+ public int Rm { get; }
public ShiftType ShiftType { get; }
@@ -22,8 +22,8 @@ public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst,
Shift = shift;
- Rm = (opCode >> 16) & 0x1f;
+ Rm = (opCode >> 16) & 0x1f;
ShiftType = (ShiftType)((opCode >> 22) & 0x3);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeAluRx.cs b/src/ARMeilleure/Decoders/OpCodeAluRx.cs
index d39da9e74..c21486788 100644
--- a/src/ARMeilleure/Decoders/OpCodeAluRx.cs
+++ b/src/ARMeilleure/Decoders/OpCodeAluRx.cs
@@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders
class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
{
public int Shift { get; }
- public int Rm { get; }
+ public int Rm { get; }
public IntType IntType { get; }
@@ -11,9 +11,9 @@ class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Shift = (opCode >> 10) & 0x7;
+ Shift = (opCode >> 10) & 0x7;
IntType = (IntType)((opCode >> 13) & 0x7);
- Rm = (opCode >> 16) & 0x1f;
+ Rm = (opCode >> 16) & 0x1f;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeBImm.cs b/src/ARMeilleure/Decoders/OpCodeBImm.cs
index e302516e2..2848c1409 100644
--- a/src/ARMeilleure/Decoders/OpCodeBImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeBImm.cs
@@ -8,4 +8,4 @@ class OpCodeBImm : OpCode, IOpCodeBImm
public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeBImmAl.cs b/src/ARMeilleure/Decoders/OpCodeBImmAl.cs
index 47ae5f562..6c4b28c6c 100644
--- a/src/ARMeilleure/Decoders/OpCodeBImmAl.cs
+++ b/src/ARMeilleure/Decoders/OpCodeBImmAl.cs
@@ -9,4 +9,4 @@ public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst,
Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs b/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs
index a52465699..c477ddecf 100644
--- a/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs
+++ b/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs
@@ -17,4 +17,4 @@ public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst
: RegisterSize.Int32;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeBImmCond.cs b/src/ARMeilleure/Decoders/OpCodeBImmCond.cs
index b57a7ea85..7a51a0720 100644
--- a/src/ARMeilleure/Decoders/OpCodeBImmCond.cs
+++ b/src/ARMeilleure/Decoders/OpCodeBImmCond.cs
@@ -22,4 +22,4 @@ public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(ins
Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeBImmTest.cs b/src/ARMeilleure/Decoders/OpCodeBImmTest.cs
index bad984055..f989e59e4 100644
--- a/src/ARMeilleure/Decoders/OpCodeBImmTest.cs
+++ b/src/ARMeilleure/Decoders/OpCodeBImmTest.cs
@@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders
{
class OpCodeBImmTest : OpCodeBImm
{
- public int Rt { get; }
+ public int Rt { get; }
public int Bit { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode);
@@ -13,8 +13,8 @@ public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(ins
Immediate = (long)address + DecoderHelper.DecodeImmS14_2(opCode);
- Bit = (opCode >> 19) & 0x1f;
+ Bit = (opCode >> 19) & 0x1f;
Bit |= (opCode >> 26) & 0x20;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeBReg.cs b/src/ARMeilleure/Decoders/OpCodeBReg.cs
index b5dcbfd8e..3b84cf5c0 100644
--- a/src/ARMeilleure/Decoders/OpCodeBReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeBReg.cs
@@ -8,7 +8,7 @@ class OpCodeBReg : OpCode
public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- int op4 = (opCode >> 0) & 0x1f;
+ int op4 = (opCode >> 0) & 0x1f;
int op2 = (opCode >> 16) & 0x1f;
if (op2 != 0b11111 || op4 != 0b00000)
@@ -21,4 +21,4 @@ public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, a
Rn = (opCode >> 5) & 0x1f;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeBfm.cs b/src/ARMeilleure/Decoders/OpCodeBfm.cs
index 8e1c78361..d51efade2 100644
--- a/src/ARMeilleure/Decoders/OpCodeBfm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeBfm.cs
@@ -4,8 +4,8 @@ class OpCodeBfm : OpCodeAlu
{
public long WMask { get; }
public long TMask { get; }
- public int Pos { get; }
- public int Shift { get; }
+ public int Pos { get; }
+ public int Shift { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode);
@@ -22,8 +22,8 @@ public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, ad
WMask = bm.WMask;
TMask = bm.TMask;
- Pos = bm.Pos;
+ Pos = bm.Pos;
Shift = bm.Shift;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeCcmp.cs b/src/ARMeilleure/Decoders/OpCodeCcmp.cs
index aa47146f8..d40353486 100644
--- a/src/ARMeilleure/Decoders/OpCodeCcmp.cs
+++ b/src/ARMeilleure/Decoders/OpCodeCcmp.cs
@@ -4,7 +4,7 @@ namespace ARMeilleure.Decoders
{
class OpCodeCcmp : OpCodeAlu, IOpCodeCond
{
- public int Nzcv { get; }
+ public int Nzcv { get; }
protected int RmImm;
public Condition Cond { get; }
@@ -22,11 +22,11 @@ public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, a
return;
}
- Nzcv = (opCode >> 0) & 0xf;
- Cond = (Condition)((opCode >> 12) & 0xf);
- RmImm = (opCode >> 16) & 0x1f;
+ Nzcv = (opCode >> 0) & 0xf;
+ Cond = (Condition)((opCode >> 12) & 0xf);
+ RmImm = (opCode >> 16) & 0x1f;
Rd = RegisterAlias.Zr;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs b/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs
index 3548f2da8..9d6acf196 100644
--- a/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs
@@ -8,4 +8,4 @@ class OpCodeCcmpImm : OpCodeCcmp, IOpCodeAluImm
public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs b/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs
index d5df3b102..349afa120 100644
--- a/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs
@@ -12,4 +12,4 @@ class OpCodeCcmpReg : OpCodeCcmp, IOpCodeAluRs
public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeCsel.cs b/src/ARMeilleure/Decoders/OpCodeCsel.cs
index 4b8dc7fdd..418962e08 100644
--- a/src/ARMeilleure/Decoders/OpCodeCsel.cs
+++ b/src/ARMeilleure/Decoders/OpCodeCsel.cs
@@ -10,8 +10,8 @@ class OpCodeCsel : OpCodeAlu, IOpCodeCond
public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rm = (opCode >> 16) & 0x1f;
+ Rm = (opCode >> 16) & 0x1f;
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeException.cs b/src/ARMeilleure/Decoders/OpCodeException.cs
index 6b72138ee..eee636405 100644
--- a/src/ARMeilleure/Decoders/OpCodeException.cs
+++ b/src/ARMeilleure/Decoders/OpCodeException.cs
@@ -11,4 +11,4 @@ public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(in
Id = (opCode >> 5) & 0xffff;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeMem.cs b/src/ARMeilleure/Decoders/OpCodeMem.cs
index 0ba2bcd18..9b4e5ff3e 100644
--- a/src/ARMeilleure/Decoders/OpCodeMem.cs
+++ b/src/ARMeilleure/Decoders/OpCodeMem.cs
@@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders
{
class OpCodeMem : OpCode
{
- public int Rt { get; protected set; }
- public int Rn { get; protected set; }
- public int Size { get; protected set; }
+ public int Rt { get; protected set; }
+ public int Rn { get; protected set; }
+ public int Size { get; protected set; }
public bool Extend64 { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode);
public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rt = (opCode >> 0) & 0x1f;
- Rn = (opCode >> 5) & 0x1f;
+ Rt = (opCode >> 0) & 0x1f;
+ Rn = (opCode >> 5) & 0x1f;
Size = (opCode >> 30) & 0x3;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeMemEx.cs b/src/ARMeilleure/Decoders/OpCodeMemEx.cs
index 899024853..1dc73140f 100644
--- a/src/ARMeilleure/Decoders/OpCodeMemEx.cs
+++ b/src/ARMeilleure/Decoders/OpCodeMemEx.cs
@@ -3,14 +3,14 @@ namespace ARMeilleure.Decoders
class OpCodeMemEx : OpCodeMem
{
public int Rt2 { get; }
- public int Rs { get; }
+ public int Rs { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode);
public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt2 = (opCode >> 10) & 0x1f;
- Rs = (opCode >> 16) & 0x1f;
+ Rs = (opCode >> 16) & 0x1f;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeMemImm.cs b/src/ARMeilleure/Decoders/OpCodeMemImm.cs
index d6ed2282f..4d5eeb1ed 100644
--- a/src/ARMeilleure/Decoders/OpCodeMemImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeMemImm.cs
@@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders
{
class OpCodeMemImm : OpCodeMem
{
- public long Immediate { get; protected set; }
- public bool WBack { get; protected set; }
- public bool PostIdx { get; protected set; }
- protected bool Unscaled { get; }
+ public long Immediate { get; protected set; }
+ public bool WBack { get; protected set; }
+ public bool PostIdx { get; protected set; }
+ protected bool Unscaled { get; }
private enum MemOp
{
- Unscaled = 0,
- PostIndexed = 1,
+ Unscaled = 0,
+ PostIndexed = 1,
Unprivileged = 2,
- PreIndexed = 3,
- Unsigned
+ PreIndexed = 3,
+ Unsigned,
}
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode);
@@ -21,13 +21,13 @@ private enum MemOp
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Extend64 = ((opCode >> 22) & 3) == 2;
- WBack = ((opCode >> 24) & 1) == 0;
+ WBack = ((opCode >> 24) & 1) == 0;
// The type is not valid for the Unsigned Immediate 12-bits encoding,
// because the bits 11:10 are used for the larger Immediate offset.
MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned;
- PostIdx = type == MemOp.PostIndexed;
+ PostIdx = type == MemOp.PostIndexed;
Unscaled = type == MemOp.Unscaled ||
type == MemOp.Unprivileged;
@@ -50,4 +50,4 @@ public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst,
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeMemLit.cs b/src/ARMeilleure/Decoders/OpCodeMemLit.cs
index 986d66340..8712a78e3 100644
--- a/src/ARMeilleure/Decoders/OpCodeMemLit.cs
+++ b/src/ARMeilleure/Decoders/OpCodeMemLit.cs
@@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders
{
class OpCodeMemLit : OpCode, IOpCodeLit
{
- public int Rt { get; }
+ public int Rt { get; }
public long Immediate { get; }
- public int Size { get; }
- public bool Signed { get; }
- public bool Prefetch { get; }
+ public int Size { get; }
+ public bool Signed { get; }
+ public bool Prefetch { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode);
@@ -18,11 +18,27 @@ public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst,
switch ((opCode >> 30) & 3)
{
- case 0: Size = 2; Signed = false; Prefetch = false; break;
- case 1: Size = 3; Signed = false; Prefetch = false; break;
- case 2: Size = 2; Signed = true; Prefetch = false; break;
- case 3: Size = 0; Signed = false; Prefetch = true; break;
+ case 0:
+ Size = 2;
+ Signed = false;
+ Prefetch = false;
+ break;
+ case 1:
+ Size = 3;
+ Signed = false;
+ Prefetch = false;
+ break;
+ case 2:
+ Size = 2;
+ Signed = true;
+ Prefetch = false;
+ break;
+ case 3:
+ Size = 0;
+ Signed = false;
+ Prefetch = true;
+ break;
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeMemPair.cs b/src/ARMeilleure/Decoders/OpCodeMemPair.cs
index 21018033d..eb696cfeb 100644
--- a/src/ARMeilleure/Decoders/OpCodeMemPair.cs
+++ b/src/ARMeilleure/Decoders/OpCodeMemPair.cs
@@ -8,11 +8,11 @@ class OpCodeMemPair : OpCodeMemImm
public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rt2 = (opCode >> 10) & 0x1f;
- WBack = ((opCode >> 23) & 0x1) != 0;
- PostIdx = ((opCode >> 23) & 0x3) == 1;
+ Rt2 = (opCode >> 10) & 0x1f;
+ WBack = ((opCode >> 23) & 0x1) != 0;
+ PostIdx = ((opCode >> 23) & 0x3) == 1;
Extend64 = ((opCode >> 30) & 0x3) == 1;
- Size = ((opCode >> 31) & 0x1) | 2;
+ Size = ((opCode >> 31) & 0x1) | 2;
DecodeImm(opCode);
}
@@ -22,4 +22,4 @@ protected void DecodeImm(int opCode)
Immediate = ((long)(opCode >> 15) << 57) >> (57 - Size);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeMemReg.cs b/src/ARMeilleure/Decoders/OpCodeMemReg.cs
index 73d6c5d2c..9b0d15959 100644
--- a/src/ARMeilleure/Decoders/OpCodeMemReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeMemReg.cs
@@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders
class OpCodeMemReg : OpCodeMem
{
public bool Shift { get; }
- public int Rm { get; }
+ public int Rm { get; }
public IntType IntType { get; }
@@ -11,10 +11,10 @@ class OpCodeMemReg : OpCodeMem
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Shift = ((opCode >> 12) & 0x1) != 0;
- IntType = (IntType)((opCode >> 13) & 0x7);
- Rm = (opCode >> 16) & 0x1f;
- Extend64 = ((opCode >> 22) & 0x3) == 2;
+ Shift = ((opCode >> 12) & 0x1) != 0;
+ IntType = (IntType)((opCode >> 13) & 0x7);
+ Rm = (opCode >> 16) & 0x1f;
+ Extend64 = ((opCode >> 22) & 0x3) == 2;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeMov.cs b/src/ARMeilleure/Decoders/OpCodeMov.cs
index 50af88cb9..a2914b71c 100644
--- a/src/ARMeilleure/Decoders/OpCodeMov.cs
+++ b/src/ARMeilleure/Decoders/OpCodeMov.cs
@@ -22,9 +22,9 @@ public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, ad
return;
}
- Rd = (opCode >> 0) & 0x1f;
- Immediate = (opCode >> 5) & 0xffff;
- Bit = (opCode >> 21) & 0x3;
+ Rd = (opCode >> 0) & 0x1f;
+ Immediate = (opCode >> 5) & 0xffff;
+ Bit = (opCode >> 21) & 0x3;
Bit <<= 4;
@@ -35,4 +35,4 @@ public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, ad
: RegisterSize.Int32;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeMul.cs b/src/ARMeilleure/Decoders/OpCodeMul.cs
index 31d140a65..9b1dd37b8 100644
--- a/src/ARMeilleure/Decoders/OpCodeMul.cs
+++ b/src/ARMeilleure/Decoders/OpCodeMul.cs
@@ -13,4 +13,4 @@ public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, ad
Rm = (opCode >> 16) & 0x1f;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimd.cs b/src/ARMeilleure/Decoders/OpCodeSimd.cs
index 85713690a..bd34d74d9 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimd.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimd.cs
@@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimd : OpCode, IOpCodeSimd
{
- public int Rd { get; }
- public int Rn { get; }
- public int Opc { get; }
+ public int Rd { get; }
+ public int Rn { get; }
+ public int Opc { get; }
public int Size { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode);
public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rd = (opCode >> 0) & 0x1f;
- Rn = (opCode >> 5) & 0x1f;
- Opc = (opCode >> 15) & 0x3;
+ Rd = (opCode >> 0) & 0x1f;
+ Rn = (opCode >> 5) & 0x1f;
+ Opc = (opCode >> 15) & 0x3;
Size = (opCode >> 22) & 0x3;
RegisterSize = ((opCode >> 30) & 1) != 0
@@ -21,4 +21,4 @@ public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, a
: RegisterSize.Simd64;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs b/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs
index 05b32941a..e50cf12e6 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs
@@ -9,7 +9,7 @@ class OpCodeSimdCvt : OpCodeSimd
public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int scale = (opCode >> 10) & 0x3f;
- int sf = (opCode >> 31) & 0x1;
+ int sf = (opCode >> 31) & 0x1;
FBits = 64 - scale;
@@ -18,4 +18,4 @@ public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst
: RegisterSize.Int32;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdExt.cs b/src/ARMeilleure/Decoders/OpCodeSimdExt.cs
index a0e264d9d..0a3359e13 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdExt.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdExt.cs
@@ -11,4 +11,4 @@ public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst
Imm4 = (opCode >> 11) & 0xf;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs b/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs
index aa16e0c19..510cd3101 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs
@@ -10,7 +10,7 @@ class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond
public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Nzcv = (opCode >> 0) & 0xf;
+ Nzcv = (opCode >> 0) & 0xf;
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs b/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs
index 9f9062b8d..662abe284 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs
@@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimdFmov : OpCode, IOpCodeSimd
{
- public int Rd { get; }
+ public int Rd { get; }
public long Immediate { get; }
- public int Size { get; }
+ public int Size { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode);
@@ -16,7 +16,7 @@ public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(ins
long imm;
- Rd = (opCode >> 0) & 0x1f;
+ Rd = (opCode >> 0) & 0x1f;
imm = (opCode >> 13) & 0xff;
if (type == 0)
@@ -29,4 +29,4 @@ public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(ins
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs b/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs
index 02f74d030..b006cc954 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
public static class OpCodeSimdHelper
{
@@ -52,17 +52,20 @@ public static (long Immediate, int Size) GetSimdImmediateAndSize(int cMode, int
else if ((modeHigh & 0b110) == 0b100)
{
// 16-bits shifted Immediate.
- size = 1; imm <<= (modeHigh & 1) << 3;
+ size = 1;
+ imm <<= (modeHigh & 1) << 3;
}
else if ((modeHigh & 0b100) == 0b000)
{
// 32-bits shifted Immediate.
- size = 2; imm <<= modeHigh << 3;
+ size = 2;
+ imm <<= modeHigh << 3;
}
else if ((modeHigh & 0b111) == 0b110)
{
// 32-bits shifted Immediate (fill with ones).
- size = 2; imm = ShlOnes(imm, 8 << modeLow);
+ size = 2;
+ imm = ShlOnes(imm, 8 << modeLow);
}
else
{
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdImm.cs b/src/ARMeilleure/Decoders/OpCodeSimdImm.cs
index eeca77096..3f4bad7f7 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdImm.cs
@@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimdImm : OpCode, IOpCodeSimd
{
- public int Rd { get; }
+ public int Rd { get; }
public long Immediate { get; }
- public int Size { get; }
+ public int Size { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode);
@@ -13,14 +13,14 @@ public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst
Rd = opCode & 0x1f;
int cMode = (opCode >> 12) & 0xf;
- int op = (opCode >> 29) & 0x1;
+ int op = (opCode >> 29) & 0x1;
- int modeLow = cMode & 1;
+ int modeLow = cMode & 1;
int modeHigh = cMode >> 1;
long imm;
- imm = ((uint)opCode >> 5) & 0x1f;
+ imm = ((uint)opCode >> 5) & 0x1f;
imm |= ((uint)opCode >> 11) & 0xe0;
if (modeHigh == 0b111)
@@ -67,17 +67,20 @@ public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst
else if ((modeHigh & 0b110) == 0b100)
{
// 16-bits shifted Immediate.
- Size = 1; imm <<= (modeHigh & 1) << 3;
+ Size = 1;
+ imm <<= (modeHigh & 1) << 3;
}
else if ((modeHigh & 0b100) == 0b000)
{
// 32-bits shifted Immediate.
- Size = 2; imm <<= modeHigh << 3;
+ Size = 2;
+ imm <<= modeHigh << 3;
}
else if ((modeHigh & 0b111) == 0b110)
{
// 32-bits shifted Immediate (fill with ones).
- Size = 2; imm = ShlOnes(imm, 8 << modeLow);
+ Size = 2;
+ imm = ShlOnes(imm, 8 << modeLow);
}
else
{
@@ -104,4 +107,4 @@ private static long ShlOnes(long value, int shift)
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdIns.cs b/src/ARMeilleure/Decoders/OpCodeSimdIns.cs
index f6f9249d1..95436879c 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdIns.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdIns.cs
@@ -23,14 +23,22 @@ public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst
switch (Size)
{
- case 1: Size = 0; break;
- case 2: Size = 1; break;
- case 4: Size = 2; break;
- case 8: Size = 3; break;
+ case 1:
+ Size = 0;
+ break;
+ case 2:
+ Size = 1;
+ break;
+ case 4:
+ Size = 2;
+ break;
+ case 8:
+ Size = 3;
+ break;
}
- SrcIndex = imm4 >> Size;
+ SrcIndex = imm4 >> Size;
DstIndex = imm5 >> (Size + 1);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs
index c11594cb0..14a9d7c9c 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs
@@ -25,4 +25,4 @@ public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(i
Extend64 = false;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs
index 8e2129661..efa558bf9 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs
@@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit
{
- public int Rt { get; }
+ public int Rt { get; }
public long Immediate { get; }
- public int Size { get; }
- public bool Signed => false;
+ public int Size { get; }
+ public bool Signed => false;
public bool Prefetch => false;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode);
@@ -28,4 +28,4 @@ public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode) : base(i
Size = opc + 2;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs
index 8922c18f6..c05b52494 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs
@@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd
{
- public int Reps { get; }
- public int SElems { get; }
- public int Elems { get; }
- public bool WBack { get; }
+ public int Reps { get; }
+ public int SElems { get; }
+ public int Elems { get; }
+ public bool WBack { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode);
@@ -13,18 +13,41 @@ public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(in
{
switch ((opCode >> 12) & 0xf)
{
- case 0b0000: Reps = 1; SElems = 4; break;
- case 0b0010: Reps = 4; SElems = 1; break;
- case 0b0100: Reps = 1; SElems = 3; break;
- case 0b0110: Reps = 3; SElems = 1; break;
- case 0b0111: Reps = 1; SElems = 1; break;
- case 0b1000: Reps = 1; SElems = 2; break;
- case 0b1010: Reps = 2; SElems = 1; break;
-
- default: Instruction = InstDescriptor.Undefined; return;
+ case 0b0000:
+ Reps = 1;
+ SElems = 4;
+ break;
+ case 0b0010:
+ Reps = 4;
+ SElems = 1;
+ break;
+ case 0b0100:
+ Reps = 1;
+ SElems = 3;
+ break;
+ case 0b0110:
+ Reps = 3;
+ SElems = 1;
+ break;
+ case 0b0111:
+ Reps = 1;
+ SElems = 1;
+ break;
+ case 0b1000:
+ Reps = 1;
+ SElems = 2;
+ break;
+ case 0b1010:
+ Reps = 2;
+ SElems = 1;
+ break;
+
+ default:
+ Instruction = InstDescriptor.Undefined;
+ return;
}
- Size = (opCode >> 10) & 3;
+ Size = (opCode >> 10) & 3;
WBack = ((opCode >> 23) & 1) != 0;
bool q = ((opCode >> 30) & 1) != 0;
@@ -45,4 +68,4 @@ public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(in
Elems = (GetBitsCount() >> 3) >> Size;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs
index 1ab953679..697163896 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs
@@ -13,4 +13,4 @@ public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(
DecodeImm(opCode);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs
index 9ea6dda37..be7b25b9d 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs
@@ -18,4 +18,4 @@ public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode) : base(i
Extend64 = false;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs
index 44abdd389..5bc614e19 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs
@@ -2,21 +2,21 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd
{
- public int SElems { get; }
- public int Index { get; }
+ public int SElems { get; }
+ public int Index { get; }
public bool Replicate { get; }
- public bool WBack { get; }
+ public bool WBack { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode);
public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- int size = (opCode >> 10) & 3;
- int s = (opCode >> 12) & 1;
+ int size = (opCode >> 10) & 3;
+ int s = (opCode >> 12) & 1;
int sElems = (opCode >> 12) & 2;
- int scale = (opCode >> 14) & 3;
- int l = (opCode >> 22) & 1;
- int q = (opCode >> 30) & 1;
+ int scale = (opCode >> 14) & 3;
+ int l = (opCode >> 22) & 1;
+ int q = (opCode >> 30) & 1;
sElems |= (opCode >> 21) & 1;
@@ -27,63 +27,63 @@ public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(in
switch (scale)
{
case 1:
- {
- if ((size & 1) != 0)
{
- Instruction = InstDescriptor.Undefined;
+ if ((size & 1) != 0)
+ {
+ Instruction = InstDescriptor.Undefined;
- return;
- }
-
- index >>= 1;
-
- break;
- }
+ return;
+ }
- case 2:
- {
- if ((size & 2) != 0 ||
- ((size & 1) != 0 && s != 0))
- {
- Instruction = InstDescriptor.Undefined;
+ index >>= 1;
- return;
+ break;
}
- if ((size & 1) != 0)
- {
- index >>= 3;
-
- scale = 3;
- }
- else
+ case 2:
{
- index >>= 2;
+ if ((size & 2) != 0 ||
+ ((size & 1) != 0 && s != 0))
+ {
+ Instruction = InstDescriptor.Undefined;
+
+ return;
+ }
+
+ if ((size & 1) != 0)
+ {
+ index >>= 3;
+
+ scale = 3;
+ }
+ else
+ {
+ index >>= 2;
+ }
+
+ break;
}
- break;
- }
-
case 3:
- {
- if (l == 0 || s != 0)
{
- Instruction = InstDescriptor.Undefined;
+ if (l == 0 || s != 0)
+ {
+ Instruction = InstDescriptor.Undefined;
- return;
- }
+ return;
+ }
- scale = size;
+ scale = size;
- Replicate = true;
+ Replicate = true;
- break;
- }
+ break;
+ }
}
- Index = index;
+ Index = index;
SElems = sElems;
- Size = scale;
+ Size = scale;
Extend64 = false;
@@ -94,4 +94,4 @@ public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(in
: RegisterSize.Simd64;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdReg.cs b/src/ARMeilleure/Decoders/OpCodeSimdReg.cs
index ac4f71dae..40f9b1c53 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdReg.cs
@@ -3,16 +3,16 @@ namespace ARMeilleure.Decoders
class OpCodeSimdReg : OpCodeSimd
{
public bool Bit3 { get; }
- public int Ra { get; }
- public int Rm { get; protected set; }
+ public int Ra { get; }
+ public int Rm { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdReg(inst, address, opCode);
public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Bit3 = ((opCode >> 3) & 0x1) != 0;
- Ra = (opCode >> 10) & 0x1f;
- Rm = (opCode >> 16) & 0x1f;
+ Bit3 = ((opCode >> 3) & 0x1) != 0;
+ Ra = (opCode >> 10) & 0x1f;
+ Rm = (opCode >> 16) & 0x1f;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs b/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs
index 92368deea..bb248ab6b 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs
@@ -12,7 +12,7 @@ public OpCodeSimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(
{
case 1:
Index = (opCode >> 20) & 3 |
- (opCode >> 9) & 4;
+ (opCode >> 9) & 4;
Rm &= 0xf;
@@ -24,8 +24,10 @@ public OpCodeSimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(
break;
- default: Instruction = InstDescriptor.Undefined; break;
+ default:
+ Instruction = InstDescriptor.Undefined;
+ break;
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs b/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs
index d46dd57ed..c97bd787e 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs
@@ -26,7 +26,9 @@ public OpCodeSimdRegElemF(InstDescriptor inst, ulong address, int opCode) : base
break;
- default: Instruction = InstDescriptor.Undefined; break;
+ default:
+ Instruction = InstDescriptor.Undefined;
+ break;
}
}
}
diff --git a/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs b/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs
index 9c631e485..3a7ef6aba 100644
--- a/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs
@@ -9,4 +9,4 @@ public OpCodeSimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst
Size = ((opCode >> 13) & 3) + 1;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeSystem.cs b/src/ARMeilleure/Decoders/OpCodeSystem.cs
index 4d79421a8..215134153 100644
--- a/src/ARMeilleure/Decoders/OpCodeSystem.cs
+++ b/src/ARMeilleure/Decoders/OpCodeSystem.cs
@@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders
{
class OpCodeSystem : OpCode
{
- public int Rt { get; }
+ public int Rt { get; }
public int Op2 { get; }
public int CRm { get; }
public int CRn { get; }
@@ -13,12 +13,12 @@ class OpCodeSystem : OpCode
public OpCodeSystem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rt = (opCode >> 0) & 0x1f;
- Op2 = (opCode >> 5) & 0x7;
- CRm = (opCode >> 8) & 0xf;
- CRn = (opCode >> 12) & 0xf;
- Op1 = (opCode >> 16) & 0x7;
+ Rt = (opCode >> 0) & 0x1f;
+ Op2 = (opCode >> 5) & 0x7;
+ CRm = (opCode >> 8) & 0xf;
+ CRn = (opCode >> 12) & 0xf;
+ Op1 = (opCode >> 16) & 0x7;
Op0 = ((opCode >> 19) & 0x1) | 2;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT16.cs b/src/ARMeilleure/Decoders/OpCodeT16.cs
index 9c3d6b006..de946b961 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16.cs
@@ -12,4 +12,4 @@ public OpCodeT16(InstDescriptor inst, ulong address, int opCode) : base(inst, ad
OpCodeSizeInBytes = 2;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs b/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
index 95f180548..683d638a8 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
@@ -1,6 +1,6 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
- class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm
+ class OpCodeT16AddSubImm3 : OpCodeT16, IOpCode32AluImm
{
public int Rd { get; }
public int Rn { get; }
@@ -15,8 +15,8 @@ class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm
public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rd = (opCode >> 0) & 0x7;
- Rn = (opCode >> 3) & 0x7;
+ Rd = (opCode >> 0) & 0x7;
+ Rn = (opCode >> 3) & 0x7;
Immediate = (opCode >> 6) & 0x7;
IsRotated = false;
}
diff --git a/src/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs b/src/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs
index 2a407b2d2..201fc8aab 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16AddSubReg : OpCodeT16, IOpCode32AluReg
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16AluImm8.cs b/src/ARMeilleure/Decoders/OpCodeT16AluImm8.cs
index 673a46045..122698d7e 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16AluImm8.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16AluImm8.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16AluImm8 : OpCodeT16, IOpCode32AluImm
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16AluImmZero.cs b/src/ARMeilleure/Decoders/OpCodeT16AluImmZero.cs
index b23f8fe03..f67a75f96 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16AluImmZero.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16AluImmZero.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16AluImmZero : OpCodeT16, IOpCode32AluImm
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs b/src/ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs
index 6d5ac8fd3..5458f65f2 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16AluRegHigh : OpCodeT16, IOpCode32AluReg
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16AluRegLow.cs b/src/ARMeilleure/Decoders/OpCodeT16AluRegLow.cs
index b37b4f661..f86f48bd4 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16AluRegLow.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16AluRegLow.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16AluRegLow : OpCodeT16, IOpCode32AluReg
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs b/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs
index f230b20e2..5ed8a4e6c 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16BImm11 : OpCodeT16, IOpCode32BImm
{
@@ -8,7 +8,7 @@ class OpCodeT16BImm11 : OpCodeT16, IOpCode32BImm
public OpCodeT16BImm11(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- int imm = (opCode << 21) >> 20;
+ int imm = (opCode << 21) >> 20;
Immediate = GetPc() + imm;
}
}
diff --git a/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs b/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs
index 5f6842983..85318e5be 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16BImm8 : OpCodeT16, IOpCode32BImm
{
@@ -10,7 +10,7 @@ public OpCodeT16BImm8(InstDescriptor inst, ulong address, int opCode) : base(ins
{
Cond = (Condition)((opCode >> 8) & 0xf);
- int imm = (opCode << 24) >> 23;
+ int imm = (opCode << 24) >> 23;
Immediate = GetPc() + imm;
}
}
diff --git a/src/ARMeilleure/Decoders/OpCodeT16BReg.cs b/src/ARMeilleure/Decoders/OpCodeT16BReg.cs
index 3122cd07e..da2a007a5 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16BReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16BReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16BReg : OpCodeT16, IOpCode32BReg
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16Exception.cs b/src/ARMeilleure/Decoders/OpCodeT16Exception.cs
index bb0050834..8ccdf09ba 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16Exception.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16Exception.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16Exception : OpCodeT16, IOpCode32Exception
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16IfThen.cs b/src/ARMeilleure/Decoders/OpCodeT16IfThen.cs
index 8c3de689e..ea435a79b 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16IfThen.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16IfThen.cs
@@ -1,4 +1,4 @@
-using System.Collections.Generic;
+using System.Collections.Generic;
namespace ARMeilleure.Decoders
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs b/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs
index 20ef31e27..e9b383989 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Instructions;
+using ARMeilleure.Instructions;
using System;
namespace ARMeilleure.Decoders
@@ -36,23 +36,13 @@ public OpCodeT16MemImm5(InstDescriptor inst, ulong address, int opCode) : base(i
break;
}
- switch (inst.Name)
+ Immediate = inst.Name switch
{
- case InstName.Str:
- case InstName.Ldr:
- Immediate = ((opCode >> 6) & 0x1f) << 2;
- break;
- case InstName.Strb:
- case InstName.Ldrb:
- Immediate = ((opCode >> 6) & 0x1f);
- break;
- case InstName.Strh:
- case InstName.Ldrh:
- Immediate = ((opCode >> 6) & 0x1f) << 1;
- break;
- default:
- throw new InvalidOperationException();
- }
+ InstName.Str or InstName.Ldr => ((opCode >> 6) & 0x1f) << 2,
+ InstName.Strb or InstName.Ldrb => ((opCode >> 6) & 0x1f),
+ InstName.Strh or InstName.Ldrh => ((opCode >> 6) & 0x1f) << 1,
+ _ => throw new InvalidOperationException(),
+ };
}
}
}
diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemLit.cs b/src/ARMeilleure/Decoders/OpCodeT16MemLit.cs
index f8c16e299..63a452ad3 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16MemLit.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16MemLit.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.State;
+using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs b/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs
index f4185cfcb..92b027a6e 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Instructions;
+using ARMeilleure.Instructions;
using System;
using System.Numerics;
@@ -27,7 +27,7 @@ public OpCodeT16MemMult(InstDescriptor inst, ulong address, int opCode) : base(i
{
InstName.Ldm => true,
InstName.Stm => false,
- _ => throw new InvalidOperationException()
+ _ => throw new InvalidOperationException(),
};
}
}
diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemReg.cs b/src/ARMeilleure/Decoders/OpCodeT16MemReg.cs
index 71100112e..17d6966b2 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16MemReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16MemReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16MemReg : OpCodeT16, IOpCode32MemReg
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemSp.cs b/src/ARMeilleure/Decoders/OpCodeT16MemSp.cs
index a038b915b..ed42679a5 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16MemSp.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16MemSp.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.State;
+using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemStack.cs b/src/ARMeilleure/Decoders/OpCodeT16MemStack.cs
index 9d7b0d203..28d5db4d9 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16MemStack.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16MemStack.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Instructions;
+using ARMeilleure.Instructions;
using ARMeilleure.State;
using System;
using System.Numerics;
diff --git a/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs b/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs
index a540026ec..18e7b9e2e 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16ShiftImm : OpCodeT16, IOpCode32AluRsImm
{
@@ -15,8 +15,8 @@ class OpCodeT16ShiftImm : OpCodeT16, IOpCode32AluRsImm
public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rd = (opCode >> 0) & 0x7;
- Rm = (opCode >> 3) & 0x7;
+ Rd = (opCode >> 0) & 0x7;
+ Rm = (opCode >> 3) & 0x7;
Immediate = (opCode >> 6) & 0x1F;
ShiftType = (ShiftType)((opCode >> 11) & 3);
}
diff --git a/src/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs b/src/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs
index 9f8982814..ce47dfb5d 100644
--- a/src/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT16ShiftReg : OpCodeT16, IOpCode32AluRsReg
{
diff --git a/src/ARMeilleure/Decoders/OpCodeT32.cs b/src/ARMeilleure/Decoders/OpCodeT32.cs
index cf43d4298..87a0520d9 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT32 : OpCode32
{
@@ -12,4 +12,4 @@ public OpCodeT32(InstDescriptor inst, ulong address, int opCode) : base(inst, ad
OpCodeSizeInBytes = 4;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32Alu.cs b/src/ARMeilleure/Decoders/OpCodeT32Alu.cs
index a81b3b3dc..cdef007a9 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32Alu.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32Alu.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT32Alu : OpCodeT32, IOpCode32Alu
{
@@ -17,4 +17,4 @@ public OpCodeT32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst,
SetFlags = ((opCode >> 20) & 1) != 0;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs b/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs
index 0895c29b4..ce88964c9 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Common;
+using ARMeilleure.Common;
using System.Runtime.Intrinsics;
namespace ARMeilleure.Decoders
@@ -35,4 +35,4 @@ public OpCodeT32AluImm(InstDescriptor inst, ulong address, int opCode) : base(in
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs b/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs
index 31de63dd3..12b65a100 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs
@@ -13,4 +13,4 @@ public OpCodeT32AluImm12(InstDescriptor inst, ulong address, int opCode) : base(
Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs b/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs
index a487f55a6..4ac983470 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs
@@ -11,4 +11,4 @@ public OpCodeT32AluReg(InstDescriptor inst, ulong address, int opCode) : base(in
Rm = (opCode >> 0) & 0xf;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs b/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs
index 1c9ba7a2c..dad0d9575 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs
@@ -1,8 +1,8 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm
{
- public int Rm { get; }
+ public int Rm { get; }
public int Immediate { get; }
public ShiftType ShiftType { get; }
@@ -11,10 +11,10 @@ class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm
public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
- Rm = (opCode >> 0) & 0xf;
+ Rm = (opCode >> 0) & 0xf;
Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c);
ShiftType = (ShiftType)((opCode >> 4) & 3);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs b/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs
index b6da8abdb..793f82627 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT32BImm20 : OpCodeT32, IOpCode32BImm
{
@@ -24,4 +24,4 @@ public OpCodeT32BImm20(InstDescriptor inst, ulong address, int opCode) : base(in
Cond = (Condition)((opCode >> 22) & 0xf);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs b/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs
index 774ec3a64..d35ab8a45 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Instructions;
+using ARMeilleure.Instructions;
namespace ARMeilleure.Decoders
{
@@ -32,4 +32,4 @@ public OpCodeT32BImm24(InstDescriptor inst, ulong address, int opCode) : base(in
Immediate = pc + imm32;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs
index 7838604b2..aac8dbfba 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT32MemImm12 : OpCodeT32, IOpCode32Mem
{
@@ -22,4 +22,4 @@ public OpCodeT32MemImm12(InstDescriptor inst, ulong address, int opCode) : base(
IsLoad = ((opCode >> 20) & 1) != 0;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs
index d8b7763cb..d80ce86c5 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Decoders
+namespace ARMeilleure.Decoders
{
class OpCodeT32MemImm8 : OpCodeT32, IOpCode32Mem
{
@@ -18,7 +18,7 @@ public OpCodeT32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(i
Rn = (opCode >> 16) & 0xf;
Index = ((opCode >> 10) & 1) != 0;
- Add = ((opCode >> 9) & 1) != 0;
+ Add = ((opCode >> 9) & 1) != 0;
WBack = ((opCode >> 8) & 1) != 0;
Immediate = opCode & 0xff;
@@ -26,4 +26,4 @@ public OpCodeT32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(i
IsLoad = ((opCode >> 20) & 1) != 0;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs
index 7a078c489..51f5042f2 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs
@@ -20,7 +20,7 @@ public OpCodeT32MemImm8D(InstDescriptor inst, ulong address, int opCode) : base(
Rn = (opCode >> 16) & 0xf;
Index = ((opCode >> 24) & 1) != 0;
- Add = ((opCode >> 23) & 1) != 0;
+ Add = ((opCode >> 23) & 1) != 0;
WBack = ((opCode >> 21) & 1) != 0;
Immediate = (opCode & 0xff) << 2;
@@ -28,4 +28,4 @@ public OpCodeT32MemImm8D(InstDescriptor inst, ulong address, int opCode) : base(
IsLoad = ((opCode >> 20) & 1) != 0;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs b/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs
index a9ba306dc..d155842a6 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs
@@ -7,8 +7,8 @@ class OpCodeT32MemMult : OpCodeT32, IOpCode32MemMult
public int Rn { get; }
public int RegisterMask { get; }
- public int Offset { get; }
- public int PostOffset { get; }
+ public int Offset { get; }
+ public int PostOffset { get; }
public bool IsLoad { get; }
@@ -19,9 +19,9 @@ public OpCodeT32MemMult(InstDescriptor inst, ulong address, int opCode) : base(i
Rn = (opCode >> 16) & 0xf;
bool isLoad = (opCode & (1 << 20)) != 0;
- bool w = (opCode & (1 << 21)) != 0;
- bool u = (opCode & (1 << 23)) != 0;
- bool p = (opCode & (1 << 24)) != 0;
+ bool w = (opCode & (1 << 21)) != 0;
+ bool u = (opCode & (1 << 23)) != 0;
+ bool p = (opCode & (1 << 24)) != 0;
RegisterMask = opCode & 0xffff;
@@ -49,4 +49,4 @@ public OpCodeT32MemMult(InstDescriptor inst, ulong address, int opCode) : base(i
IsLoad = isLoad;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs b/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs
index 5161892bb..2f871c740 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs
@@ -4,8 +4,6 @@ class OpCodeT32MovImm16 : OpCodeT32Alu, IOpCode32AluImm16
{
public int Immediate { get; }
- public bool IsRotated => false;
-
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MovImm16(inst, address, opCode);
public OpCodeT32MovImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
@@ -13,4 +11,4 @@ public OpCodeT32MovImm16(InstDescriptor inst, ulong address, int opCode) : base(
Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800) | ((opCode >> 4) & 0xf000);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeT32Tb.cs b/src/ARMeilleure/Decoders/OpCodeT32Tb.cs
index 527754b1f..0a4d2a6c4 100644
--- a/src/ARMeilleure/Decoders/OpCodeT32Tb.cs
+++ b/src/ARMeilleure/Decoders/OpCodeT32Tb.cs
@@ -13,4 +13,4 @@ public OpCodeT32Tb(InstDescriptor inst, ulong address, int opCode) : base(inst,
Rn = (opCode >> 16) & 0xf;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/OpCodeTable.cs b/src/ARMeilleure/Decoders/OpCodeTable.cs
index 4f3599583..9e13bd9b5 100644
--- a/src/ARMeilleure/Decoders/OpCodeTable.cs
+++ b/src/ARMeilleure/Decoders/OpCodeTable.cs
@@ -13,7 +13,7 @@ static class OpCodeTable
private readonly struct InstInfo
{
- public int Mask { get; }
+ public int Mask { get; }
public int Value { get; }
public InstDescriptor Inst { get; }
@@ -22,24 +22,25 @@ private readonly struct InstInfo
public InstInfo(int mask, int value, InstDescriptor inst, MakeOp makeOp)
{
- Mask = mask;
- Value = value;
- Inst = inst;
+ Mask = mask;
+ Value = value;
+ Inst = inst;
MakeOp = makeOp;
}
}
- private static List AllInstA32 = new();
- private static List AllInstT32 = new();
- private static List AllInstA64 = new();
+ private static readonly List _allInstA32 = new();
+ private static readonly List _allInstT32 = new();
+ private static readonly List _allInstA64 = new();
- private static InstInfo[][] InstA32FastLookup = new InstInfo[FastLookupSize][];
- private static InstInfo[][] InstT32FastLookup = new InstInfo[FastLookupSize][];
- private static InstInfo[][] InstA64FastLookup = new InstInfo[FastLookupSize][];
+ private static readonly InstInfo[][] _instA32FastLookup = new InstInfo[FastLookupSize][];
+ private static readonly InstInfo[][] _instT32FastLookup = new InstInfo[FastLookupSize][];
+ private static readonly InstInfo[][] _instA64FastLookup = new InstInfo[FastLookupSize][];
static OpCodeTable()
{
-#region "OpCode Table (AArch64)"
+#pragma warning disable IDE0055 // Disable formatting
+ #region "OpCode Table (AArch64)"
// Base
SetA64("x0011010000xxxxx000000xxxxxxxxxx", InstName.Adc, InstEmit.Adc, OpCodeAluRs.Create);
SetA64("x0111010000xxxxx000000xxxxxxxxxx", InstName.Adcs, InstEmit.Adcs, OpCodeAluRs.Create);
@@ -329,6 +330,7 @@ static OpCodeTable()
SetA64("011111100x110000110010xxxxxxxxxx", InstName.Fmaxnmp_S, InstEmit.Fmaxnmp_S, OpCodeSimd.Create);
SetA64("0>1011100<1xxxxx110001xxxxxxxxxx", InstName.Fmaxnmp_V, InstEmit.Fmaxnmp_V, OpCodeSimdReg.Create);
SetA64("0110111000110000110010xxxxxxxxxx", InstName.Fmaxnmv_V, InstEmit.Fmaxnmv_V, OpCodeSimd.Create);
+ SetA64("011111100x110000111110xxxxxxxxxx", InstName.Fmaxp_S, InstEmit.Fmaxp_S, OpCodeSimd.Create);
SetA64("0>1011100<1xxxxx111101xxxxxxxxxx", InstName.Fmaxp_V, InstEmit.Fmaxp_V, OpCodeSimdReg.Create);
SetA64("0110111000110000111110xxxxxxxxxx", InstName.Fmaxv_V, InstEmit.Fmaxv_V, OpCodeSimd.Create);
SetA64("000111100x1xxxxx010110xxxxxxxxxx", InstName.Fmin_S, InstEmit.Fmin_S, OpCodeSimdReg.Create);
@@ -338,6 +340,7 @@ static OpCodeTable()
SetA64("011111101x110000110010xxxxxxxxxx", InstName.Fminnmp_S, InstEmit.Fminnmp_S, OpCodeSimd.Create);
SetA64("0>1011101<1xxxxx110001xxxxxxxxxx", InstName.Fminnmp_V, InstEmit.Fminnmp_V, OpCodeSimdReg.Create);
SetA64("0110111010110000110010xxxxxxxxxx", InstName.Fminnmv_V, InstEmit.Fminnmv_V, OpCodeSimd.Create);
+ SetA64("011111101x110000111110xxxxxxxxxx", InstName.Fminp_S, InstEmit.Fminp_S, OpCodeSimd.Create);
SetA64("0>1011101<1xxxxx111101xxxxxxxxxx", InstName.Fminp_V, InstEmit.Fminp_V, OpCodeSimdReg.Create);
SetA64("0110111010110000111110xxxxxxxxxx", InstName.Fminv_V, InstEmit.Fminv_V, OpCodeSimd.Create);
SetA64("010111111xxxxxxx0001x0xxxxxxxxxx", InstName.Fmla_Se, InstEmit.Fmla_Se, OpCodeSimdRegElemF.Create);
@@ -638,9 +641,9 @@ static OpCodeTable()
SetA64("0x001110<<100001001010xxxxxxxxxx", InstName.Xtn_V, InstEmit.Xtn_V, OpCodeSimd.Create);
SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", InstName.Zip1_V, InstEmit.Zip1_V, OpCodeSimdReg.Create);
SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstName.Zip2_V, InstEmit.Zip2_V, OpCodeSimdReg.Create);
-#endregion
+ #endregion
-#region "OpCode Table (AArch32, A32)"
+ #region "OpCode Table (AArch32, A32)"
// Base
SetA32("<<<<0010101xxxxxxxxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluImm.Create);
SetA32("<<<<0000101xxxxxxxxxxxxxxxx0xxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluRsImm.Create);
@@ -882,177 +885,178 @@ static OpCodeTable()
SetVfp("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub, InstEmit32.Vsub_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
// ASIMD
- SetAsimd("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V, InstEmit32.Aesd_V, OpCode32Simd.Create, OpCode32Simd.CreateT32);
- SetAsimd("111100111x110000xxx0001100x0xxx0", InstName.Aese_V, InstEmit32.Aese_V, OpCode32Simd.Create, OpCode32Simd.CreateT32);
- SetAsimd("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V, InstEmit32.Aesimc_V, OpCode32Simd.Create, OpCode32Simd.CreateT32);
- SetAsimd("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V, InstEmit32.Aesmc_V, OpCode32Simd.Create, OpCode32Simd.CreateT32);
- SetAsimd("111100110x00xxx0xxx01100x1x0xxx0", InstName.Sha256h_V, InstEmit32.Sha256h_V, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
- SetAsimd("111100110x01xxx0xxx01100x1x0xxx0", InstName.Sha256h2_V, InstEmit32.Sha256h2_V, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
- SetAsimd("111100111x111010xxx0001111x0xxx0", InstName.Sha256su0_V, InstEmit32.Sha256su0_V, OpCode32Simd.Create, OpCode32Simd.CreateT32);
- SetAsimd("111100110x10xxx0xxx01100x1x0xxx0", InstName.Sha256su1_V, InstEmit32.Sha256su1_V, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
- SetAsimd("1111001x0x<xxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
- SetAsimd("111101000x10xxxxxxxx000x<>>xxxxxxx100101x1xxx0", InstName.Vqrshrn, InstEmit32.Vqrshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
- SetAsimd("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun, InstEmit32.Vqrshrun, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
- SetAsimd("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn, InstEmit32.Vqshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
- SetAsimd("111100111x>>>xxxxxxx100000x1xxx0", InstName.Vqshrun, InstEmit32.Vqshrun, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
- SetAsimd("1111001x0xxxxxxxxxxx0010xxx1xxxx", InstName.Vqsub, InstEmit32.Vqsub, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
- SetAsimd("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe, InstEmit32.Vrecpe, OpCode32SimdSqrte.Create, OpCode32SimdSqrte.CreateT32);
- SetAsimd("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps, InstEmit32.Vrecps, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
- SetAsimd("111100111x11xx00xxxx000<>>xxxxxxx0010>xx1xxxx", InstName.Vrshr, InstEmit32.Vrshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
- SetAsimd("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn, InstEmit32.Vrshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
- SetAsimd("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte, InstEmit32.Vrsqrte, OpCode32SimdSqrte.Create, OpCode32SimdSqrte.CreateT32);
- SetAsimd("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts, InstEmit32.Vrsqrts, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
- SetAsimd("1111001x1x>>>xxxxxxx0011>xx1xxxx", InstName.Vrsra, InstEmit32.Vrsra, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
- SetAsimd("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl, InstEmit32.Vshl, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
- SetAsimd("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl, InstEmit32.Vshl_I, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
- SetAsimd("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll, InstEmit32.Vshll, OpCode32SimdShImmLong.Create, OpCode32SimdShImmLong.CreateT32); // A1 encoding.
- SetAsimd("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
- SetAsimd("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
- SetAsimd("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra, InstEmit32.Vsra, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
- SetAsimd("111101001x00xxxxxxxx0000xxx0xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
- SetAsimd("111101001x00xxxxxxxx0100xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
- SetAsimd("111101001x00xxxxxxxx1000x000xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
- SetAsimd("111101001x00xxxxxxxx1000x011xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
- SetAsimd("111101000x00xxxxxxxx0111xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create, OpCode32SimdMemPair.CreateT32); // Regs = 1.
- SetAsimd("111101000x00xxxxxxxx1010xx<xxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
+ SetAsimd("111101000x10xxxxxxxx000x<>>xxxxxxx100101x1xxx0", InstName.Vqrshrn, InstEmit32.Vqrshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+ SetAsimd("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun, InstEmit32.Vqrshrun, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+ SetAsimd("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn, InstEmit32.Vqshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+ SetAsimd("111100111x>>>xxxxxxx100000x1xxx0", InstName.Vqshrun, InstEmit32.Vqshrun, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+ SetAsimd("1111001x0xxxxxxxxxxx0010xxx1xxxx", InstName.Vqsub, InstEmit32.Vqsub, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
+ SetAsimd("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe, InstEmit32.Vrecpe, OpCode32SimdSqrte.Create, OpCode32SimdSqrte.CreateT32);
+ SetAsimd("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps, InstEmit32.Vrecps, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
+ SetAsimd("111100111x11xx00xxxx000<>>xxxxxxx0010>xx1xxxx", InstName.Vrshr, InstEmit32.Vrshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
+ SetAsimd("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn, InstEmit32.Vrshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+ SetAsimd("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte, InstEmit32.Vrsqrte, OpCode32SimdSqrte.Create, OpCode32SimdSqrte.CreateT32);
+ SetAsimd("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts, InstEmit32.Vrsqrts, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
+ SetAsimd("1111001x1x>>>xxxxxxx0011>xx1xxxx", InstName.Vrsra, InstEmit32.Vrsra, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
+ SetAsimd("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl, InstEmit32.Vshl, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
+ SetAsimd("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl, InstEmit32.Vshl_I, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
+ SetAsimd("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll, InstEmit32.Vshll, OpCode32SimdShImmLong.Create, OpCode32SimdShImmLong.CreateT32); // A1 encoding.
+ SetAsimd("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
+ SetAsimd("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+ SetAsimd("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra, InstEmit32.Vsra, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
+ SetAsimd("111101001x00xxxxxxxx0000xxx0xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
+ SetAsimd("111101001x00xxxxxxxx0100xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
+ SetAsimd("111101001x00xxxxxxxx1000x000xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
+ SetAsimd("111101001x00xxxxxxxx1000x011xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32);
+ SetAsimd("111101000x00xxxxxxxx0111xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create, OpCode32SimdMemPair.CreateT32); // Regs = 1.
+ SetAsimd("111101000x00xxxxxxxx1010xx< allInsts, Func ToFastLookupIndex)
+ private static void FillFastLookupTable(InstInfo[][] table, List allInsts, Func toFastLookupIndex)
{
List[] temp = new List[FastLookupSize];
@@ -1315,8 +1320,8 @@ private static void FillFastLookupTable(InstInfo[][] table, List allIn
foreach (InstInfo inst in allInsts)
{
- int mask = ToFastLookupIndex(inst.Mask);
- int value = ToFastLookupIndex(inst.Value);
+ int mask = toFastLookupIndex(inst.Mask);
+ int value = toFastLookupIndex(inst.Value);
for (int index = 0; index < temp.Length; index++)
{
@@ -1335,22 +1340,21 @@ private static void FillFastLookupTable(InstInfo[][] table, List allIn
private static void SetA32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
{
- Set(encoding, AllInstA32, new InstDescriptor(name, emitter), makeOp);
+ Set(encoding, _allInstA32, new InstDescriptor(name, emitter), makeOp);
}
private static void SetT16(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
{
encoding = "xxxxxxxxxxxxxxxx" + encoding;
- Set(encoding, AllInstT32, new InstDescriptor(name, emitter), makeOp);
+ Set(encoding, _allInstT32, new InstDescriptor(name, emitter), makeOp);
}
private static void SetT32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
{
string reversedEncoding = $"{encoding.AsSpan(16)}{encoding.AsSpan(0, 16)}";
- MakeOp reversedMakeOp =
- (inst, address, opCode)
+ OpCode ReversedMakeOp(InstDescriptor inst, ulong address, int opCode)
=> makeOp(inst, address, (int)BitOperations.RotateRight((uint)opCode, 16));
- Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp);
+ Set(reversedEncoding, _allInstT32, new InstDescriptor(name, emitter), ReversedMakeOp);
}
private static void SetVfp(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32)
@@ -1395,12 +1399,12 @@ private static void SetAsimd(string encoding, InstName name, InstEmitter emitter
private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
{
- Set(encoding, AllInstA64, new InstDescriptor(name, emitter), makeOp);
+ Set(encoding, _allInstA64, new InstDescriptor(name, emitter), makeOp);
}
private static void Set(string encoding, List list, InstDescriptor inst, MakeOp makeOp)
{
- int bit = encoding.Length - 1;
+ int bit = encoding.Length - 1;
int value = 0;
int xMask = 0;
int xBits = 0;
@@ -1439,7 +1443,7 @@ private static void Set(string encoding, List list, InstDescriptor ins
}
else if (chr != '0')
{
- throw new ArgumentException(nameof(encoding));
+ throw new ArgumentException($"Invalid encoding: {encoding}", nameof(encoding));
}
}
@@ -1470,17 +1474,17 @@ private static void Set(string encoding, List list, InstDescriptor ins
public static (InstDescriptor inst, MakeOp makeOp) GetInstA32(int opCode)
{
- return GetInstFromList(InstA32FastLookup[ToFastLookupIndexA(opCode)], opCode);
+ return GetInstFromList(_instA32FastLookup[ToFastLookupIndexA(opCode)], opCode);
}
public static (InstDescriptor inst, MakeOp makeOp) GetInstT32(int opCode)
{
- return GetInstFromList(InstT32FastLookup[ToFastLookupIndexT(opCode)], opCode);
+ return GetInstFromList(_instT32FastLookup[ToFastLookupIndexT(opCode)], opCode);
}
public static (InstDescriptor inst, MakeOp makeOp) GetInstA64(int opCode)
{
- return GetInstFromList(InstA64FastLookup[ToFastLookupIndexA(opCode)], opCode);
+ return GetInstFromList(_instA64FastLookup[ToFastLookupIndexA(opCode)], opCode);
}
private static (InstDescriptor inst, MakeOp makeOp) GetInstFromList(InstInfo[] insts, int opCode)
diff --git a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs
index 17c17812d..9d988f0c9 100644
--- a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs
+++ b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
using System.Collections.Generic;
namespace ARMeilleure.Decoders.Optimizations
@@ -17,26 +17,26 @@ public static Block[] RunPass(ulong entryAddress, List blocks)
throw new InvalidOperationException("Function entry point is not contained in a block.");
}
- const ulong allowance = 4;
+ const ulong Allowance = 4;
Block entryBlock = blocks[entryBlockId];
Block startBlock = entryBlock;
- Block endBlock = entryBlock;
+ Block endBlock = entryBlock;
int startBlockIndex = entryBlockId;
- int endBlockIndex = entryBlockId;
+ int endBlockIndex = entryBlockId;
for (int i = entryBlockId + 1; i < blocks.Count; i++) // Search forwards.
{
Block block = blocks[i];
- if (endBlock.EndAddress < block.Address - allowance)
+ if (endBlock.EndAddress < block.Address - Allowance)
{
break; // End of contiguous function.
}
- endBlock = block;
+ endBlock = block;
endBlockIndex = i;
}
@@ -44,12 +44,12 @@ public static Block[] RunPass(ulong entryAddress, List blocks)
{
Block block = blocks[i];
- if (startBlock.Address > block.EndAddress + allowance)
+ if (startBlock.Address > block.EndAddress + Allowance)
{
break; // End of contiguous function.
}
- startBlock = block;
+ startBlock = block;
startBlockIndex = i;
}
@@ -57,7 +57,7 @@ public static Block[] RunPass(ulong entryAddress, List blocks)
{
return blocks.ToArray(); // Nothing to do here.
}
-
+
// Mark branches whose target is outside of the contiguous region as an exit block.
for (int i = startBlockIndex; i <= endBlockIndex; i++)
{
@@ -69,7 +69,7 @@ public static Block[] RunPass(ulong entryAddress, List blocks)
}
}
- var newBlocks = new List(blocks.Count);
+ var newBlocks = new List(blocks.Count);
// Finally, rebuild decoded block list, ignoring blocks outside the contiguous range.
for (int i = 0; i < blocks.Count; i++)
diff --git a/src/ARMeilleure/Decoders/RegisterSize.cs b/src/ARMeilleure/Decoders/RegisterSize.cs
index c9cea03ed..7c00984e8 100644
--- a/src/ARMeilleure/Decoders/RegisterSize.cs
+++ b/src/ARMeilleure/Decoders/RegisterSize.cs
@@ -5,6 +5,6 @@ enum RegisterSize
Int32,
Int64,
Simd64,
- Simd128
+ Simd128,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Decoders/ShiftType.cs b/src/ARMeilleure/Decoders/ShiftType.cs
index 8583f16ad..43b738f3f 100644
--- a/src/ARMeilleure/Decoders/ShiftType.cs
+++ b/src/ARMeilleure/Decoders/ShiftType.cs
@@ -5,6 +5,6 @@ enum ShiftType
Lsl = 0,
Lsr = 1,
Asr = 2,
- Ror = 3
+ Ror = 3,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Diagnostics/IRDumper.cs b/src/ARMeilleure/Diagnostics/IRDumper.cs
index 3d1a60e58..16833d085 100644
--- a/src/ARMeilleure/Diagnostics/IRDumper.cs
+++ b/src/ARMeilleure/Diagnostics/IRDumper.cs
@@ -34,7 +34,9 @@ private void Indent()
for (int index = 0; index < _indentLevel; index++)
{
+#pragma warning disable CA1834 // Use StringBuilder.Append(char) for single character strings
_builder.Append(Indentation);
+#pragma warning restore CA1834
}
}
@@ -110,10 +112,18 @@ private void DumpOperand(Operand operand)
switch (reg.Type)
{
- case RegisterType.Flag: _builder.Append('b'); break;
- case RegisterType.FpFlag: _builder.Append('f'); break;
- case RegisterType.Integer: _builder.Append('r'); break;
- case RegisterType.Vector: _builder.Append('v'); break;
+ case RegisterType.Flag:
+ _builder.Append('b');
+ break;
+ case RegisterType.FpFlag:
+ _builder.Append('f');
+ break;
+ case RegisterType.Integer:
+ _builder.Append('r');
+ break;
+ case RegisterType.Vector:
+ _builder.Append('v');
+ break;
}
_builder.Append(reg.Index);
@@ -145,9 +155,15 @@ private void DumpOperand(Operand operand)
switch (memOp.Scale)
{
- case Multiplier.x2: _builder.Append("*2"); break;
- case Multiplier.x4: _builder.Append("*4"); break;
- case Multiplier.x8: _builder.Append("*8"); break;
+ case Multiplier.x2:
+ _builder.Append("*2");
+ break;
+ case Multiplier.x4:
+ _builder.Append("*4");
+ break;
+ case Multiplier.x8:
+ _builder.Append("*8");
+ break;
}
}
@@ -308,4 +324,4 @@ private static string GetTypeName(OperandType type)
};
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Diagnostics/Logger.cs b/src/ARMeilleure/Diagnostics/Logger.cs
index 07a60667e..d7f61230c 100644
--- a/src/ARMeilleure/Diagnostics/Logger.cs
+++ b/src/ARMeilleure/Diagnostics/Logger.cs
@@ -8,7 +8,7 @@ static class Logger
{
private static long _startTime;
- private static long[] _accumulatedTime;
+ private static readonly long[] _accumulatedTime;
static Logger()
{
@@ -53,4 +53,4 @@ private static void WriteOutput(string text)
Console.WriteLine(text);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Diagnostics/PassName.cs b/src/ARMeilleure/Diagnostics/PassName.cs
index e34bf0d2f..2d87659f0 100644
--- a/src/ARMeilleure/Diagnostics/PassName.cs
+++ b/src/ARMeilleure/Diagnostics/PassName.cs
@@ -14,6 +14,6 @@ enum PassName
RegisterAllocation,
CodeGeneration,
- Count
+ Count,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Diagnostics/Symbols.cs b/src/ARMeilleure/Diagnostics/Symbols.cs
index 6bde62f56..be74d2b5b 100644
--- a/src/ARMeilleure/Diagnostics/Symbols.cs
+++ b/src/ARMeilleure/Diagnostics/Symbols.cs
@@ -1,6 +1,7 @@
-using System.Collections.Concurrent;
+using System.Collections.Concurrent;
using System.Collections.Generic;
using System.Diagnostics;
+using System.Text;
namespace ARMeilleure.Diagnostics
{
@@ -33,9 +34,7 @@ static Symbols()
public static string Get(ulong address)
{
- string result;
-
- if (_symbols.TryGetValue(address, out result))
+ if (_symbols.TryGetValue(address, out string result))
{
return result;
}
@@ -49,13 +48,15 @@ public static string Get(ulong address)
ulong diff = address - symbol.Start;
ulong rem = diff % symbol.ElementSize;
- result = symbol.Name + "_" + diff / symbol.ElementSize;
+ StringBuilder resultBuilder = new();
+ resultBuilder.Append($"{symbol.Name}_{diff / symbol.ElementSize}");
if (rem != 0)
{
- result += "+" + rem;
+ resultBuilder.Append($"+{rem}");
}
+ result = resultBuilder.ToString();
_symbols.TryAdd(address, result);
return result;
diff --git a/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs b/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs
index a4f17844d..2e1be8c51 100644
--- a/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs
+++ b/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs
@@ -1,4 +1,4 @@
-using System.Diagnostics.Tracing;
+using System.Diagnostics.Tracing;
using System.Threading;
namespace ARMeilleure.Diagnostics
@@ -19,19 +19,19 @@ public TranslatorEventSource()
{
_rejitQueueCounter = new PollingCounter("rejit-queue-length", this, () => _rejitQueue)
{
- DisplayName = "Rejit Queue Length"
+ DisplayName = "Rejit Queue Length",
};
_funcTabSizeCounter = new PollingCounter("addr-tab-alloc", this, () => _funcTabSize / 1024d / 1024d)
{
DisplayName = "AddressTable Total Bytes Allocated",
- DisplayUnits = "MiB"
+ DisplayUnits = "MiB",
};
_funcTabLeafSizeCounter = new PollingCounter("addr-tab-leaf-alloc", this, () => _funcTabLeafSize / 1024d / 1024d)
{
DisplayName = "AddressTable Total Leaf Bytes Allocated",
- DisplayUnits = "MiB"
+ DisplayUnits = "MiB",
};
}
diff --git a/src/ARMeilleure/Instructions/CryptoHelper.cs b/src/ARMeilleure/Instructions/CryptoHelper.cs
index e517c75d2..ba68cebb3 100644
--- a/src/ARMeilleure/Instructions/CryptoHelper.cs
+++ b/src/ARMeilleure/Instructions/CryptoHelper.cs
@@ -7,7 +7,8 @@ namespace ARMeilleure.Instructions
{
static class CryptoHelper
{
-#region "LookUp Tables"
+ #region "LookUp Tables"
+#pragma warning disable IDE1006 // Naming rule violation
private static ReadOnlySpan _sBox => new byte[]
{
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
@@ -25,7 +26,7 @@ static class CryptoHelper
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
- 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+ 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16,
};
private static ReadOnlySpan _invSBox => new byte[]
@@ -45,7 +46,7 @@ static class CryptoHelper
0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
- 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+ 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d,
};
private static ReadOnlySpan _gfMul02 => new byte[]
@@ -65,7 +66,7 @@ static class CryptoHelper
0x9b, 0x99, 0x9f, 0x9d, 0x93, 0x91, 0x97, 0x95, 0x8b, 0x89, 0x8f, 0x8d, 0x83, 0x81, 0x87, 0x85,
0xbb, 0xb9, 0xbf, 0xbd, 0xb3, 0xb1, 0xb7, 0xb5, 0xab, 0xa9, 0xaf, 0xad, 0xa3, 0xa1, 0xa7, 0xa5,
0xdb, 0xd9, 0xdf, 0xdd, 0xd3, 0xd1, 0xd7, 0xd5, 0xcb, 0xc9, 0xcf, 0xcd, 0xc3, 0xc1, 0xc7, 0xc5,
- 0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5
+ 0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5,
};
private static ReadOnlySpan _gfMul03 => new byte[]
@@ -85,7 +86,7 @@ static class CryptoHelper
0x5b, 0x58, 0x5d, 0x5e, 0x57, 0x54, 0x51, 0x52, 0x43, 0x40, 0x45, 0x46, 0x4f, 0x4c, 0x49, 0x4a,
0x6b, 0x68, 0x6d, 0x6e, 0x67, 0x64, 0x61, 0x62, 0x73, 0x70, 0x75, 0x76, 0x7f, 0x7c, 0x79, 0x7a,
0x3b, 0x38, 0x3d, 0x3e, 0x37, 0x34, 0x31, 0x32, 0x23, 0x20, 0x25, 0x26, 0x2f, 0x2c, 0x29, 0x2a,
- 0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a
+ 0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a,
};
private static ReadOnlySpan _gfMul09 => new byte[]
@@ -105,7 +106,7 @@ static class CryptoHelper
0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5, 0xd2, 0xdb, 0xc0, 0xc9, 0xf6, 0xff, 0xe4, 0xed,
0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35, 0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d,
0xa1, 0xa8, 0xb3, 0xba, 0x85, 0x8c, 0x97, 0x9e, 0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6,
- 0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46
+ 0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46,
};
private static ReadOnlySpan _gfMul0B => new byte[]
@@ -125,7 +126,7 @@ static class CryptoHelper
0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30, 0x59, 0x52, 0x4f, 0x44, 0x75, 0x7e, 0x63, 0x68,
0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80, 0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8,
0x7a, 0x71, 0x6c, 0x67, 0x56, 0x5d, 0x40, 0x4b, 0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13,
- 0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3
+ 0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3,
};
private static ReadOnlySpan _gfMul0D => new byte[]
@@ -145,7 +146,7 @@ static class CryptoHelper
0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94, 0xdf, 0xd2, 0xc5, 0xc8, 0xeb, 0xe6, 0xf1, 0xfc,
0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44, 0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c,
0x0c, 0x01, 0x16, 0x1b, 0x38, 0x35, 0x22, 0x2f, 0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47,
- 0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97
+ 0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97,
};
private static ReadOnlySpan _gfMul0E => new byte[]
@@ -165,23 +166,24 @@ static class CryptoHelper
0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6, 0x9c, 0x92, 0x80, 0x8e, 0xa4, 0xaa, 0xb8, 0xb6,
0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26, 0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56,
0x37, 0x39, 0x2b, 0x25, 0x0f, 0x01, 0x13, 0x1d, 0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d,
- 0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d
+ 0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d,
};
private static ReadOnlySpan _srPerm => new byte[]
{
- 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3
+ 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3,
};
private static ReadOnlySpan _isrPerm => new byte[]
{
- 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11
+ 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11,
};
-#endregion
+#pragma warning restore IDE1006
+ #endregion
public static V128 AesInvMixColumns(V128 op)
{
- byte[] inState = op.ToArray();
+ byte[] inState = op.ToArray();
byte[] outState = new byte[16];
for (int columns = 0; columns <= 3; columns++)
@@ -204,7 +206,7 @@ public static V128 AesInvMixColumns(V128 op)
public static V128 AesInvShiftRows(V128 op)
{
- byte[] inState = op.ToArray();
+ byte[] inState = op.ToArray();
byte[] outState = new byte[16];
for (int idx = 0; idx <= 15; idx++)
@@ -217,7 +219,7 @@ public static V128 AesInvShiftRows(V128 op)
public static V128 AesInvSubBytes(V128 op)
{
- byte[] inState = op.ToArray();
+ byte[] inState = op.ToArray();
byte[] outState = new byte[16];
for (int idx = 0; idx <= 15; idx++)
@@ -230,7 +232,7 @@ public static V128 AesInvSubBytes(V128 op)
public static V128 AesMixColumns(V128 op)
{
- byte[] inState = op.ToArray();
+ byte[] inState = op.ToArray();
byte[] outState = new byte[16];
for (int columns = 0; columns <= 3; columns++)
@@ -253,7 +255,7 @@ public static V128 AesMixColumns(V128 op)
public static V128 AesShiftRows(V128 op)
{
- byte[] inState = op.ToArray();
+ byte[] inState = op.ToArray();
byte[] outState = new byte[16];
for (int idx = 0; idx <= 15; idx++)
@@ -266,7 +268,7 @@ public static V128 AesShiftRows(V128 op)
public static V128 AesSubBytes(V128 op)
{
- byte[] inState = op.ToArray();
+ byte[] inState = op.ToArray();
byte[] outState = new byte[16];
for (int idx = 0; idx <= 15; idx++)
diff --git a/src/ARMeilleure/Instructions/InstEmitAlu.cs b/src/ARMeilleure/Instructions/InstEmitAlu.cs
index e0d10e77d..ac17c32a7 100644
--- a/src/ARMeilleure/Instructions/InstEmitAlu.cs
+++ b/src/ARMeilleure/Instructions/InstEmitAlu.cs
@@ -3,7 +3,6 @@
using ARMeilleure.State;
using ARMeilleure.Translation;
using System.Diagnostics;
-
using static ARMeilleure.Instructions.InstEmitAluHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -12,7 +11,7 @@ namespace ARMeilleure.Instructions
{
static partial class InstEmit
{
- public static void Adc(ArmEmitterContext context) => EmitAdc(context, setFlags: false);
+ public static void Adc(ArmEmitterContext context) => EmitAdc(context, setFlags: false);
public static void Adcs(ArmEmitterContext context) => EmitAdc(context, setFlags: true);
private static void EmitAdc(ArmEmitterContext context, bool setFlags)
@@ -87,7 +86,7 @@ public static void Asrv(ArmEmitterContext context)
SetAluDOrZR(context, context.ShiftRightSI(GetAluN(context), GetAluMShift(context)));
}
- public static void Bic(ArmEmitterContext context) => EmitBic(context, setFlags: false);
+ public static void Bic(ArmEmitterContext context) => EmitBic(context, setFlags: false);
public static void Bics(ArmEmitterContext context) => EmitBic(context, setFlags: true);
private static void EmitBic(ArmEmitterContext context, bool setFlags)
@@ -190,7 +189,7 @@ public static void Lsrv(ArmEmitterContext context)
SetAluDOrZR(context, context.ShiftRightUI(GetAluN(context), GetAluMShift(context)));
}
- public static void Sbc(ArmEmitterContext context) => EmitSbc(context, setFlags: false);
+ public static void Sbc(ArmEmitterContext context) => EmitSbc(context, setFlags: false);
public static void Sbcs(ArmEmitterContext context) => EmitSbc(context, setFlags: true);
private static void EmitSbc(ArmEmitterContext context, bool setFlags)
@@ -281,16 +280,16 @@ private static Operand EmitReverseBits64Op(ArmEmitterContext context, Operand op
Debug.Assert(op.Type == OperandType.I64);
Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaaaaaaaaaaaaaaaul)), Const(1)),
- context.ShiftLeft (context.BitwiseAnd(op, Const(0x5555555555555555ul)), Const(1)));
+ context.ShiftLeft(context.BitwiseAnd(op, Const(0x5555555555555555ul)), Const(1)));
val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccccccccccccccccul)), Const(2)),
- context.ShiftLeft (context.BitwiseAnd(val, Const(0x3333333333333333ul)), Const(2)));
+ context.ShiftLeft(context.BitwiseAnd(val, Const(0x3333333333333333ul)), Const(2)));
val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xf0f0f0f0f0f0f0f0ul)), Const(4)),
- context.ShiftLeft (context.BitwiseAnd(val, Const(0x0f0f0f0f0f0f0f0ful)), Const(4)));
+ context.ShiftLeft(context.BitwiseAnd(val, Const(0x0f0f0f0f0f0f0f0ful)), Const(4)));
val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xff00ff00ff00ff00ul)), Const(8)),
- context.ShiftLeft (context.BitwiseAnd(val, Const(0x00ff00ff00ff00fful)), Const(8)));
+ context.ShiftLeft(context.BitwiseAnd(val, Const(0x00ff00ff00ff00fful)), Const(8)));
val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xffff0000ffff0000ul)), Const(16)),
- context.ShiftLeft (context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16)));
+ context.ShiftLeft(context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16)));
return context.BitwiseOr(context.ShiftRightUI(val, Const(32)), context.ShiftLeft(val, Const(32)));
}
@@ -340,7 +339,7 @@ private static Operand EmitReverseBytes32_64Op(ArmEmitterContext context, Operan
Operand val = EmitReverseBytes16_64Op(context, op);
return context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xffff0000ffff0000ul)), Const(16)),
- context.ShiftLeft (context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16)));
+ context.ShiftLeft(context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16)));
}
public static void Rev64(ArmEmitterContext context)
diff --git a/src/ARMeilleure/Instructions/InstEmitAlu32.cs b/src/ARMeilleure/Instructions/InstEmitAlu32.cs
index 584ada7e0..3a5e71bcc 100644
--- a/src/ARMeilleure/Instructions/InstEmitAlu32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitAlu32.cs
@@ -2,13 +2,14 @@
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
-
+using System.Diagnostics.CodeAnalysis;
using static ARMeilleure.Instructions.InstEmitAluHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
+ [SuppressMessage("Style", "IDE0059: Remove unnecessary value assignment")]
static partial class InstEmit32
{
public static void Add(ArmEmitterContext context)
diff --git a/src/ARMeilleure/Instructions/InstEmitAluHelper.cs b/src/ARMeilleure/Instructions/InstEmitAluHelper.cs
index 994878ad7..4d4a31f7b 100644
--- a/src/ARMeilleure/Instructions/InstEmitAluHelper.cs
+++ b/src/ARMeilleure/Instructions/InstEmitAluHelper.cs
@@ -26,7 +26,7 @@ public static bool ShouldSetFlags(ArmEmitterContext context)
public static void EmitNZFlagsCheck(ArmEmitterContext context, Operand d)
{
- SetFlag(context, PState.NFlag, context.ICompareLess (d, Const(d.Type, 0)));
+ SetFlag(context, PState.NFlag, context.ICompareLess(d, Const(d.Type, 0)));
SetFlag(context, PState.ZFlag, context.ICompareEqual(d, Const(d.Type, 0)));
}
@@ -196,60 +196,73 @@ public static Operand GetAluM(ArmEmitterContext context, bool setCarry = true)
{
// ARM32.
case IOpCode32AluImm op:
- {
- if (ShouldSetFlags(context) && op.IsRotated && setCarry)
{
- SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31));
+ if (ShouldSetFlags(context) && op.IsRotated && setCarry)
+ {
+ SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31));
+ }
+
+ return Const(op.Immediate);
}
+ case IOpCode32AluImm16 op:
return Const(op.Immediate);
- }
-
- case IOpCode32AluImm16 op: return Const(op.Immediate);
- case IOpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
- case IOpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry);
+ case IOpCode32AluRsImm op:
+ return GetMShiftedByImmediate(context, op, setCarry);
+ case IOpCode32AluRsReg op:
+ return GetMShiftedByReg(context, op, setCarry);
- case IOpCode32AluReg op: return GetIntA32(context, op.Rm);
+ case IOpCode32AluReg op:
+ return GetIntA32(context, op.Rm);
// ARM64.
case IOpCodeAluImm op:
- {
- if (op.GetOperandType() == OperandType.I32)
- {
- return Const((int)op.Immediate);
- }
- else
{
- return Const(op.Immediate);
+ if (op.GetOperandType() == OperandType.I32)
+ {
+ return Const((int)op.Immediate);
+ }
+ else
+ {
+ return Const(op.Immediate);
+ }
}
- }
case IOpCodeAluRs op:
- {
- Operand value = GetIntOrZR(context, op.Rm);
-
- switch (op.ShiftType)
{
- case ShiftType.Lsl: value = context.ShiftLeft (value, Const(op.Shift)); break;
- case ShiftType.Lsr: value = context.ShiftRightUI(value, Const(op.Shift)); break;
- case ShiftType.Asr: value = context.ShiftRightSI(value, Const(op.Shift)); break;
- case ShiftType.Ror: value = context.RotateRight (value, Const(op.Shift)); break;
- }
+ Operand value = GetIntOrZR(context, op.Rm);
- return value;
- }
+ switch (op.ShiftType)
+ {
+ case ShiftType.Lsl:
+ value = context.ShiftLeft(value, Const(op.Shift));
+ break;
+ case ShiftType.Lsr:
+ value = context.ShiftRightUI(value, Const(op.Shift));
+ break;
+ case ShiftType.Asr:
+ value = context.ShiftRightSI(value, Const(op.Shift));
+ break;
+ case ShiftType.Ror:
+ value = context.RotateRight(value, Const(op.Shift));
+ break;
+ }
+
+ return value;
+ }
case IOpCodeAluRx op:
- {
- Operand value = GetExtendedM(context, op.Rm, op.IntType);
+ {
+ Operand value = GetExtendedM(context, op.Rm, op.IntType);
- value = context.ShiftLeft(value, Const(op.Shift));
+ value = context.ShiftLeft(value, Const(op.Shift));
- return value;
- }
+ return value;
+ }
- default: throw InvalidOpCodeType(context.CurrOp);
+ default:
+ throw InvalidOpCodeType(context.CurrOp);
}
}
@@ -269,9 +282,15 @@ public static Operand GetMShiftedByImmediate(ArmEmitterContext context, IOpCode3
{
switch (op.ShiftType)
{
- case ShiftType.Lsr: shift = 32; break;
- case ShiftType.Asr: shift = 32; break;
- case ShiftType.Ror: shift = 1; break;
+ case ShiftType.Lsr:
+ shift = 32;
+ break;
+ case ShiftType.Asr:
+ shift = 32;
+ break;
+ case ShiftType.Ror:
+ shift = 1;
+ break;
}
}
@@ -281,9 +300,15 @@ public static Operand GetMShiftedByImmediate(ArmEmitterContext context, IOpCode3
switch (op.ShiftType)
{
- case ShiftType.Lsl: m = GetLslC(context, m, setCarry, shift); break;
- case ShiftType.Lsr: m = GetLsrC(context, m, setCarry, shift); break;
- case ShiftType.Asr: m = GetAsrC(context, m, setCarry, shift); break;
+ case ShiftType.Lsl:
+ m = GetLslC(context, m, setCarry, shift);
+ break;
+ case ShiftType.Lsr:
+ m = GetLsrC(context, m, setCarry, shift);
+ break;
+ case ShiftType.Asr:
+ m = GetAsrC(context, m, setCarry, shift);
+ break;
case ShiftType.Ror:
if (op.Immediate != 0)
{
@@ -306,9 +331,15 @@ public static int DecodeImmShift(ShiftType shiftType, int shift)
{
switch (shiftType)
{
- case ShiftType.Lsr: shift = 32; break;
- case ShiftType.Asr: shift = 32; break;
- case ShiftType.Ror: shift = 1; break;
+ case ShiftType.Lsr:
+ shift = 32;
+ break;
+ case ShiftType.Asr:
+ shift = 32;
+ break;
+ case ShiftType.Ror:
+ shift = 1;
+ break;
}
}
@@ -328,10 +359,18 @@ public static Operand GetMShiftedByReg(ArmEmitterContext context, IOpCode32AluRs
switch (op.ShiftType)
{
- case ShiftType.Lsl: shiftResult = EmitLslC(context, m, setCarry, s, shiftIsZero); break;
- case ShiftType.Lsr: shiftResult = EmitLsrC(context, m, setCarry, s, shiftIsZero); break;
- case ShiftType.Asr: shiftResult = EmitAsrC(context, m, setCarry, s, shiftIsZero); break;
- case ShiftType.Ror: shiftResult = EmitRorC(context, m, setCarry, s, shiftIsZero); break;
+ case ShiftType.Lsl:
+ shiftResult = EmitLslC(context, m, setCarry, s, shiftIsZero);
+ break;
+ case ShiftType.Lsr:
+ shiftResult = EmitLsrC(context, m, setCarry, s, shiftIsZero);
+ break;
+ case ShiftType.Asr:
+ shiftResult = EmitAsrC(context, m, setCarry, s, shiftIsZero);
+ break;
+ case ShiftType.Ror:
+ shiftResult = EmitRorC(context, m, setCarry, s, shiftIsZero);
+ break;
}
return context.ConditionalSelect(shiftIsZero, zeroResult, shiftResult);
diff --git a/src/ARMeilleure/Instructions/InstEmitBfm.cs b/src/ARMeilleure/Instructions/InstEmitBfm.cs
index 46a7ddddd..aaf228756 100644
--- a/src/ARMeilleure/Instructions/InstEmitBfm.cs
+++ b/src/ARMeilleure/Instructions/InstEmitBfm.cs
@@ -84,9 +84,9 @@ public static void Sbfm(ArmEmitterContext context)
{
Operand res = GetIntOrZR(context, op.Rn);
- res = context.ShiftLeft (res, Const(bitsCount - 1 - op.Pos));
+ res = context.ShiftLeft(res, Const(bitsCount - 1 - op.Pos));
res = context.ShiftRightSI(res, Const(bitsCount - 1));
- res = context.BitwiseAnd (res, Const(res.Type, ~op.TMask));
+ res = context.BitwiseAnd(res, Const(res.Type, ~op.TMask));
Operand n2 = GetBfmN(context);
@@ -193,4 +193,4 @@ private static Operand GetBfmN(ArmEmitterContext context)
return context.BitwiseAnd(context.RotateRight(res, Const(op.Shift)), Const(res.Type, mask));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitCcmp.cs b/src/ARMeilleure/Instructions/InstEmitCcmp.cs
index 7f0beb6cb..a71fc2689 100644
--- a/src/ARMeilleure/Instructions/InstEmitCcmp.cs
+++ b/src/ARMeilleure/Instructions/InstEmitCcmp.cs
@@ -2,7 +2,6 @@
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
-
using static ARMeilleure.Instructions.InstEmitAluHelper;
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
@@ -20,7 +19,7 @@ private static void EmitCcmp(ArmEmitterContext context, bool isNegated)
OpCodeCcmp op = (OpCodeCcmp)context.CurrOp;
Operand lblTrue = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
EmitCondBranch(context, lblTrue, op.Cond);
@@ -58,4 +57,4 @@ private static void EmitCcmp(ArmEmitterContext context, bool isNegated)
context.MarkLabel(lblEnd);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitCsel.cs b/src/ARMeilleure/Instructions/InstEmitCsel.cs
index 926b9a9ed..1cd936b31 100644
--- a/src/ARMeilleure/Instructions/InstEmitCsel.cs
+++ b/src/ARMeilleure/Instructions/InstEmitCsel.cs
@@ -1,7 +1,6 @@
using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
-
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -15,10 +14,10 @@ private enum CselOperation
None,
Increment,
Invert,
- Negate
+ Negate,
}
- public static void Csel(ArmEmitterContext context) => EmitCsel(context, CselOperation.None);
+ public static void Csel(ArmEmitterContext context) => EmitCsel(context, CselOperation.None);
public static void Csinc(ArmEmitterContext context) => EmitCsel(context, CselOperation.Increment);
public static void Csinv(ArmEmitterContext context) => EmitCsel(context, CselOperation.Invert);
public static void Csneg(ArmEmitterContext context) => EmitCsel(context, CselOperation.Negate);
@@ -50,4 +49,4 @@ private static void EmitCsel(ArmEmitterContext context, CselOperation cselOp)
SetIntOrZR(context, op.Rd, d);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitDiv.cs b/src/ARMeilleure/Instructions/InstEmitDiv.cs
index 39a5c32e6..728462ed4 100644
--- a/src/ARMeilleure/Instructions/InstEmitDiv.cs
+++ b/src/ARMeilleure/Instructions/InstEmitDiv.cs
@@ -1,7 +1,6 @@
using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -23,7 +22,7 @@ private static void EmitDiv(ArmEmitterContext context, bool unsigned)
Operand divisorIsZero = context.ICompareEqual(m, Const(m.Type, 0));
Operand lblBadDiv = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
context.BranchIfTrue(lblBadDiv, divisorIsZero);
@@ -33,7 +32,7 @@ private static void EmitDiv(ArmEmitterContext context, bool unsigned)
bool is32Bits = op.RegisterSize == RegisterSize.Int32;
Operand intMin = is32Bits ? Const(int.MinValue) : Const(long.MinValue);
- Operand minus1 = is32Bits ? Const(-1) : Const(-1L);
+ Operand minus1 = is32Bits ? Const(-1) : Const(-1L);
Operand nIsIntMin = context.ICompareEqual(n, intMin);
Operand mIsMinus1 = context.ICompareEqual(m, minus1);
@@ -51,7 +50,7 @@ private static void EmitDiv(ArmEmitterContext context, bool unsigned)
Operand d = unsigned
? context.DivideUI(n, m)
- : context.Divide (n, m);
+ : context.Divide(n, m);
SetAluDOrZR(context, d);
diff --git a/src/ARMeilleure/Instructions/InstEmitException.cs b/src/ARMeilleure/Instructions/InstEmitException.cs
index 0baaa87d7..d30fb2fbd 100644
--- a/src/ARMeilleure/Instructions/InstEmitException.cs
+++ b/src/ARMeilleure/Instructions/InstEmitException.cs
@@ -52,4 +52,4 @@ public static void Und(ArmEmitterContext context)
context.Return(Const(op.Address));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitException32.cs b/src/ARMeilleure/Instructions/InstEmitException32.cs
index ec0c32bf9..57af1522b 100644
--- a/src/ARMeilleure/Instructions/InstEmitException32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitException32.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.Translation;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
diff --git a/src/ARMeilleure/Instructions/InstEmitFlow.cs b/src/ARMeilleure/Instructions/InstEmitFlow.cs
index c40eb55cf..a986bf66f 100644
--- a/src/ARMeilleure/Instructions/InstEmitFlow.cs
+++ b/src/ARMeilleure/Instructions/InstEmitFlow.cs
@@ -53,7 +53,7 @@ public static void Br(ArmEmitterContext context)
}
public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true);
- public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
+ public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
private static void EmitCb(ArmEmitterContext context, bool onNotZero)
{
@@ -70,7 +70,7 @@ public static void Ret(ArmEmitterContext context)
}
public static void Tbnz(ArmEmitterContext context) => EmitTb(context, onNotZero: true);
- public static void Tbz(ArmEmitterContext context) => EmitTb(context, onNotZero: false);
+ public static void Tbz(ArmEmitterContext context) => EmitTb(context, onNotZero: false);
private static void EmitTb(ArmEmitterContext context, bool onNotZero)
{
@@ -104,4 +104,4 @@ private static void EmitBranch(ArmEmitterContext context, Operand value, bool on
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitFlow32.cs b/src/ARMeilleure/Instructions/InstEmitFlow32.cs
index 3a7707ee9..289d3f483 100644
--- a/src/ARMeilleure/Instructions/InstEmitFlow32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitFlow32.cs
@@ -82,7 +82,7 @@ public static void Bx(ArmEmitterContext context)
}
public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true);
- public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
+ public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
private static void EmitCb(ArmEmitterContext context, bool onNotZero)
{
@@ -109,7 +109,7 @@ public static void It(ArmEmitterContext context)
}
public static void Tbb(ArmEmitterContext context) => EmitTb(context, halfword: false);
- public static void Tbh(ArmEmitterContext context) => EmitTb(context, halfword: true);
+ public static void Tbh(ArmEmitterContext context) => EmitTb(context, halfword: true);
private static void EmitTb(ArmEmitterContext context, bool halfword)
{
@@ -133,4 +133,4 @@ private static void EmitTb(ArmEmitterContext context, bool halfword)
EmitVirtualJump(context, targetAddress, isReturn: false);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs b/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs
index 6ac329085..2009bafda 100644
--- a/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs
+++ b/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs
@@ -75,66 +75,66 @@ Operand Inverse(Operand val)
break;
case Condition.GtUn:
- {
- Operand c = GetFlag(PState.CFlag);
- Operand z = GetFlag(PState.ZFlag);
+ {
+ Operand c = GetFlag(PState.CFlag);
+ Operand z = GetFlag(PState.ZFlag);
- value = context.BitwiseAnd(c, Inverse(z));
+ value = context.BitwiseAnd(c, Inverse(z));
- break;
- }
+ break;
+ }
case Condition.LeUn:
- {
- Operand c = GetFlag(PState.CFlag);
- Operand z = GetFlag(PState.ZFlag);
+ {
+ Operand c = GetFlag(PState.CFlag);
+ Operand z = GetFlag(PState.ZFlag);
- value = context.BitwiseOr(Inverse(c), z);
+ value = context.BitwiseOr(Inverse(c), z);
- break;
- }
+ break;
+ }
case Condition.Ge:
- {
- Operand n = GetFlag(PState.NFlag);
- Operand v = GetFlag(PState.VFlag);
+ {
+ Operand n = GetFlag(PState.NFlag);
+ Operand v = GetFlag(PState.VFlag);
- value = context.ICompareEqual(n, v);
+ value = context.ICompareEqual(n, v);
- break;
- }
+ break;
+ }
case Condition.Lt:
- {
- Operand n = GetFlag(PState.NFlag);
- Operand v = GetFlag(PState.VFlag);
+ {
+ Operand n = GetFlag(PState.NFlag);
+ Operand v = GetFlag(PState.VFlag);
- value = context.ICompareNotEqual(n, v);
+ value = context.ICompareNotEqual(n, v);
- break;
- }
+ break;
+ }
case Condition.Gt:
- {
- Operand n = GetFlag(PState.NFlag);
- Operand z = GetFlag(PState.ZFlag);
- Operand v = GetFlag(PState.VFlag);
+ {
+ Operand n = GetFlag(PState.NFlag);
+ Operand z = GetFlag(PState.ZFlag);
+ Operand v = GetFlag(PState.VFlag);
- value = context.BitwiseAnd(Inverse(z), context.ICompareEqual(n, v));
+ value = context.BitwiseAnd(Inverse(z), context.ICompareEqual(n, v));
- break;
- }
+ break;
+ }
case Condition.Le:
- {
- Operand n = GetFlag(PState.NFlag);
- Operand z = GetFlag(PState.ZFlag);
- Operand v = GetFlag(PState.VFlag);
+ {
+ Operand n = GetFlag(PState.NFlag);
+ Operand z = GetFlag(PState.ZFlag);
+ Operand v = GetFlag(PState.VFlag);
- value = context.BitwiseOr(z, context.ICompareNotEqual(n, v));
+ value = context.BitwiseOr(z, context.ICompareNotEqual(n, v));
- break;
- }
+ break;
+ }
}
return value;
diff --git a/src/ARMeilleure/Instructions/InstEmitHash32.cs b/src/ARMeilleure/Instructions/InstEmitHash32.cs
index 5d39f8afc..30c893a78 100644
--- a/src/ARMeilleure/Instructions/InstEmitHash32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitHash32.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHashHelper;
diff --git a/src/ARMeilleure/Instructions/InstEmitHashHelper.cs b/src/ARMeilleure/Instructions/InstEmitHashHelper.cs
index 55a03a4f6..9b1ad8721 100644
--- a/src/ARMeilleure/Instructions/InstEmitHashHelper.cs
+++ b/src/ARMeilleure/Instructions/InstEmitHashHelper.cs
@@ -1,4 +1,4 @@
-// https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
+// https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
@@ -45,7 +45,7 @@ public static Operand EmitCrc32(ArmEmitterContext context, Operand crc, Operand
}
else
{
- string name = (size, castagnoli) switch
+ string name = (size, castagnoli) switch
{
(0, false) => nameof(SoftFallback.Crc32b),
(1, false) => nameof(SoftFallback.Crc32h),
@@ -55,7 +55,7 @@ public static Operand EmitCrc32(ArmEmitterContext context, Operand crc, Operand
(1, true) => nameof(SoftFallback.Crc32ch),
(2, true) => nameof(SoftFallback.Crc32cw),
(3, true) => nameof(SoftFallback.Crc32cx),
- _ => throw new ArgumentOutOfRangeException(nameof(size))
+ _ => throw new ArgumentOutOfRangeException(nameof(size)),
};
return context.Call(typeof(SoftFallback).GetMethod(name), crc, value);
@@ -71,9 +71,15 @@ private static Operand EmitCrc32Optimized(ArmEmitterContext context, Operand crc
switch (size)
{
- case 0: data = context.VectorInsert8(context.VectorZero(), data, 0); break;
- case 1: data = context.VectorInsert16(context.VectorZero(), data, 0); break;
- case 2: data = context.VectorInsert(context.VectorZero(), data, 0); break;
+ case 0:
+ data = context.VectorInsert8(context.VectorZero(), data, 0);
+ break;
+ case 1:
+ data = context.VectorInsert16(context.VectorZero(), data, 0);
+ break;
+ case 2:
+ data = context.VectorInsert(context.VectorZero(), data, 0);
+ break;
}
int bitsize = 8 << size;
diff --git a/src/ARMeilleure/Instructions/InstEmitHelper.cs b/src/ARMeilleure/Instructions/InstEmitHelper.cs
index a22bb3fb7..7a515f94f 100644
--- a/src/ARMeilleure/Instructions/InstEmitHelper.cs
+++ b/src/ARMeilleure/Instructions/InstEmitHelper.cs
@@ -16,13 +16,25 @@ public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType ty
switch (type)
{
- case IntType.UInt8: value = context.ZeroExtend8 (value.Type, value); break;
- case IntType.UInt16: value = context.ZeroExtend16(value.Type, value); break;
- case IntType.UInt32: value = context.ZeroExtend32(value.Type, value); break;
-
- case IntType.Int8: value = context.SignExtend8 (value.Type, value); break;
- case IntType.Int16: value = context.SignExtend16(value.Type, value); break;
- case IntType.Int32: value = context.SignExtend32(value.Type, value); break;
+ case IntType.UInt8:
+ value = context.ZeroExtend8(value.Type, value);
+ break;
+ case IntType.UInt16:
+ value = context.ZeroExtend16(value.Type, value);
+ break;
+ case IntType.UInt32:
+ value = context.ZeroExtend32(value.Type, value);
+ break;
+
+ case IntType.Int8:
+ value = context.SignExtend8(value.Type, value);
+ break;
+ case IntType.Int16:
+ value = context.SignExtend16(value.Type, value);
+ break;
+ case IntType.Int32:
+ value = context.SignExtend32(value.Type, value);
+ break;
}
return value;
@@ -100,78 +112,51 @@ public static int GetRegisterAlias(Aarch32Mode mode, int regIndex)
public static int GetBankedRegisterAlias(Aarch32Mode mode, int regIndex)
{
- switch (regIndex)
+ return regIndex switch
{
- case 8: return mode == Aarch32Mode.Fiq
- ? RegisterAlias.R8Fiq
- : RegisterAlias.R8Usr;
-
- case 9: return mode == Aarch32Mode.Fiq
- ? RegisterAlias.R9Fiq
- : RegisterAlias.R9Usr;
-
- case 10: return mode == Aarch32Mode.Fiq
- ? RegisterAlias.R10Fiq
- : RegisterAlias.R10Usr;
-
- case 11: return mode == Aarch32Mode.Fiq
- ? RegisterAlias.R11Fiq
- : RegisterAlias.R11Usr;
-
- case 12: return mode == Aarch32Mode.Fiq
- ? RegisterAlias.R12Fiq
- : RegisterAlias.R12Usr;
-
- case 13:
- switch (mode)
- {
- case Aarch32Mode.User:
- case Aarch32Mode.System: return RegisterAlias.SpUsr;
- case Aarch32Mode.Fiq: return RegisterAlias.SpFiq;
- case Aarch32Mode.Irq: return RegisterAlias.SpIrq;
- case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc;
- case Aarch32Mode.Abort: return RegisterAlias.SpAbt;
- case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp;
- case Aarch32Mode.Undefined: return RegisterAlias.SpUnd;
-
- default: throw new ArgumentException(nameof(mode));
- }
-
- case 14:
- switch (mode)
- {
- case Aarch32Mode.User:
- case Aarch32Mode.Hypervisor:
- case Aarch32Mode.System: return RegisterAlias.LrUsr;
- case Aarch32Mode.Fiq: return RegisterAlias.LrFiq;
- case Aarch32Mode.Irq: return RegisterAlias.LrIrq;
- case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc;
- case Aarch32Mode.Abort: return RegisterAlias.LrAbt;
- case Aarch32Mode.Undefined: return RegisterAlias.LrUnd;
-
- default: throw new ArgumentException(nameof(mode));
- }
-
- default: throw new ArgumentOutOfRangeException(nameof(regIndex));
- }
+#pragma warning disable IDE0055 // Disable formatting
+ 8 => mode == Aarch32Mode.Fiq ? RegisterAlias.R8Fiq : RegisterAlias.R8Usr,
+ 9 => mode == Aarch32Mode.Fiq ? RegisterAlias.R9Fiq : RegisterAlias.R9Usr,
+ 10 => mode == Aarch32Mode.Fiq ? RegisterAlias.R10Fiq : RegisterAlias.R10Usr,
+ 11 => mode == Aarch32Mode.Fiq ? RegisterAlias.R11Fiq : RegisterAlias.R11Usr,
+ 12 => mode == Aarch32Mode.Fiq ? RegisterAlias.R12Fiq : RegisterAlias.R12Usr,
+ 13 => mode switch
+ {
+ Aarch32Mode.User or Aarch32Mode.System => RegisterAlias.SpUsr,
+ Aarch32Mode.Fiq => RegisterAlias.SpFiq,
+ Aarch32Mode.Irq => RegisterAlias.SpIrq,
+ Aarch32Mode.Supervisor => RegisterAlias.SpSvc,
+ Aarch32Mode.Abort => RegisterAlias.SpAbt,
+ Aarch32Mode.Hypervisor => RegisterAlias.SpHyp,
+ Aarch32Mode.Undefined => RegisterAlias.SpUnd,
+ _ => throw new ArgumentException($"No such AArch32Mode: {mode}", nameof(mode)),
+ },
+ 14 => mode switch
+ {
+ Aarch32Mode.User or Aarch32Mode.Hypervisor or Aarch32Mode.System => RegisterAlias.LrUsr,
+ Aarch32Mode.Fiq => RegisterAlias.LrFiq,
+ Aarch32Mode.Irq => RegisterAlias.LrIrq,
+ Aarch32Mode.Supervisor => RegisterAlias.LrSvc,
+ Aarch32Mode.Abort => RegisterAlias.LrAbt,
+ Aarch32Mode.Undefined => RegisterAlias.LrUnd,
+ _ => throw new ArgumentException($"No such AArch32Mode: {mode}", nameof(mode)),
+ },
+ _ => throw new ArgumentOutOfRangeException(nameof(regIndex), regIndex, null),
+#pragma warning restore IDE0055
+ };
}
public static bool IsA32Return(ArmEmitterContext context)
{
- switch (context.CurrOp)
+ return context.CurrOp switch
{
- case IOpCode32MemMult op:
- return true; // Setting PC using LDM is nearly always a return.
- case OpCode32AluRsImm op:
- return op.Rm == RegisterAlias.Aarch32Lr;
- case OpCode32AluRsReg op:
- return op.Rm == RegisterAlias.Aarch32Lr;
- case OpCode32AluReg op:
- return op.Rm == RegisterAlias.Aarch32Lr;
- case OpCode32Mem op:
- return op.Rn == RegisterAlias.Aarch32Sp && op.WBack && !op.Index; // Setting PC to an address stored on the stack is nearly always a return.
- }
- return false;
+ IOpCode32MemMult => true, // Setting PC using LDM is nearly always a return.
+ OpCode32AluRsImm op => op.Rm == RegisterAlias.Aarch32Lr,
+ OpCode32AluRsReg op => op.Rm == RegisterAlias.Aarch32Lr,
+ OpCode32AluReg op => op.Rm == RegisterAlias.Aarch32Lr,
+ OpCode32Mem op => op.Rn == RegisterAlias.Aarch32Sp && op.WBack && !op.Index, // Setting PC to an address stored on the stack is nearly always a return.
+ _ => false,
+ };
}
public static void EmitBxWritePc(ArmEmitterContext context, Operand pc, int sourceRegister = 0)
diff --git a/src/ARMeilleure/Instructions/InstEmitMemory.cs b/src/ARMeilleure/Instructions/InstEmitMemory.cs
index 7baed14c8..840099f9c 100644
--- a/src/ARMeilleure/Instructions/InstEmitMemory.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMemory.cs
@@ -26,7 +26,7 @@ public static void Adrp(ArmEmitterContext context)
SetIntOrZR(context, op.Rd, Const(address));
}
- public static void Ldr(ArmEmitterContext context) => EmitLdr(context, signed: false);
+ public static void Ldr(ArmEmitterContext context) => EmitLdr(context, signed: false);
public static void Ldrs(ArmEmitterContext context) => EmitLdr(context, signed: true);
private static void EmitLdr(ArmEmitterContext context, bool signed)
@@ -89,7 +89,7 @@ void EmitLoad(int rt, Operand ldAddr)
Operand address = GetAddress(context);
Operand address2 = GetAddress(context, 1L << op.Size);
- EmitLoad(op.Rt, address);
+ EmitLoad(op.Rt, address);
EmitLoad(op.Rt2, address2);
EmitWBackIfNeeded(context, address);
@@ -113,7 +113,7 @@ public static void Stp(ArmEmitterContext context)
Operand address = GetAddress(context);
Operand address2 = GetAddress(context, 1L << op.Size);
- EmitStore(context, address, op.Rt, op.Size);
+ EmitStore(context, address, op.Rt, op.Size);
EmitStore(context, address2, op.Rt2, op.Size);
EmitWBackIfNeeded(context, address);
@@ -126,42 +126,42 @@ private static Operand GetAddress(ArmEmitterContext context, long addend = 0)
switch (context.CurrOp)
{
case OpCodeMemImm op:
- {
- address = context.Copy(GetIntOrSP(context, op.Rn));
-
- // Pre-indexing.
- if (!op.PostIdx)
- {
- address = context.Add(address, Const(op.Immediate + addend));
- }
- else if (addend != 0)
{
- address = context.Add(address, Const(addend));
+ address = context.Copy(GetIntOrSP(context, op.Rn));
+
+ // Pre-indexing.
+ if (!op.PostIdx)
+ {
+ address = context.Add(address, Const(op.Immediate + addend));
+ }
+ else if (addend != 0)
+ {
+ address = context.Add(address, Const(addend));
+ }
+
+ break;
}
- break;
- }
-
case OpCodeMemReg op:
- {
- Operand n = GetIntOrSP(context, op.Rn);
+ {
+ Operand n = GetIntOrSP(context, op.Rn);
- Operand m = GetExtendedM(context, op.Rm, op.IntType);
+ Operand m = GetExtendedM(context, op.Rm, op.IntType);
- if (op.Shift)
- {
- m = context.ShiftLeft(m, Const(op.Size));
- }
+ if (op.Shift)
+ {
+ m = context.ShiftLeft(m, Const(op.Size));
+ }
- address = context.Add(n, m);
+ address = context.Add(n, m);
- if (addend != 0)
- {
- address = context.Add(address, Const(addend));
- }
+ if (addend != 0)
+ {
+ address = context.Add(address, Const(addend));
+ }
- break;
- }
+ break;
+ }
}
return address;
@@ -181,4 +181,4 @@ private static void EmitWBackIfNeeded(ArmEmitterContext context, Operand address
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitMemory32.cs b/src/ARMeilleure/Instructions/InstEmitMemory32.cs
index 17ec97aa6..cee06700d 100644
--- a/src/ARMeilleure/Instructions/InstEmitMemory32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMemory32.cs
@@ -3,7 +3,6 @@
using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitMemoryHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -12,18 +11,18 @@ namespace ARMeilleure.Instructions
{
static partial class InstEmit32
{
- private const int ByteSizeLog2 = 0;
+ private const int ByteSizeLog2 = 0;
private const int HWordSizeLog2 = 1;
- private const int WordSizeLog2 = 2;
+ private const int WordSizeLog2 = 2;
private const int DWordSizeLog2 = 3;
[Flags]
enum AccessType
{
- Store = 0,
- Signed = 1,
- Load = 2,
- Ordered = 4,
+ Store = 0,
+ Signed = 1,
+ Load = 2,
+ Ordered = 4,
Exclusive = 8,
LoadZx = Load,
@@ -47,7 +46,7 @@ public static void Ldm(ArmEmitterContext context)
SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset)));
}
- int mask = op.RegisterMask;
+ int mask = op.RegisterMask;
int offset = 0;
for (int register = 0; mask != 0; mask >>= 1, register++)
@@ -101,7 +100,7 @@ public static void Stm(ArmEmitterContext context)
Operand baseAddress = context.Add(n, Const(op.Offset));
- int mask = op.RegisterMask;
+ int mask = op.RegisterMask;
int offset = 0;
for (int register = 0; mask != 0; mask >>= 1, register++)
@@ -161,7 +160,7 @@ private static void EmitLoadOrStore(ArmEmitterContext context, int size, AccessT
if (op.Index || op.WBack)
{
temp = op.Add
- ? context.Add (n, m)
+ ? context.Add(n, m)
: context.Subtract(n, m);
}
@@ -200,7 +199,7 @@ void Load(int rt, int offs, int loadSize)
if (size == DWordSizeLog2)
{
Operand lblBigEndian = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
@@ -233,7 +232,7 @@ void Store(int rt, int offs, int storeSize)
if (size == DWordSizeLog2)
{
Operand lblBigEndian = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
@@ -262,4 +261,4 @@ public static void Adr(ArmEmitterContext context)
SetIntA32(context, op.Rd, Const(op.Immediate));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs b/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs
index c7ed01e34..8c95b33c5 100644
--- a/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs
@@ -3,7 +3,6 @@
using ARMeilleure.Translation;
using System;
using System.Diagnostics;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitMemoryExHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -15,10 +14,10 @@ static partial class InstEmit
[Flags]
private enum AccessType
{
- None = 0,
- Ordered = 1,
+ None = 0,
+ Ordered = 1,
Exclusive = 2,
- OrderedEx = Ordered | Exclusive
+ OrderedEx = Ordered | Exclusive,
}
public static void Clrex(ArmEmitterContext context)
@@ -34,10 +33,10 @@ public static void Csdb(ArmEmitterContext context)
public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);
- public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered);
+ public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered);
public static void Ldaxr(ArmEmitterContext context) => EmitLdr(context, AccessType.OrderedEx);
- public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive);
- public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive);
+ public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive);
+ public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive);
public static void Ldaxp(ArmEmitterContext context) => EmitLdp(context, AccessType.OrderedEx);
private static void EmitLdr(ArmEmitterContext context, AccessType accType)
@@ -54,7 +53,7 @@ private static void EmitLoadEx(ArmEmitterContext context, AccessType accType, bo
{
OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
- bool ordered = (accType & AccessType.Ordered) != 0;
+ bool ordered = (accType & AccessType.Ordered) != 0;
bool exclusive = (accType & AccessType.Exclusive) != 0;
if (ordered)
@@ -80,17 +79,17 @@ private static void EmitLoadEx(ArmEmitterContext context, AccessType accType, bo
Operand valueHigh = context.ShiftRightUI(value, Const(32));
- SetIntOrZR(context, op.Rt, valueLow);
+ SetIntOrZR(context, op.Rt, valueLow);
SetIntOrZR(context, op.Rt2, valueHigh);
}
else if (op.Size == 3)
{
Operand value = EmitLoadExclusive(context, address, exclusive, 4);
- Operand valueLow = context.VectorExtract(OperandType.I64, value, 0);
+ Operand valueLow = context.VectorExtract(OperandType.I64, value, 0);
Operand valueHigh = context.VectorExtract(OperandType.I64, value, 1);
- SetIntOrZR(context, op.Rt, valueLow);
+ SetIntOrZR(context, op.Rt, valueLow);
SetIntOrZR(context, op.Rt2, valueHigh);
}
else
@@ -112,10 +111,10 @@ public static void Prfm(ArmEmitterContext context)
// Memory Prefetch, execute as no-op.
}
- public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered);
+ public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered);
public static void Stlxr(ArmEmitterContext context) => EmitStr(context, AccessType.OrderedEx);
- public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive);
- public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive);
+ public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive);
+ public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive);
public static void Stlxp(ArmEmitterContext context) => EmitStp(context, AccessType.OrderedEx);
private static void EmitStr(ArmEmitterContext context, AccessType accType)
@@ -132,7 +131,7 @@ private static void EmitStoreEx(ArmEmitterContext context, AccessType accType, b
{
OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
- bool ordered = (accType & AccessType.Ordered) != 0;
+ bool ordered = (accType & AccessType.Ordered) != 0;
bool exclusive = (accType & AccessType.Exclusive) != 0;
Operand address = context.Copy(GetIntOrSP(context, op.Rn));
@@ -153,8 +152,8 @@ private static void EmitStoreEx(ArmEmitterContext context, AccessType accType, b
}
else /* if (op.Size == 3) */
{
- value = context.VectorInsert(context.VectorZero(), t, 0);
- value = context.VectorInsert(value, t2, 1);
+ value = context.VectorInsert(context.VectorZero(), t, 0);
+ value = context.VectorInsert(value, t2, 1);
}
EmitStoreExclusive(context, address, value, exclusive, op.Size + 1, op.Rs, a32: false);
@@ -175,4 +174,4 @@ private static void EmitBarrier(ArmEmitterContext context)
context.MemoryBarrier();
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryEx32.cs b/src/ARMeilleure/Instructions/InstEmitMemoryEx32.cs
index c0b6fc39d..150218827 100644
--- a/src/ARMeilleure/Instructions/InstEmitMemoryEx32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMemoryEx32.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs b/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs
index 9a69442a6..7fca5b853 100644
--- a/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs
@@ -1,7 +1,6 @@
-using ARMeilleure.IntermediateRepresentation;
+using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -33,7 +32,7 @@ public static Operand EmitLoadExclusive(ArmEmitterContext context, Operand addre
Operand arg0 = context.LoadArgument(OperandType.I64, 0);
- Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
+ Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset()));
context.Store(exAddrPtr, context.BitwiseAnd(address, Const(address.Type, GetExclusiveAddressMask())));
@@ -118,14 +117,14 @@ void SetRs(Operand value)
1 => context.Load16(exValuePtr),
2 => context.Load(OperandType.I32, exValuePtr),
3 => context.Load(OperandType.I64, exValuePtr),
- _ => context.Load(OperandType.V128, exValuePtr)
+ _ => context.Load(OperandType.V128, exValuePtr),
};
Operand currValue = size switch
{
0 => context.CompareAndSwap8(physAddr, exValue, value),
1 => context.CompareAndSwap16(physAddr, exValue, value),
- _ => context.CompareAndSwap(physAddr, exValue, value)
+ _ => context.CompareAndSwap(physAddr, exValue, value),
};
// STEP 3: Check if we succeeded by comparing expected and in-memory values.
@@ -133,14 +132,14 @@ void SetRs(Operand value)
if (size == 4)
{
- Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0);
+ Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0);
Operand currValueHigh = context.VectorExtract(OperandType.I64, currValue, 1);
- Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0);
+ Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0);
Operand exValueHigh = context.VectorExtract(OperandType.I64, exValue, 1);
storeFailed = context.BitwiseOr(
- context.ICompareNotEqual(currValueLow, exValueLow),
+ context.ICompareNotEqual(currValueLow, exValueLow),
context.ICompareNotEqual(currValueHigh, exValueHigh));
}
else
diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs b/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs
index f97e395ce..a807eed51 100644
--- a/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs
@@ -5,7 +5,6 @@
using ARMeilleure.Translation.PTC;
using System;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -20,7 +19,7 @@ private enum Extension
{
Zx,
Sx32,
- Sx64
+ Sx64,
}
public static void EmitLoadZx(ArmEmitterContext context, Operand address, int rt, int size)
@@ -66,9 +65,15 @@ private static void EmitLoad(ArmEmitterContext context, Operand address, Extensi
switch (size)
{
- case 0: value = context.SignExtend8 (destType, value); break;
- case 1: value = context.SignExtend16(destType, value); break;
- case 2: value = context.SignExtend32(destType, value); break;
+ case 0:
+ value = context.SignExtend8(destType, value);
+ break;
+ case 1:
+ value = context.SignExtend16(destType, value);
+ break;
+ case 2:
+ value = context.SignExtend32(destType, value);
+ break;
}
}
@@ -128,7 +133,7 @@ public static Operand EmitReadInt(ArmEmitterContext context, Operand address, in
Operand temp = context.AllocateLocal(size == 3 ? OperandType.I64 : OperandType.I32);
Operand lblSlowPath = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
@@ -136,10 +141,18 @@ public static Operand EmitReadInt(ArmEmitterContext context, Operand address, in
switch (size)
{
- case 0: value = context.Load8 (physAddr); break;
- case 1: value = context.Load16(physAddr); break;
- case 2: value = context.Load (OperandType.I32, physAddr); break;
- case 3: value = context.Load (OperandType.I64, physAddr); break;
+ case 0:
+ value = context.Load8(physAddr);
+ break;
+ case 1:
+ value = context.Load16(physAddr);
+ break;
+ case 2:
+ value = context.Load(OperandType.I32, physAddr);
+ break;
+ case 3:
+ value = context.Load(OperandType.I64, physAddr);
+ break;
}
context.Copy(temp, value);
@@ -161,7 +174,7 @@ public static Operand EmitReadInt(ArmEmitterContext context, Operand address, in
private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size)
{
Operand lblSlowPath = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
@@ -169,10 +182,18 @@ private static void EmitReadInt(ArmEmitterContext context, Operand address, int
switch (size)
{
- case 0: value = context.Load8 (physAddr); break;
- case 1: value = context.Load16(physAddr); break;
- case 2: value = context.Load (OperandType.I32, physAddr); break;
- case 3: value = context.Load (OperandType.I64, physAddr); break;
+ case 0:
+ value = context.Load8(physAddr);
+ break;
+ case 1:
+ value = context.Load16(physAddr);
+ break;
+ case 2:
+ value = context.Load(OperandType.I32, physAddr);
+ break;
+ case 3:
+ value = context.Load(OperandType.I64, physAddr);
+ break;
}
SetInt(context, rt, value);
@@ -204,7 +225,7 @@ public static Operand EmitReadIntAligned(ArmEmitterContext context, Operand addr
1 => context.Load16(physAddr),
2 => context.Load(OperandType.I32, physAddr),
3 => context.Load(OperandType.I64, physAddr),
- _ => context.Load(OperandType.V128, physAddr)
+ _ => context.Load(OperandType.V128, physAddr),
};
}
@@ -217,7 +238,7 @@ private static void EmitReadVector(
int size)
{
Operand lblSlowPath = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
@@ -225,11 +246,21 @@ private static void EmitReadVector(
switch (size)
{
- case 0: value = context.VectorInsert8 (vector, context.Load8(physAddr), elem); break;
- case 1: value = context.VectorInsert16(vector, context.Load16(physAddr), elem); break;
- case 2: value = context.VectorInsert (vector, context.Load(OperandType.I32, physAddr), elem); break;
- case 3: value = context.VectorInsert (vector, context.Load(OperandType.I64, physAddr), elem); break;
- case 4: value = context.Load (OperandType.V128, physAddr); break;
+ case 0:
+ value = context.VectorInsert8(vector, context.Load8(physAddr), elem);
+ break;
+ case 1:
+ value = context.VectorInsert16(vector, context.Load16(physAddr), elem);
+ break;
+ case 2:
+ value = context.VectorInsert(vector, context.Load(OperandType.I32, physAddr), elem);
+ break;
+ case 3:
+ value = context.VectorInsert(vector, context.Load(OperandType.I64, physAddr), elem);
+ break;
+ case 4:
+ value = context.Load(OperandType.V128, physAddr);
+ break;
}
context.Copy(GetVec(rt), value);
@@ -254,7 +285,7 @@ private static Operand VectorCreate(ArmEmitterContext context, Operand value)
private static void EmitWriteInt(ArmEmitterContext context, Operand address, int rt, int size)
{
Operand lblSlowPath = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true, size);
@@ -267,10 +298,18 @@ private static void EmitWriteInt(ArmEmitterContext context, Operand address, int
switch (size)
{
- case 0: context.Store8 (physAddr, value); break;
- case 1: context.Store16(physAddr, value); break;
- case 2: context.Store (physAddr, value); break;
- case 3: context.Store (physAddr, value); break;
+ case 0:
+ context.Store8(physAddr, value);
+ break;
+ case 1:
+ context.Store16(physAddr, value);
+ break;
+ case 2:
+ context.Store(physAddr, value);
+ break;
+ case 3:
+ context.Store(physAddr, value);
+ break;
}
if (!context.Memory.Type.IsHostMapped())
@@ -321,7 +360,7 @@ private static void EmitWriteVector(
int size)
{
Operand lblSlowPath = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true, size);
@@ -329,11 +368,21 @@ private static void EmitWriteVector(
switch (size)
{
- case 0: context.Store8 (physAddr, context.VectorExtract8(value, elem)); break;
- case 1: context.Store16(physAddr, context.VectorExtract16(value, elem)); break;
- case 2: context.Store (physAddr, context.VectorExtract(OperandType.I32, value, elem)); break;
- case 3: context.Store (physAddr, context.VectorExtract(OperandType.I64, value, elem)); break;
- case 4: context.Store (physAddr, value); break;
+ case 0:
+ context.Store8(physAddr, context.VectorExtract8(value, elem));
+ break;
+ case 1:
+ context.Store16(physAddr, context.VectorExtract16(value, elem));
+ break;
+ case 2:
+ context.Store(physAddr, context.VectorExtract(OperandType.I32, value, elem));
+ break;
+ case 3:
+ context.Store(physAddr, context.VectorExtract(OperandType.I64, value, elem));
+ break;
+ case 4:
+ context.Store(physAddr, value);
+ break;
}
if (!context.Memory.Type.IsHostMapped())
@@ -464,10 +513,18 @@ private static Operand EmitReadIntFallback(ArmEmitterContext context, Operand ad
switch (size)
{
- case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break;
- case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break;
- case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break;
- case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break;
+ case 0:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte));
+ break;
+ case 1:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16));
+ break;
+ case 2:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32));
+ break;
+ case 3:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64));
+ break;
}
return context.Call(info, address);
@@ -485,21 +542,39 @@ private static void EmitReadVectorFallback(
switch (size)
{
- case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break;
- case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break;
- case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break;
- case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break;
- case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128)); break;
+ case 0:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte));
+ break;
+ case 1:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16));
+ break;
+ case 2:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32));
+ break;
+ case 3:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64));
+ break;
+ case 4:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128));
+ break;
}
Operand value = context.Call(info, address);
switch (size)
{
- case 0: value = context.VectorInsert8 (vector, value, elem); break;
- case 1: value = context.VectorInsert16(vector, value, elem); break;
- case 2: value = context.VectorInsert (vector, value, elem); break;
- case 3: value = context.VectorInsert (vector, value, elem); break;
+ case 0:
+ value = context.VectorInsert8(vector, value, elem);
+ break;
+ case 1:
+ value = context.VectorInsert16(vector, value, elem);
+ break;
+ case 2:
+ value = context.VectorInsert(vector, value, elem);
+ break;
+ case 3:
+ value = context.VectorInsert(vector, value, elem);
+ break;
}
context.Copy(GetVec(rt), value);
@@ -511,10 +586,18 @@ private static void EmitWriteIntFallback(ArmEmitterContext context, Operand addr
switch (size)
{
- case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break;
- case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break;
- case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break;
- case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break;
+ case 0:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte));
+ break;
+ case 1:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16));
+ break;
+ case 2:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32));
+ break;
+ case 3:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64));
+ break;
}
Operand value = GetInt(context, rt);
@@ -538,11 +621,21 @@ private static void EmitWriteVectorFallback(
switch (size)
{
- case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break;
- case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break;
- case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break;
- case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break;
- case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)); break;
+ case 0:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte));
+ break;
+ case 1:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16));
+ break;
+ case 2:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32));
+ break;
+ case 3:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64));
+ break;
+ case 4:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128));
+ break;
}
Operand value = default;
@@ -551,10 +644,18 @@ private static void EmitWriteVectorFallback(
{
switch (size)
{
- case 0: value = context.VectorExtract8 (GetVec(rt), elem); break;
- case 1: value = context.VectorExtract16(GetVec(rt), elem); break;
- case 2: value = context.VectorExtract (OperandType.I32, GetVec(rt), elem); break;
- case 3: value = context.VectorExtract (OperandType.I64, GetVec(rt), elem); break;
+ case 0:
+ value = context.VectorExtract8(GetVec(rt), elem);
+ break;
+ case 1:
+ value = context.VectorExtract16(GetVec(rt), elem);
+ break;
+ case 2:
+ value = context.VectorExtract(OperandType.I32, GetVec(rt), elem);
+ break;
+ case 3:
+ value = context.VectorExtract(OperandType.I64, GetVec(rt), elem);
+ break;
}
}
else
@@ -585,18 +686,14 @@ private static void SetInt(ArmEmitterContext context, int rt, Operand value)
// ARM32 helpers.
public static Operand GetMemM(ArmEmitterContext context, bool setCarry = true)
{
- switch (context.CurrOp)
+ return context.CurrOp switch
{
- case IOpCode32MemRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
-
- case IOpCode32MemReg op: return GetIntA32(context, op.Rm);
-
- case IOpCode32Mem op: return Const(op.Immediate);
-
- case OpCode32SimdMemImm op: return Const(op.Immediate);
-
- default: throw InvalidOpCodeType(context.CurrOp);
- }
+ IOpCode32MemRsImm op => GetMShiftedByImmediate(context, op, setCarry),
+ IOpCode32MemReg op => GetIntA32(context, op.Rm),
+ IOpCode32Mem op => Const(op.Immediate),
+ OpCode32SimdMemImm op => Const(op.Immediate),
+ _ => throw InvalidOpCodeType(context.CurrOp),
+ };
}
private static Exception InvalidOpCodeType(OpCode opCode)
@@ -614,9 +711,15 @@ public static Operand GetMShiftedByImmediate(ArmEmitterContext context, IOpCode3
{
switch (op.ShiftType)
{
- case ShiftType.Lsr: shift = 32; break;
- case ShiftType.Asr: shift = 32; break;
- case ShiftType.Ror: shift = 1; break;
+ case ShiftType.Lsr:
+ shift = 32;
+ break;
+ case ShiftType.Asr:
+ shift = 32;
+ break;
+ case ShiftType.Ror:
+ shift = 1;
+ break;
}
}
@@ -626,9 +729,15 @@ public static Operand GetMShiftedByImmediate(ArmEmitterContext context, IOpCode3
switch (op.ShiftType)
{
- case ShiftType.Lsl: m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift); break;
- case ShiftType.Lsr: m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift); break;
- case ShiftType.Asr: m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift); break;
+ case ShiftType.Lsl:
+ m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift);
+ break;
+ case ShiftType.Lsr:
+ m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift);
+ break;
+ case ShiftType.Asr:
+ m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift);
+ break;
case ShiftType.Ror:
if (op.Immediate != 0)
{
diff --git a/src/ARMeilleure/Instructions/InstEmitMove.cs b/src/ARMeilleure/Instructions/InstEmitMove.cs
index d551bf2da..f23ac333b 100644
--- a/src/ARMeilleure/Instructions/InstEmitMove.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMove.cs
@@ -38,4 +38,4 @@ public static void Movz(ArmEmitterContext context)
SetIntOrZR(context, op.Rd, Const(op.GetOperandType(), op.Immediate));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitMul.cs b/src/ARMeilleure/Instructions/InstEmitMul.cs
index 65d11b30d..89dc09938 100644
--- a/src/ARMeilleure/Instructions/InstEmitMul.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMul.cs
@@ -2,7 +2,7 @@
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System;
-
+using System.Diagnostics.CodeAnalysis;
using static ARMeilleure.Instructions.InstEmitHelper;
namespace ARMeilleure.Instructions
@@ -33,14 +33,15 @@ private static void EmitMul(ArmEmitterContext context, bool isAdd)
public static void Umsubl(ArmEmitterContext context) => EmitMull(context, MullFlags.Subtract);
[Flags]
+ [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
private enum MullFlags
{
Subtract = 0,
- Add = 1 << 0,
- Signed = 1 << 1,
+ Add = 1 << 0,
+ Signed = 1 << 1,
- SignedAdd = Signed | Add,
- SignedSubtract = Signed | Subtract
+ SignedAdd = Signed | Add,
+ SignedSubtract = Signed | Subtract,
}
private static void EmitMull(ArmEmitterContext context, MullFlags flags)
@@ -97,4 +98,4 @@ public static void Umulh(ArmEmitterContext context)
SetIntOrZR(context, op.Rd, d);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitMul32.cs b/src/ARMeilleure/Instructions/InstEmitMul32.cs
index 0822f92c3..b9966ad1d 100644
--- a/src/ARMeilleure/Instructions/InstEmitMul32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitMul32.cs
@@ -1,9 +1,8 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
-
using static ARMeilleure.Instructions.InstEmitAluHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -20,7 +19,7 @@ private enum MullFlags
Signed = 1 << 2,
SignedAdd = Signed | Add,
- SignedSubtract = Signed | Subtract
+ SignedSubtract = Signed | Subtract,
}
public static void Mla(ArmEmitterContext context)
@@ -287,14 +286,14 @@ public static void Umaal(ArmEmitterContext context)
{
IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
- Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn));
- Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm));
+ Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn));
+ Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm));
Operand dHi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.RdHi));
Operand dLo = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.RdLo));
Operand res = context.Multiply(n, m);
- res = context.Add(res, dHi);
- res = context.Add(res, dLo);
+ res = context.Add(res, dHi);
+ res = context.Add(res, dLo);
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
Operand lo = context.ConvertI64ToI32(res);
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
index 7e7f26b1a..543aab023 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
@@ -7,7 +7,6 @@
using ARMeilleure.Translation;
using System;
using System.Diagnostics;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
@@ -185,11 +184,12 @@ public static void Clz_V(ArmEmitterContext context)
int eSize = 8 << op.Size;
- Operand res = eSize switch {
- 8 => Clz_V_I8 (context, GetVec(op.Rn)),
+ Operand res = eSize switch
+ {
+ 8 => Clz_V_I8(context, GetVec(op.Rn)),
16 => Clz_V_I16(context, GetVec(op.Rn)),
32 => Clz_V_I32(context, GetVec(op.Rn)),
- _ => default
+ _ => default,
};
if (res != default)
@@ -230,14 +230,14 @@ private static Operand Clz_V_I8(ArmEmitterContext context, Operand arg)
Operand clzTable = X86GetScalar(context, 0x01_01_01_01_02_02_03_04);
Operand maskLow = X86GetAllElements(context, 0x0f_0f_0f_0f);
- Operand c04 = X86GetAllElements(context, 0x04_04_04_04);
+ Operand c04 = X86GetAllElements(context, 0x04_04_04_04);
// CLZ of low 4 bits of elements in arg.
Operand loClz = context.AddIntrinsic(Intrinsic.X86Pshufb, clzTable, arg);
// Get the high 4 bits of elements in arg.
Operand hiArg = context.AddIntrinsic(Intrinsic.X86Psrlw, arg, Const(4));
- hiArg = context.AddIntrinsic(Intrinsic.X86Pand, hiArg, maskLow);
+ hiArg = context.AddIntrinsic(Intrinsic.X86Pand, hiArg, maskLow);
// CLZ of high 4 bits of elements in arg.
Operand hiClz = context.AddIntrinsic(Intrinsic.X86Pshufb, clzTable, hiArg);
@@ -257,8 +257,8 @@ private static Operand Clz_V_I16(ArmEmitterContext context, Operand arg)
}
Operand maskSwap = X86GetElements(context, 0x80_0f_80_0d_80_0b_80_09, 0x80_07_80_05_80_03_80_01);
- Operand maskLow = X86GetAllElements(context, 0x00ff_00ff);
- Operand c0008 = X86GetAllElements(context, 0x0008_0008);
+ Operand maskLow = X86GetAllElements(context, 0x00ff_00ff);
+ Operand c0008 = X86GetAllElements(context, 0x0008_0008);
// CLZ pair of high 8 and low 8 bits of elements in arg.
Operand hiloClz = Clz_V_I8(context, arg);
@@ -282,12 +282,14 @@ private static Operand Clz_V_I32(ArmEmitterContext context, Operand arg)
return default;
}
+#pragma warning disable IDE0055 // Disable formatting
Operand AddVectorI32(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Paddd, op0, op1);
Operand SubVectorI32(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Psubd, op0, op1);
Operand ShiftRightVectorUI32(Operand op0, int imm8) => context.AddIntrinsic(Intrinsic.X86Psrld, op0, Const(imm8));
Operand OrVector(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Por, op0, op1);
Operand AndVector(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Pand, op0, op1);
Operand NotVector(Operand op0) => context.AddIntrinsic(Intrinsic.X86Pandn, op0, context.VectorOne());
+#pragma warning restore IDE0055
Operand c55555555 = X86GetAllElements(context, 0x55555555);
Operand c33333333 = X86GetAllElements(context, 0x33333333);
@@ -311,24 +313,24 @@ private static Operand Clz_V_I32(ArmEmitterContext context, Operand arg)
// Count leading 1s, which is the population count.
tmp0 = ShiftRightVectorUI32(res, 1);
tmp0 = AndVector(tmp0, c55555555);
- res = SubVectorI32(res, tmp0);
+ res = SubVectorI32(res, tmp0);
tmp0 = ShiftRightVectorUI32(res, 2);
tmp0 = AndVector(tmp0, c33333333);
tmp1 = AndVector(res, c33333333);
- res = AddVectorI32(tmp0, tmp1);
+ res = AddVectorI32(tmp0, tmp1);
tmp0 = ShiftRightVectorUI32(res, 4);
tmp0 = AddVectorI32(tmp0, res);
- res = AndVector(tmp0, c0f0f0f0f);
+ res = AndVector(tmp0, c0f0f0f0f);
tmp0 = ShiftRightVectorUI32(res, 8);
- res = AddVectorI32(tmp0, res);
+ res = AddVectorI32(tmp0, res);
tmp0 = ShiftRightVectorUI32(res, 16);
- res = AddVectorI32(tmp0, res);
+ res = AddVectorI32(tmp0, res);
- res = AndVector(res, c0000003f);
+ res = AndVector(res, c0000003f);
return res;
}
@@ -881,6 +883,31 @@ public static void Fmaxnmv_V(ArmEmitterContext context)
}
}
+ public static void Fmaxp_S(ArmEmitterContext context)
+ {
+ if (Optimizations.UseAdvSimd)
+ {
+ InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FmaxpS);
+ }
+ else if (Optimizations.FastFP && Optimizations.UseSse41)
+ {
+ EmitSse2ScalarPairwiseOpF(context, (op1, op2) =>
+ {
+ return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
+ {
+ return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: true);
+ }, scalar: true, op1, op2);
+ });
+ }
+ else
+ {
+ EmitScalarPairwiseOpF(context, (op1, op2) =>
+ {
+ return EmitSoftFloatCall(context, nameof(SoftFloat32.FPMax), op1, op2);
+ });
+ }
+ }
+
public static void Fmaxp_V(ArmEmitterContext context)
{
if (Optimizations.UseAdvSimd)
@@ -1079,6 +1106,31 @@ public static void Fminnmv_V(ArmEmitterContext context)
}
}
+ public static void Fminp_S(ArmEmitterContext context)
+ {
+ if (Optimizations.UseAdvSimd)
+ {
+ InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FminpS);
+ }
+ else if (Optimizations.FastFP && Optimizations.UseSse41)
+ {
+ EmitSse2ScalarPairwiseOpF(context, (op1, op2) =>
+ {
+ return EmitSse41ProcessNaNsOpF(context, (op1, op2) =>
+ {
+ return EmitSse2VectorMaxMinOpF(context, op1, op2, isMax: false);
+ }, scalar: true, op1, op2);
+ });
+ }
+ else
+ {
+ EmitScalarPairwiseOpF(context, (op1, op2) =>
+ {
+ return EmitSoftFloatCall(context, nameof(SoftFloat32.FPMin), op1, op2);
+ });
+ }
+ }
+
public static void Fminp_V(ArmEmitterContext context)
{
if (Optimizations.UseAdvSimd)
@@ -2436,8 +2488,8 @@ public static void Frsqrts_S(ArmEmitterContext context) // Fused.
if (sizeF == 0)
{
- Operand maskHalf = X86GetScalar(context, 0.5f);
- Operand maskThree = X86GetScalar(context, 3f);
+ Operand maskHalf = X86GetScalar(context, 0.5f);
+ Operand maskThree = X86GetScalar(context, 3f);
Operand maskOneHalf = X86GetScalar(context, 1.5f);
if (Optimizations.UseFma)
@@ -2457,8 +2509,8 @@ public static void Frsqrts_S(ArmEmitterContext context) // Fused.
}
else /* if (sizeF == 1) */
{
- Operand maskHalf = X86GetScalar(context, 0.5d);
- Operand maskThree = X86GetScalar(context, 3d);
+ Operand maskHalf = X86GetScalar(context, 0.5d);
+ Operand maskThree = X86GetScalar(context, 3d);
Operand maskOneHalf = X86GetScalar(context, 1.5d);
if (Optimizations.UseFma)
@@ -2505,8 +2557,8 @@ public static void Frsqrts_V(ArmEmitterContext context) // Fused.
if (sizeF == 0)
{
- Operand maskHalf = X86GetAllElements(context, 0.5f);
- Operand maskThree = X86GetAllElements(context, 3f);
+ Operand maskHalf = X86GetAllElements(context, 0.5f);
+ Operand maskThree = X86GetAllElements(context, 3f);
Operand maskOneHalf = X86GetAllElements(context, 1.5f);
if (Optimizations.UseFma)
@@ -2519,7 +2571,7 @@ public static void Frsqrts_V(ArmEmitterContext context) // Fused.
res = context.AddIntrinsic(Intrinsic.X86Subps, maskThree, res);
}
- res = context.AddIntrinsic(Intrinsic.X86Mulps, maskHalf, res);
+ res = context.AddIntrinsic(Intrinsic.X86Mulps, maskHalf, res);
res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: false, sizeF);
if (op.RegisterSize == RegisterSize.Simd64)
@@ -2531,8 +2583,8 @@ public static void Frsqrts_V(ArmEmitterContext context) // Fused.
}
else /* if (sizeF == 1) */
{
- Operand maskHalf = X86GetAllElements(context, 0.5d);
- Operand maskThree = X86GetAllElements(context, 3d);
+ Operand maskHalf = X86GetAllElements(context, 0.5d);
+ Operand maskThree = X86GetAllElements(context, 3d);
Operand maskOneHalf = X86GetAllElements(context, 1.5d);
if (Optimizations.UseFma)
@@ -2545,7 +2597,7 @@ public static void Frsqrts_V(ArmEmitterContext context) // Fused.
res = context.AddIntrinsic(Intrinsic.X86Subpd, maskThree, res);
}
- res = context.AddIntrinsic(Intrinsic.X86Mulpd, maskHalf, res);
+ res = context.AddIntrinsic(Intrinsic.X86Mulpd, maskHalf, res);
res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: false, sizeF);
context.Copy(GetVec(op.Rd), res);
@@ -2824,10 +2876,10 @@ public static void Pmull_V(ArmEmitterContext context)
for (int i = 0; i < 8; i++)
{
Operand mask = context.AddIntrinsic(Intrinsic.X86Psllw, n, Const(15 - i));
- mask = context.AddIntrinsic(Intrinsic.X86Psraw, mask, Const(15));
+ mask = context.AddIntrinsic(Intrinsic.X86Psraw, mask, Const(15));
Operand tmp = context.AddIntrinsic(Intrinsic.X86Psllw, m, Const(i));
- tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask);
+ tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask);
res = context.AddIntrinsic(Intrinsic.X86Pxor, res, tmp);
}
@@ -2839,12 +2891,12 @@ public static void Pmull_V(ArmEmitterContext context)
for (int i = 0; i < 64; i++)
{
Operand mask = context.AddIntrinsic(Intrinsic.X86Movlhps, n, n);
- mask = context.AddIntrinsic(Intrinsic.X86Psllq, mask, Const(63 - i));
- mask = context.AddIntrinsic(Intrinsic.X86Psrlq, mask, Const(63));
- mask = context.AddIntrinsic(Intrinsic.X86Psubq, zero, mask);
+ mask = context.AddIntrinsic(Intrinsic.X86Psllq, mask, Const(63 - i));
+ mask = context.AddIntrinsic(Intrinsic.X86Psrlq, mask, Const(63));
+ mask = context.AddIntrinsic(Intrinsic.X86Psubq, zero, mask);
Operand tmp = EmitSse2Sll_128(context, m, i);
- tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask);
+ tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask);
res = context.AddIntrinsic(Intrinsic.X86Pxor, res, tmp);
}
@@ -3119,7 +3171,7 @@ public static void Shadd_V(ArmEmitterContext context)
Operand n = GetVec(op.Rn);
Operand m = GetVec(op.Rm);
- Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m);
+ Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m);
Operand res2 = context.AddIntrinsic(Intrinsic.X86Pxor, n, m);
Intrinsic shiftInst = op.Size == 1 ? Intrinsic.X86Psraw : Intrinsic.X86Psrad;
@@ -4058,7 +4110,7 @@ public static void Uhadd_V(ArmEmitterContext context)
Operand n = GetVec(op.Rn);
Operand m = GetVec(op.Rm);
- Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m);
+ Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m);
Operand res2 = context.AddIntrinsic(Intrinsic.X86Pxor, n, m);
Intrinsic shiftInst = op.Size == 1 ? Intrinsic.X86Psrlw : Intrinsic.X86Psrld;
@@ -4594,7 +4646,7 @@ private static void EmitAddLongPairwise(ArmEmitterContext context, bool signed,
{
int pairIndex = index << 1;
- Operand ne0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
+ Operand ne0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
Operand ne1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed);
Operand e = context.Add(ne0, ne1);
@@ -4686,7 +4738,7 @@ private static Operand EmitMax64Op(ArmEmitterContext context, Operand op1, Opera
Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);
Operand cmp = signed
- ? context.ICompareGreaterOrEqual (op1, op2)
+ ? context.ICompareGreaterOrEqual(op1, op2)
: context.ICompareGreaterOrEqualUI(op1, op2);
return context.ConditionalSelect(cmp, op1, op2);
@@ -4697,7 +4749,7 @@ private static Operand EmitMin64Op(ArmEmitterContext context, Operand op1, Opera
Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);
Operand cmp = signed
- ? context.ICompareLessOrEqual (op1, op2)
+ ? context.ICompareLessOrEqual(op1, op2)
: context.ICompareLessOrEqualUI(op1, op2);
return context.ConditionalSelect(cmp, op1, op2);
@@ -4852,10 +4904,10 @@ public static void EmitSse2VectorIsNaNOpF(
Operand mask1 = context.AddIntrinsic(Intrinsic.X86Cmpps, opF, opF, Const((int)CmpCondition.UnorderedQ));
- Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask);
- mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, mask2, qMask, Const((int)CmpCondition.Equal));
+ Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask);
+ mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, mask2, qMask, Const((int)CmpCondition.Equal));
- qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andps, mask2, mask1) : default;
+ qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andps, mask2, mask1) : default;
sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnps, mask2, mask1) : default;
}
else /* if ((op.Size & 1) == 1) */
@@ -4866,10 +4918,10 @@ public static void EmitSse2VectorIsNaNOpF(
Operand mask1 = context.AddIntrinsic(Intrinsic.X86Cmppd, opF, opF, Const((int)CmpCondition.UnorderedQ));
- Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask);
- mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, mask2, qMask, Const((int)CmpCondition.Equal));
+ Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask);
+ mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, mask2, qMask, Const((int)CmpCondition.Equal));
- qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andpd, mask2, mask1) : default;
+ qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andpd, mask2, mask1) : default;
sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnpd, mask2, mask1) : default;
}
}
@@ -4895,11 +4947,11 @@ public static Operand EmitSse41ProcessNaNsOpF(
Operand qMask = scalar ? X86GetScalar(context, 1 << QBit) : X86GetAllElements(context, 1 << QBit);
- Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask);
- resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask);
+ Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask);
+ resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask);
Operand resNaN = context.AddIntrinsic(Intrinsic.X86Blendvps, mCopy, nCopy, resNaNMask);
- resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask);
+ resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask);
Operand resMask = context.AddIntrinsic(Intrinsic.X86Cmpps, nCopy, mCopy, Const((int)CmpCondition.OrderedQ));
@@ -4929,11 +4981,11 @@ public static Operand EmitSse41ProcessNaNsOpF(
Operand qMask = scalar ? X86GetScalar(context, 1L << QBit) : X86GetAllElements(context, 1L << QBit);
- Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask);
- resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask);
+ Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask);
+ resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask);
Operand resNaN = context.AddIntrinsic(Intrinsic.X86Blendvpd, mCopy, nCopy, resNaNMask);
- resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask);
+ resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask);
Operand resMask = context.AddIntrinsic(Intrinsic.X86Cmppd, nCopy, mCopy, Const((int)CmpCondition.OrderedQ));
@@ -4964,10 +5016,10 @@ private static Operand EmitSse2VectorMaxMinOpF(ArmEmitterContext context, Operan
Operand mask = X86GetAllElements(context, -0f);
Operand res = context.AddIntrinsic(isMax ? Intrinsic.X86Maxps : Intrinsic.X86Minps, n, m);
- res = context.AddIntrinsic(Intrinsic.X86Andnps, mask, res);
+ res = context.AddIntrinsic(Intrinsic.X86Andnps, mask, res);
Operand resSign = context.AddIntrinsic(isMax ? Intrinsic.X86Pand : Intrinsic.X86Por, n, m);
- resSign = context.AddIntrinsic(Intrinsic.X86Andps, mask, resSign);
+ resSign = context.AddIntrinsic(Intrinsic.X86Andps, mask, resSign);
return context.AddIntrinsic(Intrinsic.X86Por, res, resSign);
}
@@ -4976,10 +5028,10 @@ private static Operand EmitSse2VectorMaxMinOpF(ArmEmitterContext context, Operan
Operand mask = X86GetAllElements(context, -0d);
Operand res = context.AddIntrinsic(isMax ? Intrinsic.X86Maxpd : Intrinsic.X86Minpd, n, m);
- res = context.AddIntrinsic(Intrinsic.X86Andnpd, mask, res);
+ res = context.AddIntrinsic(Intrinsic.X86Andnpd, mask, res);
Operand resSign = context.AddIntrinsic(isMax ? Intrinsic.X86Pand : Intrinsic.X86Por, n, m);
- resSign = context.AddIntrinsic(Intrinsic.X86Andpd, mask, resSign);
+ resSign = context.AddIntrinsic(Intrinsic.X86Andpd, mask, resSign);
return context.AddIntrinsic(Intrinsic.X86Por, res, resSign);
}
@@ -5003,7 +5055,7 @@ private static Operand EmitSse41MaxMinNumOpF(
if (sizeF == 0)
{
Operand negInfMask = scalar
- ? X86GetScalar (context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity)
+ ? X86GetScalar(context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity)
: X86GetAllElements(context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity);
Operand nMask = context.AddIntrinsic(Intrinsic.X86Andnps, mQNaNMask, nQNaNMask);
@@ -5038,7 +5090,7 @@ private static Operand EmitSse41MaxMinNumOpF(
else /* if (sizeF == 1) */
{
Operand negInfMask = scalar
- ? X86GetScalar (context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity)
+ ? X86GetScalar(context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity)
: X86GetAllElements(context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity);
Operand nMask = context.AddIntrinsic(Intrinsic.X86Andnpd, mQNaNMask, nQNaNMask);
@@ -5072,7 +5124,7 @@ private enum AddSub
{
None,
Add,
- Subtract
+ Subtract,
}
private static void EmitSse41VectorMul_AddSub(ArmEmitterContext context, AddSub addSub)
@@ -5187,10 +5239,10 @@ private static void EmitSse41VectorUabdOp(
Intrinsic subInst = X86PsubInstruction[size];
- Operand res = context.AddIntrinsic(subInst, n, m);
+ Operand res = context.AddIntrinsic(subInst, n, m);
Operand res2 = context.AddIntrinsic(subInst, m, n);
- res = context.AddIntrinsic(Intrinsic.X86Pand, cmpMask, res);
+ res = context.AddIntrinsic(Intrinsic.X86Pand, cmpMask, res);
res2 = context.AddIntrinsic(Intrinsic.X86Pandn, cmpMask, res2);
res = context.AddIntrinsic(Intrinsic.X86Por, res, res2);
@@ -5214,7 +5266,7 @@ private static Operand EmitSse2Sll_128(ArmEmitterContext context, Operand op, in
}
Operand high = context.AddIntrinsic(Intrinsic.X86Pslldq, op, Const(8));
- high = context.AddIntrinsic(Intrinsic.X86Psrlq, high, Const(64 - shift));
+ high = context.AddIntrinsic(Intrinsic.X86Psrlq, high, Const(64 - shift));
Operand low = context.AddIntrinsic(Intrinsic.X86Psllq, op, Const(shift));
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs
index a9994e412..27608ebf8 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs
@@ -1,8 +1,7 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System;
-
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
@@ -190,7 +189,7 @@ public static void Vdup(ArmEmitterContext context)
2 => context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u)),
1 => context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u)),
0 => context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u)),
- _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\".")
+ _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\"."),
};
InsertScalar(context, op.Vd, insert);
@@ -212,7 +211,7 @@ public static void Vdup_1(ArmEmitterContext context)
2 => context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u)),
1 => context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u)),
0 => context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u)),
- _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\".")
+ _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\"."),
};
InsertScalar(context, op.Vd, insert);
@@ -1654,7 +1653,7 @@ private static void EmitSse41MaxMinNumOpF32(ArmEmitterContext context, bool isMa
{
IOpCode32Simd op = (IOpCode32Simd)context.CurrOp;
- Func genericEmit = (n, m) =>
+ Operand genericEmit(Operand n, Operand m)
{
Operand nNum = context.Copy(n);
Operand mNum = context.Copy(m);
@@ -1688,7 +1687,7 @@ private static void EmitSse41MaxMinNumOpF32(ArmEmitterContext context, bool isMa
return context.AddIntrinsic(isMaxNum ? Intrinsic.X86Maxpd : Intrinsic.X86Minpd, nNum, mNum);
}
- };
+ }
if (scalar)
{
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs b/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs
index c32b64ba1..aab677869 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs
@@ -3,7 +3,6 @@
using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -493,7 +492,7 @@ private static void EmitFccmpOrFccmpe(ArmEmitterContext context, bool signalNaNs
OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp;
Operand lblTrue = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
context.BranchIfTrue(lblTrue, InstEmitFlowHelper.GetCondTrue(context, op.Cond));
@@ -510,7 +509,7 @@ private static void EmitFccmpOrFccmpe(ArmEmitterContext context, bool signalNaNs
private static void EmitSetNzcv(ArmEmitterContext context, int nzcv)
{
- Operand Extract(int value, int bit)
+ static Operand Extract(int value, int bit)
{
if (bit != 0)
{
@@ -532,7 +531,7 @@ private static void EmitFcmpOrFcmpe(ArmEmitterContext context, bool signalNaNs)
{
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
- bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false;
+ bool cmpWithZero = op is not OpCodeSimdFcond && op.Bit3;
if (Optimizations.FastFP && (signalNaNs ? Optimizations.UseAvx : Optimizations.UseSse2))
{
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCmp32.cs b/src/ARMeilleure/Instructions/InstEmitSimdCmp32.cs
index a990e057d..1d68bce6b 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdCmp32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdCmp32.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCrypto.cs b/src/ARMeilleure/Instructions/InstEmitSimdCrypto.cs
index db24e0290..6226e35ae 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdCrypto.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdCrypto.cs
@@ -17,7 +17,11 @@ public static void Aesd_V(ArmEmitterContext context)
Operand res;
- if (Optimizations.UseAesni)
+ if (Optimizations.UseArm64Aes)
+ {
+ res = context.AddIntrinsic(Intrinsic.Arm64AesdV, d, n);
+ }
+ else if (Optimizations.UseAesni)
{
res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
}
@@ -38,7 +42,11 @@ public static void Aese_V(ArmEmitterContext context)
Operand res;
- if (Optimizations.UseAesni)
+ if (Optimizations.UseArm64Aes)
+ {
+ res = context.AddIntrinsic(Intrinsic.Arm64AeseV, d, n);
+ }
+ else if (Optimizations.UseAesni)
{
res = context.AddIntrinsic(Intrinsic.X86Aesenclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
}
@@ -58,7 +66,11 @@ public static void Aesimc_V(ArmEmitterContext context)
Operand res;
- if (Optimizations.UseAesni)
+ if (Optimizations.UseArm64Aes)
+ {
+ res = context.AddIntrinsic(Intrinsic.Arm64AesimcV, n);
+ }
+ else if (Optimizations.UseAesni)
{
res = context.AddIntrinsic(Intrinsic.X86Aesimc, n);
}
@@ -78,7 +90,11 @@ public static void Aesmc_V(ArmEmitterContext context)
Operand res;
- if (Optimizations.UseAesni)
+ if (Optimizations.UseArm64Aes)
+ {
+ res = context.AddIntrinsic(Intrinsic.Arm64AesmcV, n);
+ }
+ else if (Optimizations.UseAesni)
{
Operand roundKey = context.VectorZero();
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs b/src/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs
index f713a388c..7a0c981e7 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
@@ -17,7 +17,11 @@ public static void Aesd_V(ArmEmitterContext context)
Operand res;
- if (Optimizations.UseAesni)
+ if (Optimizations.UseArm64Aes)
+ {
+ res = context.AddIntrinsic(Intrinsic.Arm64AesdV, d, n);
+ }
+ else if (Optimizations.UseAesni)
{
res = context.AddIntrinsic(Intrinsic.X86Aesdeclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
}
@@ -38,7 +42,11 @@ public static void Aese_V(ArmEmitterContext context)
Operand res;
- if (Optimizations.UseAesni)
+ if (Optimizations.UseArm64Aes)
+ {
+ res = context.AddIntrinsic(Intrinsic.Arm64AeseV, d, n);
+ }
+ else if (Optimizations.UseAesni)
{
res = context.AddIntrinsic(Intrinsic.X86Aesenclast, context.AddIntrinsic(Intrinsic.X86Xorpd, d, n), context.VectorZero());
}
@@ -58,7 +66,11 @@ public static void Aesimc_V(ArmEmitterContext context)
Operand res;
- if (Optimizations.UseAesni)
+ if (Optimizations.UseArm64Aes)
+ {
+ res = context.AddIntrinsic(Intrinsic.Arm64AesimcV, n);
+ }
+ else if (Optimizations.UseAesni)
{
res = context.AddIntrinsic(Intrinsic.X86Aesimc, n);
}
@@ -78,7 +90,11 @@ public static void Aesmc_V(ArmEmitterContext context)
Operand res;
- if (Optimizations.UseAesni)
+ if (Optimizations.UseArm64Aes)
+ {
+ res = context.AddIntrinsic(Intrinsic.Arm64AesmcV, n);
+ }
+ else if (Optimizations.UseAesni)
{
Operand roundKey = context.VectorZero();
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs b/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs
index 652ad397c..3363a7c77 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs
@@ -5,7 +5,6 @@
using System;
using System.Diagnostics;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -67,8 +66,8 @@ public static void Fcvt_S(ArmEmitterContext context)
Operand n = GetVec(op.Rn);
Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
- res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112()
- res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14));
+ res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112()
+ res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14));
context.Copy(GetVec(op.Rd), res);
}
@@ -92,7 +91,7 @@ public static void Fcvt_S(ArmEmitterContext context)
Debug.Assert(!Optimizations.ForceLegacySse);
Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
- res = context.VectorZeroUpper96(res);
+ res = context.VectorZeroUpper96(res);
context.Copy(GetVec(op.Rd), res);
}
@@ -116,7 +115,7 @@ public static void Fcvt_S(ArmEmitterContext context)
Operand n = GetVec(op.Rn);
Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n);
- res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
+ res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
context.Copy(GetVec(op.Rd), res);
}
@@ -140,8 +139,8 @@ public static void Fcvt_S(ArmEmitterContext context)
Operand n = GetVec(op.Rn);
Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn));
- res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res);
- res = context.VectorZeroUpper64(res);
+ res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res);
+ res = context.VectorZeroUpper64(res);
context.Copy(GetVec(op.Rd), res);
}
@@ -273,7 +272,7 @@ public static void Fcvtl_V(ArmEmitterContext context)
Operand n = GetVec(op.Rn);
Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
- res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
+ res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res);
context.Copy(GetVec(op.Rd), res);
}
@@ -284,7 +283,7 @@ public static void Fcvtl_V(ArmEmitterContext context)
Operand n = GetVec(op.Rn);
Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n;
- res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
+ res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
context.Copy(GetVec(op.Rd), res);
}
@@ -387,10 +386,10 @@ public static void Fcvtn_V(ArmEmitterContext context)
Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn));
- nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
+ nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
Operand res = context.VectorZeroUpper64(d);
- res = context.AddIntrinsic(movInst, res, nInt);
+ res = context.AddIntrinsic(movInst, res, nInt);
context.Copy(d, res);
}
@@ -404,10 +403,10 @@ public static void Fcvtn_V(ArmEmitterContext context)
Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps;
Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
- nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
+ nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt);
Operand res = context.VectorZeroUpper64(d);
- res = context.AddIntrinsic(movInst, res, nInt);
+ res = context.AddIntrinsic(movInst, res, nInt);
context.Copy(d, res);
}
@@ -1225,15 +1224,15 @@ public static Operand EmitSse2CvtDoubleToInt64OpF(ArmEmitterContext context, Ope
{
Debug.Assert(opF.Type == OperandType.V128);
- Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL
- Operand res = context.VectorCreateScalar(longL);
+ Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, opF); // opFL
+ Operand res = context.VectorCreateScalar(longL);
if (!scalar)
{
- Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
- Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH);
- Operand resH = context.VectorCreateScalar(longH);
- res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
+ Operand opFH = context.AddIntrinsic(Intrinsic.X86Movhlps, res, opF); // res doesn't matter.
+ Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, opFH);
+ Operand resH = context.VectorCreateScalar(longH);
+ res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, resH);
}
return res;
@@ -1244,14 +1243,14 @@ private static Operand EmitSse2CvtInt64ToDoubleOp(ArmEmitterContext context, Ope
Debug.Assert(op.Type == OperandType.V128);
Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL
- Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
+ Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL);
if (!scalar)
{
- Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter.
+ Operand opH = context.AddIntrinsic(Intrinsic.X86Movhlps, res, op); // res doesn't matter.
Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH);
- Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
- res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH);
+ Operand resH = context.AddIntrinsic(Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter.
+ res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, resH);
}
return res;
@@ -1278,7 +1277,7 @@ private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
int fpScaled = 0x3F800000 - fBits * 0x800000;
Operand fpScaledMask = scalar
- ? X86GetScalar (context, fpScaled)
+ ? X86GetScalar(context, fpScaled)
: X86GetAllElements(context, fpScaled);
res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
@@ -1307,7 +1306,7 @@ private static void EmitSse2ScvtfOp(ArmEmitterContext context, bool scalar)
long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
Operand fpScaledMask = scalar
- ? X86GetScalar (context, fpScaled)
+ ? X86GetScalar(context, fpScaled)
: X86GetAllElements(context, fpScaled);
res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
@@ -1334,16 +1333,16 @@ private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
if (sizeF == 0)
{
Operand mask = scalar // 65536.000f (1 << 16)
- ? X86GetScalar (context, 0x47800000)
+ ? X86GetScalar(context, 0x47800000)
: X86GetAllElements(context, 0x47800000);
Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16));
- res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
- res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
+ res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res);
+ res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask);
Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16));
- res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
- res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
+ res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16));
+ res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2);
res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2);
@@ -1355,7 +1354,7 @@ private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
int fpScaled = 0x3F800000 - fBits * 0x800000;
Operand fpScaledMask = scalar
- ? X86GetScalar (context, fpScaled)
+ ? X86GetScalar(context, fpScaled)
: X86GetAllElements(context, fpScaled);
res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask);
@@ -1375,16 +1374,16 @@ private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
else /* if (sizeF == 1) */
{
Operand mask = scalar // 4294967296.0000000d (1L << 32)
- ? X86GetScalar (context, 0x41F0000000000000L)
+ ? X86GetScalar(context, 0x41F0000000000000L)
: X86GetAllElements(context, 0x41F0000000000000L);
- Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32));
- res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
- res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask);
+ Operand res = context.AddIntrinsic(Intrinsic.X86Psrlq, n, Const(32));
+ res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar);
+ res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, mask);
- Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32));
- res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32));
- res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
+ Operand res2 = context.AddIntrinsic(Intrinsic.X86Psllq, n, Const(32));
+ res2 = context.AddIntrinsic(Intrinsic.X86Psrlq, res2, Const(32));
+ res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar);
res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2);
@@ -1396,7 +1395,7 @@ private static void EmitSse2UcvtfOp(ArmEmitterContext context, bool scalar)
long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L;
Operand fpScaledMask = scalar
- ? X86GetScalar (context, fpScaled)
+ ? X86GetScalar(context, fpScaled)
: X86GetAllElements(context, fpScaled);
res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask);
@@ -1423,7 +1422,7 @@ private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode
if (sizeF == 0)
{
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
if (op is OpCodeSimdShImm fixedOp)
{
@@ -1433,7 +1432,7 @@ private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode
int fpScaled = 0x3F800000 + fBits * 0x800000;
Operand fpScaledMask = scalar
- ? X86GetScalar (context, fpScaled)
+ ? X86GetScalar(context, fpScaled)
: X86GetAllElements(context, fpScaled);
nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
@@ -1451,7 +1450,7 @@ private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode
Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
- ? X86GetScalar (context, 0x4F000000)
+ ? X86GetScalar(context, 0x4F000000)
: X86GetAllElements(context, 0x4F000000);
nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
@@ -1472,7 +1471,7 @@ private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode
else /* if (sizeF == 1) */
{
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
if (op is OpCodeSimdShImm fixedOp)
{
@@ -1482,7 +1481,7 @@ private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode
long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
Operand fpScaledMask = scalar
- ? X86GetScalar (context, fpScaled)
+ ? X86GetScalar(context, fpScaled)
: X86GetAllElements(context, fpScaled);
nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
@@ -1500,7 +1499,7 @@ private static void EmitSse41FcvtsOpF(ArmEmitterContext context, FPRoundingMode
Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
- ? X86GetScalar (context, 0x43E0000000000000L)
+ ? X86GetScalar(context, 0x43E0000000000000L)
: X86GetAllElements(context, 0x43E0000000000000L);
nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
@@ -1528,7 +1527,7 @@ private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode
if (sizeF == 0)
{
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
if (op is OpCodeSimdShImm fixedOp)
{
@@ -1538,7 +1537,7 @@ private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode
int fpScaled = 0x3F800000 + fBits * 0x800000;
Operand fpScaledMask = scalar
- ? X86GetScalar (context, fpScaled)
+ ? X86GetScalar(context, fpScaled)
: X86GetAllElements(context, fpScaled);
nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask);
@@ -1556,10 +1555,10 @@ private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode
Operand zero = context.VectorZero();
Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648)
- ? X86GetScalar (context, 0x4F000000)
+ ? X86GetScalar(context, 0x4F000000)
: X86GetAllElements(context, 0x4F000000);
Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
@@ -1567,14 +1566,14 @@ private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode
nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
- Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
- dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
+ Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes);
+ dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt);
if (scalar)
{
@@ -1590,7 +1589,7 @@ private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode
else /* if (sizeF == 1) */
{
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
if (op is OpCodeSimdShImm fixedOp)
{
@@ -1600,7 +1599,7 @@ private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode
long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L;
Operand fpScaledMask = scalar
- ? X86GetScalar (context, fpScaled)
+ ? X86GetScalar(context, fpScaled)
: X86GetAllElements(context, fpScaled);
nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask);
@@ -1618,10 +1617,10 @@ private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode
Operand zero = context.VectorZero();
Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808)
- ? X86GetScalar (context, 0x43E0000000000000L)
+ ? X86GetScalar(context, 0x43E0000000000000L)
: X86GetAllElements(context, 0x43E0000000000000L);
Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
@@ -1629,14 +1628,14 @@ private static void EmitSse41FcvtuOpF(ArmEmitterContext context, FPRoundingMode
nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);
nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar);
nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
- Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
- dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
+ Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes);
+ dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong);
if (scalar)
{
@@ -1656,7 +1655,7 @@ private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode
if (op.Size == 0)
{
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
if (isFixed)
{
@@ -1678,7 +1677,7 @@ private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode
}
Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
- ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
+ ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes)
: context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
int fpMaxVal = op.RegisterSize == RegisterSize.Int32
@@ -1703,7 +1702,7 @@ private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode
else /* if (op.Size == 1) */
{
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
if (isFixed)
{
@@ -1725,7 +1724,7 @@ private static void EmitSse41Fcvts_Gp(ArmEmitterContext context, FPRoundingMode
}
Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
- ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
+ ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes)
: context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
long fpMaxVal = op.RegisterSize == RegisterSize.Int32
@@ -1758,7 +1757,7 @@ private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode
if (op.Size == 0)
{
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
if (isFixed)
{
@@ -1782,7 +1781,7 @@ private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode
Operand zero = context.VectorZero();
Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
int fpMaxVal = op.RegisterSize == RegisterSize.Int32
? 0x4F000000 // 2.14748365E9f (2147483648)
@@ -1791,16 +1790,16 @@ private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode
Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
- ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
+ ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes)
: context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask);
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
- ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes)
+ ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes)
: context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes);
nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
@@ -1813,14 +1812,14 @@ private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode
}
Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt);
- dRes = context.Add(dRes, nIntOrLong);
+ dRes = context.Add(dRes, nIntOrLong);
SetIntOrZR(context, op.Rd, dRes);
}
else /* if (op.Size == 1) */
{
Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n);
if (isFixed)
{
@@ -1844,7 +1843,7 @@ private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode
Operand zero = context.VectorZero();
Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
long fpMaxVal = op.RegisterSize == RegisterSize.Int32
? 0x41E0000000000000L // 2147483648.0000000d (2147483648)
@@ -1853,16 +1852,16 @@ private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode
Operand fpMaxValMask = X86GetScalar(context, fpMaxVal);
Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32
- ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
+ ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes)
: context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask);
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
- nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
+ nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp);
Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32
- ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes)
+ ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes)
: context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes);
nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan));
@@ -1875,7 +1874,7 @@ private static void EmitSse41Fcvtu_Gp(ArmEmitterContext context, FPRoundingMode
}
Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong);
- dRes = context.Add(dRes, nIntOrLong);
+ dRes = context.Add(dRes, nIntOrLong);
SetIntOrZR(context, op.Rd, dRes);
}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs b/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs
index 33ae83df6..630e114c4 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs
@@ -1,11 +1,10 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
using System.Diagnostics;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
@@ -115,6 +114,35 @@ public static void Vcvt_V(ArmEmitterContext context)
}
}
+ public static void Vcvt_V_Fixed(ArmEmitterContext context)
+ {
+ OpCode32SimdCvtFFixed op = (OpCode32SimdCvtFFixed)context.CurrOp;
+
+ var toFixed = op.Opc == 1;
+ int fracBits = op.Fbits;
+ var unsigned = op.U;
+
+ if (toFixed) // F32 to S32 or U32 (fixed)
+ {
+ EmitVectorUnaryOpF32(context, (op1) =>
+ {
+ var scaledValue = context.Multiply(op1, ConstF(MathF.Pow(2f, fracBits)));
+ MethodInfo info = unsigned ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32)) : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32));
+
+ return context.Call(info, scaledValue);
+ });
+ }
+ else // S32 or U32 (fixed) to F32
+ {
+ EmitVectorUnaryOpI32(context, (op1) =>
+ {
+ var floatValue = unsigned ? context.ConvertToFPUI(OperandType.FP32, op1) : context.ConvertToFP(OperandType.FP32, op1);
+
+ return context.Multiply(floatValue, ConstF(1f / MathF.Pow(2f, fracBits)));
+ }, !unsigned);
+ }
+ }
+
public static void Vcvt_FD(ArmEmitterContext context)
{
OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
@@ -165,7 +193,7 @@ public static void Vcvt_FI(ArmEmitterContext context)
{
Operand m = GetVecA32(op.Vm >> 1);
- Operand toConvert = InstEmitSimdHelper32Arm64.EmitExtractScalar(context, m, op.Vm, doubleSize);
+ Operand toConvert = InstEmitSimdHelper32Arm64.EmitExtractScalar(context, m, op.Vm, true);
Intrinsic inst = (unsigned ? Intrinsic.Arm64FcvtzuGp : Intrinsic.Arm64FcvtzsGp) | Intrinsic.Arm64VDouble;
@@ -175,7 +203,7 @@ public static void Vcvt_FI(ArmEmitterContext context)
}
else
{
- InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, unsigned ? Intrinsic.Arm64FcvtzuS : Intrinsic.Arm64FcvtzsS);
+ InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, unsigned ? Intrinsic.Arm64FcvtzuS : Intrinsic.Arm64FcvtzsS, false);
}
}
else if (!roundWithFpscr && Optimizations.UseSse41)
@@ -217,33 +245,22 @@ private static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRoun
string name = nameof(Math.Round);
MethodInfo info = (op.Size & 1) == 0
- ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
- : typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
+ ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
+ : typeof(Math).GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
return context.Call(info, n, Const((int)roundMode));
}
private static FPRoundingMode RMToRoundMode(int rm)
{
- FPRoundingMode roundMode;
- switch (rm)
- {
- case 0b00:
- roundMode = FPRoundingMode.ToNearestAway;
- break;
- case 0b01:
- roundMode = FPRoundingMode.ToNearest;
- break;
- case 0b10:
- roundMode = FPRoundingMode.TowardsPlusInfinity;
- break;
- case 0b11:
- roundMode = FPRoundingMode.TowardsMinusInfinity;
- break;
- default:
- throw new ArgumentOutOfRangeException(nameof(rm));
- }
- return roundMode;
+ return rm switch
+ {
+ 0b00 => FPRoundingMode.ToNearestAway,
+ 0b01 => FPRoundingMode.ToNearest,
+ 0b10 => FPRoundingMode.TowardsPlusInfinity,
+ 0b11 => FPRoundingMode.TowardsMinusInfinity,
+ _ => throw new ArgumentOutOfRangeException(nameof(rm)),
+ };
}
// VCVTA/M/N/P (floating-point).
@@ -260,28 +277,68 @@ public static void Vcvt_RM(ArmEmitterContext context)
if (Optimizations.UseAdvSimd)
{
- if (unsigned)
+ bool doubleSize = floatSize == OperandType.FP64;
+
+ if (doubleSize)
{
- inst = rm switch {
- 0b00 => Intrinsic.Arm64FcvtauS,
- 0b01 => Intrinsic.Arm64FcvtnuS,
- 0b10 => Intrinsic.Arm64FcvtpuS,
- 0b11 => Intrinsic.Arm64FcvtmuS,
- _ => throw new ArgumentOutOfRangeException(nameof(rm))
- };
+ Operand m = GetVecA32(op.Vm >> 1);
+
+ Operand toConvert = InstEmitSimdHelper32Arm64.EmitExtractScalar(context, m, op.Vm, true);
+
+ if (unsigned)
+ {
+ inst = rm switch
+ {
+ 0b00 => Intrinsic.Arm64FcvtauGp,
+ 0b01 => Intrinsic.Arm64FcvtnuGp,
+ 0b10 => Intrinsic.Arm64FcvtpuGp,
+ 0b11 => Intrinsic.Arm64FcvtmuGp,
+ _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"),
+ };
+ }
+ else
+ {
+ inst = rm switch
+ {
+ 0b00 => Intrinsic.Arm64FcvtasGp,
+ 0b01 => Intrinsic.Arm64FcvtnsGp,
+ 0b10 => Intrinsic.Arm64FcvtpsGp,
+ 0b11 => Intrinsic.Arm64FcvtmsGp,
+ _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"),
+ };
+ }
+
+ Operand asInteger = context.AddIntrinsicInt(inst | Intrinsic.Arm64VDouble, toConvert);
+
+ InsertScalar(context, op.Vd, asInteger);
}
else
{
- inst = rm switch {
- 0b00 => Intrinsic.Arm64FcvtasS,
- 0b01 => Intrinsic.Arm64FcvtnsS,
- 0b10 => Intrinsic.Arm64FcvtpsS,
- 0b11 => Intrinsic.Arm64FcvtmsS,
- _ => throw new ArgumentOutOfRangeException(nameof(rm))
- };
- }
+ if (unsigned)
+ {
+ inst = rm switch
+ {
+ 0b00 => Intrinsic.Arm64FcvtauS,
+ 0b01 => Intrinsic.Arm64FcvtnuS,
+ 0b10 => Intrinsic.Arm64FcvtpuS,
+ 0b11 => Intrinsic.Arm64FcvtmuS,
+ _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"),
+ };
+ }
+ else
+ {
+ inst = rm switch
+ {
+ 0b00 => Intrinsic.Arm64FcvtasS,
+ 0b01 => Intrinsic.Arm64FcvtnsS,
+ 0b10 => Intrinsic.Arm64FcvtpsS,
+ 0b11 => Intrinsic.Arm64FcvtmsS,
+ _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"),
+ };
+ }
- InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, inst);
+ InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, inst);
+ }
}
else if (Optimizations.UseSse41)
{
@@ -396,12 +453,13 @@ public static void Vrint_RM(ArmEmitterContext context)
if (Optimizations.UseAdvSimd)
{
- Intrinsic inst = rm switch {
+ Intrinsic inst = rm switch
+ {
0b00 => Intrinsic.Arm64FrintaS,
0b01 => Intrinsic.Arm64FrintnS,
0b10 => Intrinsic.Arm64FrintpS,
0b11 => Intrinsic.Arm64FrintmS,
- _ => throw new ArgumentOutOfRangeException(nameof(rm))
+ _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"),
};
InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, inst);
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHash.cs b/src/ARMeilleure/Instructions/InstEmitSimdHash.cs
index 4fb048eed..aee12d7dc 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdHash.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdHash.cs
@@ -8,7 +8,7 @@ namespace ARMeilleure.Instructions
{
static partial class InstEmit
{
-#region "Sha1"
+ #region "Sha1"
public static void Sha1c_V(ArmEmitterContext context)
{
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
@@ -89,9 +89,9 @@ public static void Sha1su1_V(ArmEmitterContext context)
context.Copy(GetVec(op.Rd), res);
}
-#endregion
+ #endregion
-#region "Sha256"
+ #region "Sha256"
public static void Sha256h_V(ArmEmitterContext context)
{
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
@@ -142,6 +142,6 @@ public static void Sha256su1_V(ArmEmitterContext context)
context.Copy(GetVec(op.Rd), res);
}
-#endregion
+ #endregion
}
}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs b/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs
index 51334608d..c2bb951ab 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs
@@ -8,7 +8,7 @@ namespace ARMeilleure.Instructions
{
static partial class InstEmit32
{
-#region "Sha256"
+ #region "Sha256"
public static void Sha256h_V(ArmEmitterContext context)
{
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
@@ -59,6 +59,6 @@ public static void Sha256su1_V(ArmEmitterContext context)
context.Copy(GetVecA32(op.Qd), res);
}
-#endregion
+ #endregion
}
}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs b/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs
index 23e4948d9..a672b159f 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs
@@ -18,9 +18,9 @@ public static Operand EmitSha256h(ArmEmitterContext context, Operand x, Operand
Operand round2 = context.AddIntrinsic(Intrinsic.X86Sha256Rnds2, src1, src2, w);
Operand round4 = context.AddIntrinsic(Intrinsic.X86Sha256Rnds2, src2, round2, w2);
-
+
Operand res = context.AddIntrinsic(Intrinsic.X86Shufps, round4, round2, Const(part2 ? 0x11 : 0xbb));
-
+
return res;
}
@@ -53,4 +53,4 @@ public static Operand EmitSha256su1(ArmEmitterContext context, Operand x, Operan
return context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart2)), x, y, z);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs
index c44c9b4d9..abd0d9acc 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs
@@ -6,7 +6,6 @@
using System;
using System.Diagnostics;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -18,39 +17,39 @@ namespace ARMeilleure.Instructions
static class InstEmitSimdHelper
{
-#region "Masks"
+ #region "Masks"
public static readonly long[] EvenMasks = new long[]
{
14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0, // B
13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0, // H
- 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0 // S
+ 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0, // S
};
public static readonly long[] OddMasks = new long[]
{
15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0, // B
15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0, // H
- 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0 // S
+ 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0, // S
};
- public static readonly long ZeroMask = 128L << 56 | 128L << 48 | 128L << 40 | 128L << 32 | 128L << 24 | 128L << 16 | 128L << 8 | 128L << 0;
+ public const long ZeroMask = 128L << 56 | 128L << 48 | 128L << 40 | 128L << 32 | 128L << 24 | 128L << 16 | 128L << 8 | 128L << 0;
public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
{
ulong identity = (0b00000001UL << 56) | (0b00000010UL << 48) | (0b00000100UL << 40) | (0b00001000UL << 32) |
- (0b00010000UL << 24) | (0b00100000UL << 16) | (0b01000000UL << 8) | (0b10000000UL << 0);
+ (0b00010000UL << 24) | (0b00100000UL << 16) | (0b01000000UL << 8) | (0b10000000UL << 0);
return shift >= 0 ? identity >> (shift * 8) : identity << (-shift * 8);
}
-#endregion
+ #endregion
-#region "X86 SSE Intrinsics"
+ #region "X86 SSE Intrinsics"
public static readonly Intrinsic[] X86PaddInstruction = new Intrinsic[]
{
Intrinsic.X86Paddb,
Intrinsic.X86Paddw,
Intrinsic.X86Paddd,
- Intrinsic.X86Paddq
+ Intrinsic.X86Paddq,
};
public static readonly Intrinsic[] X86PcmpeqInstruction = new Intrinsic[]
@@ -58,7 +57,7 @@ public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
Intrinsic.X86Pcmpeqb,
Intrinsic.X86Pcmpeqw,
Intrinsic.X86Pcmpeqd,
- Intrinsic.X86Pcmpeqq
+ Intrinsic.X86Pcmpeqq,
};
public static readonly Intrinsic[] X86PcmpgtInstruction = new Intrinsic[]
@@ -66,49 +65,49 @@ public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
Intrinsic.X86Pcmpgtb,
Intrinsic.X86Pcmpgtw,
Intrinsic.X86Pcmpgtd,
- Intrinsic.X86Pcmpgtq
+ Intrinsic.X86Pcmpgtq,
};
public static readonly Intrinsic[] X86PmaxsInstruction = new Intrinsic[]
{
Intrinsic.X86Pmaxsb,
Intrinsic.X86Pmaxsw,
- Intrinsic.X86Pmaxsd
+ Intrinsic.X86Pmaxsd,
};
public static readonly Intrinsic[] X86PmaxuInstruction = new Intrinsic[]
{
Intrinsic.X86Pmaxub,
Intrinsic.X86Pmaxuw,
- Intrinsic.X86Pmaxud
+ Intrinsic.X86Pmaxud,
};
public static readonly Intrinsic[] X86PminsInstruction = new Intrinsic[]
{
Intrinsic.X86Pminsb,
Intrinsic.X86Pminsw,
- Intrinsic.X86Pminsd
+ Intrinsic.X86Pminsd,
};
public static readonly Intrinsic[] X86PminuInstruction = new Intrinsic[]
{
Intrinsic.X86Pminub,
Intrinsic.X86Pminuw,
- Intrinsic.X86Pminud
+ Intrinsic.X86Pminud,
};
public static readonly Intrinsic[] X86PmovsxInstruction = new Intrinsic[]
{
Intrinsic.X86Pmovsxbw,
Intrinsic.X86Pmovsxwd,
- Intrinsic.X86Pmovsxdq
+ Intrinsic.X86Pmovsxdq,
};
public static readonly Intrinsic[] X86PmovzxInstruction = new Intrinsic[]
{
Intrinsic.X86Pmovzxbw,
Intrinsic.X86Pmovzxwd,
- Intrinsic.X86Pmovzxdq
+ Intrinsic.X86Pmovzxdq,
};
public static readonly Intrinsic[] X86PsllInstruction = new Intrinsic[]
@@ -116,14 +115,14 @@ public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
0,
Intrinsic.X86Psllw,
Intrinsic.X86Pslld,
- Intrinsic.X86Psllq
+ Intrinsic.X86Psllq,
};
public static readonly Intrinsic[] X86PsraInstruction = new Intrinsic[]
{
0,
Intrinsic.X86Psraw,
- Intrinsic.X86Psrad
+ Intrinsic.X86Psrad,
};
public static readonly Intrinsic[] X86PsrlInstruction = new Intrinsic[]
@@ -131,7 +130,7 @@ public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
0,
Intrinsic.X86Psrlw,
Intrinsic.X86Psrld,
- Intrinsic.X86Psrlq
+ Intrinsic.X86Psrlq,
};
public static readonly Intrinsic[] X86PsubInstruction = new Intrinsic[]
@@ -139,7 +138,7 @@ public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
Intrinsic.X86Psubb,
Intrinsic.X86Psubw,
Intrinsic.X86Psubd,
- Intrinsic.X86Psubq
+ Intrinsic.X86Psubq,
};
public static readonly Intrinsic[] X86PunpckhInstruction = new Intrinsic[]
@@ -147,7 +146,7 @@ public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
Intrinsic.X86Punpckhbw,
Intrinsic.X86Punpckhwd,
Intrinsic.X86Punpckhdq,
- Intrinsic.X86Punpckhqdq
+ Intrinsic.X86Punpckhqdq,
};
public static readonly Intrinsic[] X86PunpcklInstruction = new Intrinsic[]
@@ -155,9 +154,9 @@ public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
Intrinsic.X86Punpcklbw,
Intrinsic.X86Punpcklwd,
Intrinsic.X86Punpckldq,
- Intrinsic.X86Punpcklqdq
+ Intrinsic.X86Punpcklqdq,
};
-#endregion
+ #endregion
public static void EnterArmFpMode(EmitterContext context, Func getFpFlag)
{
@@ -310,15 +309,16 @@ public static Operand X86GetElements(ArmEmitterContext context, ulong e1, ulong
public static int X86GetRoundControl(FPRoundingMode roundMode)
{
- switch (roundMode)
+ return roundMode switch
{
- case FPRoundingMode.ToNearest: return 8 | 0; // even
- case FPRoundingMode.TowardsPlusInfinity: return 8 | 2;
- case FPRoundingMode.TowardsMinusInfinity: return 8 | 1;
- case FPRoundingMode.TowardsZero: return 8 | 3;
- }
-
- throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
+#pragma warning disable IDE0055 // Disable formatting
+ FPRoundingMode.ToNearest => 8 | 0, // even
+ FPRoundingMode.TowardsPlusInfinity => 8 | 2,
+ FPRoundingMode.TowardsMinusInfinity => 8 | 1,
+ FPRoundingMode.TowardsZero => 8 | 3,
+ _ => throw new ArgumentException($"Invalid rounding mode \"{roundMode}\"."),
+#pragma warning restore IDE0055
+ };
}
public static Operand EmitSse41RoundToNearestWithTiesToAwayOpF(ArmEmitterContext context, Operand n, bool scalar)
@@ -334,11 +334,11 @@ public static Operand EmitSse41RoundToNearestWithTiesToAwayOpF(ArmEmitterContext
if ((op.Size & 1) == 0)
{
Operand signMask = scalar ? X86GetScalar(context, int.MinValue) : X86GetAllElements(context, int.MinValue);
- signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy);
+ signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy);
// 0x3EFFFFFF == BitConverter.SingleToInt32Bits(0.5f) - 1
Operand valueMask = scalar ? X86GetScalar(context, 0x3EFFFFFF) : X86GetAllElements(context, 0x3EFFFFFF);
- valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask);
+ valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask);
nCopy = context.AddIntrinsic(scalar ? Intrinsic.X86Addss : Intrinsic.X86Addps, nCopy, valueMask);
@@ -347,11 +347,11 @@ public static Operand EmitSse41RoundToNearestWithTiesToAwayOpF(ArmEmitterContext
else
{
Operand signMask = scalar ? X86GetScalar(context, long.MinValue) : X86GetAllElements(context, long.MinValue);
- signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy);
+ signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy);
// 0x3FDFFFFFFFFFFFFFL == BitConverter.DoubleToInt64Bits(0.5d) - 1L
Operand valueMask = scalar ? X86GetScalar(context, 0x3FDFFFFFFFFFFFFFL) : X86GetAllElements(context, 0x3FDFFFFFFFFFFFFFL);
- valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask);
+ valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask);
nCopy = context.AddIntrinsic(scalar ? Intrinsic.X86Addsd : Intrinsic.X86Addpd, nCopy, valueMask);
@@ -461,7 +461,7 @@ public static Operand EmitUnaryMathCall(ArmEmitterContext context, string name,
MethodInfo info = (op.Size & 1) == 0
? typeof(MathF).GetMethod(name, new Type[] { typeof(float) })
- : typeof(Math). GetMethod(name, new Type[] { typeof(double) });
+ : typeof(Math).GetMethod(name, new Type[] { typeof(double) });
return context.Call(info, n);
}
@@ -473,8 +473,8 @@ public static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRound
string name = nameof(Math.Round);
MethodInfo info = (op.Size & 1) == 0
- ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
- : typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
+ ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
+ : typeof(Math).GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
return context.Call(info, n, Const((int)roundMode));
}
@@ -482,7 +482,7 @@ public static Operand EmitRoundMathCall(ArmEmitterContext context, MidpointRound
public static Operand EmitGetRoundingMode(ArmEmitterContext context)
{
Operand rMode = context.ShiftLeft(GetFpFlag(FPState.RMode1Flag), Const(1));
- rMode = context.BitwiseOr(rMode, GetFpFlag(FPState.RMode0Flag));
+ rMode = context.BitwiseOr(rMode, GetFpFlag(FPState.RMode0Flag));
return rMode;
}
@@ -1015,8 +1015,8 @@ private static void EmitVectorWidenRmBinaryOp(ArmEmitterContext context, Func2I
for (int index = 0; index < elems; index++)
{
- Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed);
- Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
+ Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed);
+ Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
}
@@ -1077,9 +1077,9 @@ private static void EmitVectorWidenRnRmTernaryOp(ArmEmitterContext context, Func
for (int index = 0; index < elems; index++)
{
- Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
- Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
- Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
+ Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
+ Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
+ Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
}
@@ -1143,8 +1143,8 @@ private static void EmitVectorWidenTernaryOpByElem(ArmEmitterContext context, Fu
for (int index = 0; index < elems; index++)
{
- Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
- Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
+ Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
+ Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
}
@@ -1174,13 +1174,13 @@ private static void EmitVectorPairwiseOp(ArmEmitterContext context, Func2I emit,
{
int pairIndex = index << 1;
- Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
+ Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
Operand n1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed);
- Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed);
+ Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed);
Operand m1 = EmitVectorExtract(context, op.Rm, pairIndex + 1, op.Size, signed);
- res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size);
+ res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size);
res = EmitVectorInsert(context, res, emit(m0, m1), pairs + index, op.Size);
}
@@ -1197,11 +1197,11 @@ public static void EmitSsse3VectorPairwiseOp(ArmEmitterContext context, Intrinsi
if (op.RegisterSize == RegisterSize.Simd64)
{
Operand zeroEvenMask = X86GetElements(context, ZeroMask, EvenMasks[op.Size]);
- Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks [op.Size]);
+ Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks[op.Size]);
Operand mN = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); // m:n
- Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
+ Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
@@ -1213,14 +1213,14 @@ public static void EmitSsse3VectorPairwiseOp(ArmEmitterContext context, Intrinsi
Operand oddEvenN = context.AddIntrinsic(Intrinsic.X86Pshufb, n, oddEvenMask); // odd:even from n
Operand oddEvenM = context.AddIntrinsic(Intrinsic.X86Pshufb, m, oddEvenMask); // odd:even from m
- Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
+ Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM);
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
}
else
{
- Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
+ Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m);
context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[3], left, right));
@@ -1299,17 +1299,17 @@ public static void EmitSse2VectorAcrossVectorOpF(ArmEmitterContext context, Func
Debug.Assert((op.Size & 1) == 0 && op.RegisterSize == RegisterSize.Simd128);
- const int sm0 = 0 << 6 | 0 << 4 | 0 << 2 | 0 << 0;
- const int sm1 = 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0;
- const int sm2 = 2 << 6 | 2 << 4 | 2 << 2 | 2 << 0;
- const int sm3 = 3 << 6 | 3 << 4 | 3 << 2 | 3 << 0;
+ const int SM0 = 0 << 6 | 0 << 4 | 0 << 2 | 0 << 0;
+ const int SM1 = 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0;
+ const int SM2 = 2 << 6 | 2 << 4 | 2 << 2 | 2 << 0;
+ const int SM3 = 3 << 6 | 3 << 4 | 3 << 2 | 3 << 0;
Operand nCopy = context.Copy(GetVec(op.Rn));
- Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm0));
- Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm1));
- Operand part2 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm2));
- Operand part3 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm3));
+ Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM0));
+ Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM1));
+ Operand part2 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM2));
+ Operand part3 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM3));
Operand res = emit(emit(part0, part1), emit(part2, part3));
@@ -1340,13 +1340,13 @@ public static void EmitSse2ScalarPairwiseOpF(ArmEmitterContext context, Func2I e
if ((op.Size & 1) == 0)
{
- const int sm0 = 2 << 6 | 2 << 4 | 2 << 2 | 0 << 0;
- const int sm1 = 2 << 6 | 2 << 4 | 2 << 2 | 1 << 0;
+ const int SM0 = 2 << 6 | 2 << 4 | 2 << 2 | 0 << 0;
+ const int SM1 = 2 << 6 | 2 << 4 | 2 << 2 | 1 << 0;
Operand zeroN = context.VectorZeroUpper64(n);
- op0 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(sm0));
- op1 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(sm1));
+ op0 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(SM0));
+ op1 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(SM1));
}
else /* if ((op.Size & 1) == 1) */
{
@@ -1381,7 +1381,7 @@ public static void EmitVectorPairwiseOpF(ArmEmitterContext context, Func2I emit)
Operand m0 = context.VectorExtract(type, GetVec(op.Rm), pairIndex);
Operand m1 = context.VectorExtract(type, GetVec(op.Rm), pairIndex + 1);
- res = context.VectorInsert(res, emit(n0, n1), index);
+ res = context.VectorInsert(res, emit(n0, n1), index);
res = context.VectorInsert(res, emit(m0, m1), pairs + index);
}
@@ -1412,11 +1412,11 @@ public static void EmitSse2VectorPairwiseOpF(ArmEmitterContext context, Func2I e
}
else /* if (op.RegisterSize == RegisterSize.Simd128) */
{
- const int sm0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0;
- const int sm1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0;
+ const int SM0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0;
+ const int SM1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0;
- Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm0));
- Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm1));
+ Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(SM0));
+ Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(SM1));
context.Copy(GetVec(op.Rd), emit(part0, part1));
}
@@ -1433,18 +1433,18 @@ public static void EmitSse2VectorPairwiseOpF(ArmEmitterContext context, Func2I e
public enum CmpCondition
{
// Legacy Sse.
- Equal = 0, // Ordered, non-signaling.
- LessThan = 1, // Ordered, signaling.
- LessThanOrEqual = 2, // Ordered, signaling.
- UnorderedQ = 3, // Non-signaling.
- NotLessThan = 5, // Unordered, signaling.
+ Equal = 0, // Ordered, non-signaling.
+ LessThan = 1, // Ordered, signaling.
+ LessThanOrEqual = 2, // Ordered, signaling.
+ UnorderedQ = 3, // Non-signaling.
+ NotLessThan = 5, // Unordered, signaling.
NotLessThanOrEqual = 6, // Unordered, signaling.
- OrderedQ = 7, // Non-signaling.
+ OrderedQ = 7, // Non-signaling.
// Vex.
GreaterThanOrEqual = 13, // Ordered, signaling.
- GreaterThan = 14, // Ordered, signaling.
- OrderedS = 23 // Signaling.
+ GreaterThan = 14, // Ordered, signaling.
+ OrderedS = 23, // Signaling.
}
[Flags]
@@ -1459,7 +1459,7 @@ public enum SaturatingFlags
Add = 1 << 3,
Sub = 1 << 4,
- Accumulate = 1 << 5
+ Accumulate = 1 << 5,
}
public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
@@ -1579,7 +1579,7 @@ public static void EmitSaturatingBinaryOp(ArmEmitterContext context, Func2I emit
{
Operand de;
Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, !signed);
- Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed);
+ Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed);
if (op.Size <= 2)
{
@@ -1627,7 +1627,7 @@ public static void EmitSaturatingBinaryOp(ArmEmitterContext context, Func2I emit
[Flags]
public enum SaturatingNarrowFlags
{
- Scalar = 1 << 0,
+ Scalar = 1 << 0,
SignedSrc = 1 << 1,
SignedDst = 1 << 2,
@@ -1637,14 +1637,14 @@ public enum SaturatingNarrowFlags
VectorSxSx = SignedSrc | SignedDst,
VectorSxZx = SignedSrc,
- VectorZxZx = 0
+ VectorZxZx = 0,
}
public static void EmitSaturatingNarrowOp(ArmEmitterContext context, SaturatingNarrowFlags flags)
{
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
- bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
+ bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0;
bool signedDst = (flags & SaturatingNarrowFlags.SignedDst) != 0;
@@ -2034,18 +2034,30 @@ public static Operand EmitVectorExtract(ArmEmitterContext context, int reg, int
{
switch (size)
{
- case 0: res = context.SignExtend8 (OperandType.I64, res); break;
- case 1: res = context.SignExtend16(OperandType.I64, res); break;
- case 2: res = context.SignExtend32(OperandType.I64, res); break;
+ case 0:
+ res = context.SignExtend8(OperandType.I64, res);
+ break;
+ case 1:
+ res = context.SignExtend16(OperandType.I64, res);
+ break;
+ case 2:
+ res = context.SignExtend32(OperandType.I64, res);
+ break;
}
}
else
{
switch (size)
{
- case 0: res = context.ZeroExtend8 (OperandType.I64, res); break;
- case 1: res = context.ZeroExtend16(OperandType.I64, res); break;
- case 2: res = context.ZeroExtend32(OperandType.I64, res); break;
+ case 0:
+ res = context.ZeroExtend8(OperandType.I64, res);
+ break;
+ case 1:
+ res = context.ZeroExtend16(OperandType.I64, res);
+ break;
+ case 2:
+ res = context.ZeroExtend32(OperandType.I64, res);
+ break;
}
}
@@ -2063,10 +2075,18 @@ public static Operand EmitVectorInsert(ArmEmitterContext context, Operand vector
switch (size)
{
- case 0: vector = context.VectorInsert8 (vector, value, index); break;
- case 1: vector = context.VectorInsert16(vector, value, index); break;
- case 2: vector = context.VectorInsert (vector, value, index); break;
- case 3: vector = context.VectorInsert (vector, value, index); break;
+ case 0:
+ vector = context.VectorInsert8(vector, value, index);
+ break;
+ case 1:
+ vector = context.VectorInsert16(vector, value, index);
+ break;
+ case 2:
+ vector = context.VectorInsert(vector, value, index);
+ break;
+ case 3:
+ vector = context.VectorInsert(vector, value, index);
+ break;
}
return vector;
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
index 36d27d425..c1c59b87b 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
@@ -4,7 +4,6 @@
using System;
using System.Diagnostics;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -19,18 +18,13 @@ static class InstEmitSimdHelper32
{
public static (int, int) GetQuadwordAndSubindex(int index, RegisterSize size)
{
- switch (size)
+ return size switch
{
- case RegisterSize.Simd128:
- return (index >> 1, 0);
- case RegisterSize.Simd64:
- case RegisterSize.Int64:
- return (index >> 1, index & 1);
- case RegisterSize.Int32:
- return (index >> 2, index & 3);
- }
-
- throw new ArgumentException("Unrecognized Vector Register Size.");
+ RegisterSize.Simd128 => (index >> 1, 0),
+ RegisterSize.Simd64 or RegisterSize.Int64 => (index >> 1, index & 1),
+ RegisterSize.Int32 => (index >> 2, index & 3),
+ _ => throw new ArgumentException("Unrecognized Vector Register Size."),
+ };
}
public static Operand ExtractScalar(ArmEmitterContext context, OperandType type, int reg)
@@ -327,7 +321,7 @@ public static void EmitVectorBinaryWideOpI32(ArmEmitterContext context, Func2I e
for (int index = 0; index < elems; index++)
{
Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size + 1, signed);
- Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
+ Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
if (op.Size == 2)
{
@@ -380,8 +374,8 @@ public static void EmitVectorTernaryLongOpI32(ArmEmitterContext context, Func3I
for (int index = 0; index < elems; index++)
{
Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size + 1, signed);
- Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
- Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
+ Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed);
+ Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
if (op.Size == 2)
{
@@ -778,7 +772,10 @@ public static Operand EmitSwapScalar(ArmEmitterContext context, Operand target,
{
// Index into 0, 0 into index. This swap happens at the start of an A32 scalar op if required.
int index = reg & (doubleWidth ? 1 : 3);
- if (index == 0) return target;
+ if (index == 0)
+ {
+ return target;
+ }
if (doubleWidth)
{
@@ -974,7 +971,7 @@ public static void EmitScalarBinaryOpF32(ArmEmitterContext context, Intrinsic in
Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32;
- EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m));
+ EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m));
}
public static void EmitScalarTernaryOpSimd32(ArmEmitterContext context, Func3I scalarFunc)
@@ -1195,7 +1192,7 @@ public static Operand EmitSoftFloatCallDefaultFpscr(ArmEmitterContext context, s
: typeof(SoftFloat64).GetMethod(name);
Array.Resize(ref callArgs, callArgs.Length + 1);
- callArgs[callArgs.Length - 1] = Const(1);
+ callArgs[^1] = Const(1);
context.ExitArmFpMode();
context.StoreToContext();
@@ -1245,16 +1242,24 @@ public static Operand EmitVectorExtract32(ArmEmitterContext context, int reg, in
{
switch (size)
{
- case 0: res = context.SignExtend8(OperandType.I32, res); break;
- case 1: res = context.SignExtend16(OperandType.I32, res); break;
+ case 0:
+ res = context.SignExtend8(OperandType.I32, res);
+ break;
+ case 1:
+ res = context.SignExtend16(OperandType.I32, res);
+ break;
}
}
else
{
switch (size)
{
- case 0: res = context.ZeroExtend8(OperandType.I32, res); break;
- case 1: res = context.ZeroExtend16(OperandType.I32, res); break;
+ case 0:
+ res = context.ZeroExtend8(OperandType.I32, res);
+ break;
+ case 1:
+ res = context.ZeroExtend16(OperandType.I32, res);
+ break;
}
}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs
index 98236be6d..568c07122 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs
@@ -1,11 +1,9 @@
-
using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
using System.Diagnostics;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -74,7 +72,10 @@ public static Operand EmitScalarInsert(ArmEmitterContext context, Operand target
public static Operand EmitExtractScalar(ArmEmitterContext context, Operand target, int reg, bool doubleWidth)
{
int index = reg & (doubleWidth ? 1 : 3);
- if (index == 0) return target; // Element is already at index 0, so just return the vector directly.
+ if (index == 0)
+ {
+ return target; // Element is already at index 0, so just return the vector directly.
+ }
if (doubleWidth)
{
@@ -192,11 +193,10 @@ public static void EmitVectorTernaryOpF32(ArmEmitterContext context, Intrinsic i
EmitVectorTernaryOpSimd32(context, (d, n, m) => context.AddIntrinsic(inst, d, n, m));
}
- public static void EmitScalarUnaryOpSimd32(ArmEmitterContext context, Func1I scalarFunc)
+ public static void EmitScalarUnaryOpSimd32(ArmEmitterContext context, Func1I scalarFunc, bool doubleSize)
{
OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
- bool doubleSize = (op.Size & 1) != 0;
int shift = doubleSize ? 1 : 2;
Operand m = GetVecA32(op.Vm >> shift);
Operand d = GetVecA32(op.Vd >> shift);
@@ -215,8 +215,13 @@ public static void EmitScalarUnaryOpF32(ArmEmitterContext context, Intrinsic ins
{
OpCode32SimdS op = (OpCode32SimdS)context.CurrOp;
- inst |= ((op.Size & 1) != 0 ? Intrinsic.Arm64VDouble : Intrinsic.Arm64VFloat) | Intrinsic.Arm64V128;
- EmitScalarUnaryOpSimd32(context, (m) => (inst == 0) ? m : context.AddIntrinsic(inst, m));
+ EmitScalarUnaryOpF32(context, inst, (op.Size & 1) != 0);
+ }
+
+ public static void EmitScalarUnaryOpF32(ArmEmitterContext context, Intrinsic inst, bool doubleSize)
+ {
+ inst |= (doubleSize ? Intrinsic.Arm64VDouble : Intrinsic.Arm64VFloat) | Intrinsic.Arm64V128;
+ EmitScalarUnaryOpSimd32(context, (m) => (inst == 0) ? m : context.AddIntrinsic(inst, m), doubleSize);
}
public static void EmitScalarBinaryOpSimd32(ArmEmitterContext context, Func2I scalarFunc)
@@ -245,7 +250,7 @@ public static void EmitScalarBinaryOpF32(ArmEmitterContext context, Intrinsic in
OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
inst |= ((op.Size & 1) != 0 ? Intrinsic.Arm64VDouble : Intrinsic.Arm64VFloat) | Intrinsic.Arm64V128;
- EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m));
+ EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m));
}
public static void EmitScalarTernaryOpSimd32(ArmEmitterContext context, Func3I scalarFunc)
@@ -332,16 +337,17 @@ public static void EmitCmpOpF32(ArmEmitterContext context, CmpCondition cond, bo
CmpCondition.GreaterThanOrEqual => Intrinsic.Arm64FcmgeVz,
CmpCondition.LessThan => Intrinsic.Arm64FcmltVz,
CmpCondition.LessThanOrEqual => Intrinsic.Arm64FcmleVz,
- _ => throw new InvalidOperationException()
+ _ => throw new InvalidOperationException(),
};
}
- else {
+ else
+ {
inst = cond switch
{
CmpCondition.Equal => Intrinsic.Arm64FcmeqV,
CmpCondition.GreaterThan => Intrinsic.Arm64FcmgtV,
CmpCondition.GreaterThanOrEqual => Intrinsic.Arm64FcmgeV,
- _ => throw new InvalidOperationException()
+ _ => throw new InvalidOperationException(),
};
}
@@ -363,4 +369,4 @@ public static void EmitCmpOpF32(ArmEmitterContext context, CmpCondition cond, bo
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs
index f0d242ae2..70dfc0fbd 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs
@@ -50,7 +50,7 @@ public static void EmitScalarUnaryOpFToGp(ArmEmitterContext context, Intrinsic i
}
SetIntOrZR(context, op.Rd, op.RegisterSize == RegisterSize.Int32
- ? context.AddIntrinsicInt (inst, n)
+ ? context.AddIntrinsicInt(inst, n)
: context.AddIntrinsicLong(inst, n));
}
@@ -288,7 +288,7 @@ public static void EmitScalarConvertBinaryOpFToGp(ArmEmitterContext context, Int
}
SetIntOrZR(context, op.Rd, op.RegisterSize == RegisterSize.Int32
- ? context.AddIntrinsicInt (inst, n, Const(fBits))
+ ? context.AddIntrinsicInt(inst, n, Const(fBits))
: context.AddIntrinsicLong(inst, n, Const(fBits)));
}
@@ -695,7 +695,7 @@ public static void EmitFcmpOrFcmpe(ArmEmitterContext context, bool signalNaNs)
{
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
- bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false;
+ bool cmpWithZero = op is not OpCodeSimdFcond && op.Bit3;
Intrinsic inst = signalNaNs ? Intrinsic.Arm64FcmpeS : Intrinsic.Arm64FcmpS;
@@ -717,4 +717,4 @@ public static void EmitFcmpOrFcmpe(ArmEmitterContext context, bool signalNaNs)
SetFlag(context, PState.NFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const(31)), one));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs b/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs
index 2bf531e6c..ace8e4c54 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs
@@ -3,7 +3,6 @@
using ARMeilleure.Translation;
using System;
using System.Diagnostics;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -80,10 +79,11 @@ public static void Bic_Vi(ArmEmitterContext context)
int eSize = 8 << op.Size;
Operand d = GetVec(op.Rd);
- Operand imm = eSize switch {
+ Operand imm = eSize switch
+ {
16 => X86GetAllElements(context, (short)~op.Immediate),
32 => X86GetAllElements(context, (int)~op.Immediate),
- _ => throw new InvalidOperationException($"Invalid element size {eSize}.")
+ _ => throw new InvalidOperationException($"Invalid element size {eSize}."),
};
Operand res = context.AddIntrinsic(Intrinsic.X86Pand, d, imm);
@@ -380,10 +380,11 @@ public static void Orr_Vi(ArmEmitterContext context)
int eSize = 8 << op.Size;
Operand d = GetVec(op.Rd);
- Operand imm = eSize switch {
+ Operand imm = eSize switch
+ {
16 => X86GetAllElements(context, (short)op.Immediate),
32 => X86GetAllElements(context, (int)op.Immediate),
- _ => throw new InvalidOperationException($"Invalid element size {eSize}.")
+ _ => throw new InvalidOperationException($"Invalid element size {eSize}."),
};
Operand res = context.AddIntrinsic(Intrinsic.X86Por, d, imm);
@@ -407,17 +408,17 @@ public static void Rbit_V(ArmEmitterContext context)
if (Optimizations.UseGfni)
{
- const long bitMatrix =
+ const long BitMatrix =
(0b10000000L << 56) |
(0b01000000L << 48) |
(0b00100000L << 40) |
(0b00010000L << 32) |
(0b00001000L << 24) |
(0b00000100L << 16) |
- (0b00000010L << 8) |
- (0b00000001L << 0);
+ (0b00000010L << 8) |
+ (0b00000001L << 0);
- Operand vBitMatrix = X86GetAllElements(context, bitMatrix);
+ Operand vBitMatrix = X86GetAllElements(context, BitMatrix);
Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, GetVec(op.Rn), vBitMatrix, Const(0));
@@ -451,13 +452,13 @@ private static Operand EmitReverseBits8Op(ArmEmitterContext context, Operand op)
Debug.Assert(op.Type == OperandType.I64);
Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaul)), Const(1)),
- context.ShiftLeft (context.BitwiseAnd(op, Const(0x55ul)), Const(1)));
+ context.ShiftLeft(context.BitwiseAnd(op, Const(0x55ul)), Const(1)));
val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccul)), Const(2)),
- context.ShiftLeft (context.BitwiseAnd(val, Const(0x33ul)), Const(2)));
+ context.ShiftLeft(context.BitwiseAnd(val, Const(0x33ul)), Const(2)));
return context.BitwiseOr(context.ShiftRightUI(val, Const(4)),
- context.ShiftLeft (context.BitwiseAnd(val, Const(0x0ful)), Const(4)));
+ context.ShiftLeft(context.BitwiseAnd(val, Const(0x0ful)), Const(4)));
}
public static void Rev16_V(ArmEmitterContext context)
@@ -468,12 +469,12 @@ public static void Rev16_V(ArmEmitterContext context)
Operand n = GetVec(op.Rn);
- const long maskE0 = 06L << 56 | 07L << 48 | 04L << 40 | 05L << 32 | 02L << 24 | 03L << 16 | 00L << 8 | 01L << 0;
- const long maskE1 = 14L << 56 | 15L << 48 | 12L << 40 | 13L << 32 | 10L << 24 | 11L << 16 | 08L << 8 | 09L << 0;
+ const long MaskE0 = 06L << 56 | 07L << 48 | 04L << 40 | 05L << 32 | 02L << 24 | 03L << 16 | 00L << 8 | 01L << 0;
+ const long MaskE1 = 14L << 56 | 15L << 48 | 12L << 40 | 13L << 32 | 10L << 24 | 11L << 16 | 08L << 8 | 09L << 0;
- Operand mask = X86GetScalar(context, maskE0);
+ Operand mask = X86GetScalar(context, MaskE0);
- mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
+ mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
@@ -502,21 +503,21 @@ public static void Rev32_V(ArmEmitterContext context)
if (op.Size == 0)
{
- const long maskE0 = 04L << 56 | 05L << 48 | 06L << 40 | 07L << 32 | 00L << 24 | 01L << 16 | 02L << 8 | 03L << 0;
- const long maskE1 = 12L << 56 | 13L << 48 | 14L << 40 | 15L << 32 | 08L << 24 | 09L << 16 | 10L << 8 | 11L << 0;
+ const long MaskE0 = 04L << 56 | 05L << 48 | 06L << 40 | 07L << 32 | 00L << 24 | 01L << 16 | 02L << 8 | 03L << 0;
+ const long MaskE1 = 12L << 56 | 13L << 48 | 14L << 40 | 15L << 32 | 08L << 24 | 09L << 16 | 10L << 8 | 11L << 0;
- mask = X86GetScalar(context, maskE0);
+ mask = X86GetScalar(context, MaskE0);
- mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
+ mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
else /* if (op.Size == 1) */
{
- const long maskE0 = 05L << 56 | 04L << 48 | 07L << 40 | 06L << 32 | 01L << 24 | 00L << 16 | 03L << 8 | 02L << 0;
- const long maskE1 = 13L << 56 | 12L << 48 | 15L << 40 | 14L << 32 | 09L << 24 | 08L << 16 | 11L << 8 | 10L << 0;
+ const long MaskE0 = 05L << 56 | 04L << 48 | 07L << 40 | 06L << 32 | 01L << 24 | 00L << 16 | 03L << 8 | 02L << 0;
+ const long MaskE1 = 13L << 56 | 12L << 48 | 15L << 40 | 14L << 32 | 09L << 24 | 08L << 16 | 11L << 8 | 10L << 0;
- mask = X86GetScalar(context, maskE0);
+ mask = X86GetScalar(context, MaskE0);
- mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
+ mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
@@ -546,30 +547,30 @@ public static void Rev64_V(ArmEmitterContext context)
if (op.Size == 0)
{
- const long maskE0 = 00L << 56 | 01L << 48 | 02L << 40 | 03L << 32 | 04L << 24 | 05L << 16 | 06L << 8 | 07L << 0;
- const long maskE1 = 08L << 56 | 09L << 48 | 10L << 40 | 11L << 32 | 12L << 24 | 13L << 16 | 14L << 8 | 15L << 0;
+ const long MaskE0 = 00L << 56 | 01L << 48 | 02L << 40 | 03L << 32 | 04L << 24 | 05L << 16 | 06L << 8 | 07L << 0;
+ const long MaskE1 = 08L << 56 | 09L << 48 | 10L << 40 | 11L << 32 | 12L << 24 | 13L << 16 | 14L << 8 | 15L << 0;
- mask = X86GetScalar(context, maskE0);
+ mask = X86GetScalar(context, MaskE0);
- mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
+ mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
else if (op.Size == 1)
{
- const long maskE0 = 01L << 56 | 00L << 48 | 03L << 40 | 02L << 32 | 05L << 24 | 04L << 16 | 07L << 8 | 06L << 0;
- const long maskE1 = 09L << 56 | 08L << 48 | 11L << 40 | 10L << 32 | 13L << 24 | 12L << 16 | 15L << 8 | 14L << 0;
+ const long MaskE0 = 01L << 56 | 00L << 48 | 03L << 40 | 02L << 32 | 05L << 24 | 04L << 16 | 07L << 8 | 06L << 0;
+ const long MaskE1 = 09L << 56 | 08L << 48 | 11L << 40 | 10L << 32 | 13L << 24 | 12L << 16 | 15L << 8 | 14L << 0;
- mask = X86GetScalar(context, maskE0);
+ mask = X86GetScalar(context, MaskE0);
- mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
+ mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
else /* if (op.Size == 2) */
{
- const long maskE0 = 03L << 56 | 02L << 48 | 01L << 40 | 00L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0;
- const long maskE1 = 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 15L << 24 | 14L << 16 | 13L << 8 | 12L << 0;
+ const long MaskE0 = 03L << 56 | 02L << 48 | 01L << 40 | 00L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0;
+ const long MaskE1 = 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 15L << 24 | 14L << 16 | 13L << 8 | 12L << 0;
- mask = X86GetScalar(context, maskE0);
+ mask = X86GetScalar(context, MaskE0);
- mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
+ mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
index 68ef4ed17..26d093447 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
@@ -52,9 +52,15 @@ public static void Vbic_II(ArmEmitterContext context)
// Replicate fields to fill the 64-bits, if size is < 64-bits.
switch (op.Size)
{
- case 0: immediate *= 0x0101010101010101L; break;
- case 1: immediate *= 0x0001000100010001L; break;
- case 2: immediate *= 0x0000000100000001L; break;
+ case 0:
+ immediate *= 0x0101010101010101L;
+ break;
+ case 1:
+ immediate *= 0x0001000100010001L;
+ break;
+ case 2:
+ immediate *= 0x0000000100000001L;
+ break;
}
Operand imm = Const(immediate);
@@ -199,9 +205,15 @@ public static void Vorr_II(ArmEmitterContext context)
// Replicate fields to fill the 64-bits, if size is < 64-bits.
switch (op.Size)
{
- case 0: immediate *= 0x0101010101010101L; break;
- case 1: immediate *= 0x0001000100010001L; break;
- case 2: immediate *= 0x0000000100000001L; break;
+ case 0:
+ immediate *= 0x0101010101010101L;
+ break;
+ case 1:
+ immediate *= 0x0001000100010001L;
+ break;
+ case 2:
+ immediate *= 0x0000000100000001L;
+ break;
}
Operand imm = Const(immediate);
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs b/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs
index 9b19872af..dedf0fa05 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs
@@ -40,6 +40,7 @@ private static void EmitSimdMemMs(ArmEmitterContext context, bool isLoad)
long offset = 0;
+#pragma warning disable IDE0055 // Disable formatting
for (int rep = 0; rep < op.Reps; rep++)
for (int elem = 0; elem < op.Elems; elem++)
for (int sElem = 0; sElem < op.SElems; sElem++)
@@ -66,6 +67,7 @@ private static void EmitSimdMemMs(ArmEmitterContext context, bool isLoad)
offset += 1 << op.Size;
}
+#pragma warning restore IDE0055
if (op.WBack)
{
@@ -157,4 +159,4 @@ private static void EmitSimdMemWBack(ArmEmitterContext context, long offset)
context.Copy(n, context.Add(n, m));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMemory32.cs b/src/ARMeilleure/Instructions/InstEmitSimdMemory32.cs
index b774bd061..35c6dd328 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdMemory32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdMemory32.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMove.cs b/src/ARMeilleure/Instructions/InstEmitSimdMove.cs
index b58a32f69..85c98fe3a 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdMove.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdMove.cs
@@ -3,7 +3,6 @@
using ARMeilleure.Translation;
using System.Collections.Generic;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -12,19 +11,19 @@ namespace ARMeilleure.Instructions
{
static partial class InstEmit
{
-#region "Masks"
+ #region "Masks"
private static readonly long[] _masksE0_Uzp = new long[]
{
13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0,
- 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0
+ 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0,
};
private static readonly long[] _masksE1_Uzp = new long[]
{
15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0,
- 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0
+ 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0,
};
-#endregion
+ #endregion
public static void Dup_Gp(ArmEmitterContext context)
{
@@ -36,9 +35,17 @@ public static void Dup_Gp(ArmEmitterContext context)
{
switch (op.Size)
{
- case 0: n = context.ZeroExtend8 (n.Type, n); n = context.Multiply(n, Const(n.Type, 0x01010101)); break;
- case 1: n = context.ZeroExtend16(n.Type, n); n = context.Multiply(n, Const(n.Type, 0x00010001)); break;
- case 2: n = context.ZeroExtend32(n.Type, n); break;
+ case 0:
+ n = context.ZeroExtend8(n.Type, n);
+ n = context.Multiply(n, Const(n.Type, 0x01010101));
+ break;
+ case 1:
+ n = context.ZeroExtend16(n.Type, n);
+ n = context.Multiply(n, Const(n.Type, 0x00010001));
+ break;
+ case 2:
+ n = context.ZeroExtend32(n.Type, n);
+ break;
}
Operand res = context.VectorInsert(context.VectorZero(), n, 0);
@@ -209,7 +216,7 @@ public static void Fcsel_S(ArmEmitterContext context)
OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp;
Operand lblTrue = Label();
- Operand lblEnd = Label();
+ Operand lblEnd = Label();
Operand isTrue = InstEmitFlowHelper.GetCondTrue(context, op.Cond);
@@ -353,7 +360,7 @@ public static void Ins_V(ArmEmitterContext context)
{
OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
- Operand d = GetVec(op.Rd);
+ Operand d = GetVec(op.Rd);
Operand ne = EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size);
context.Copy(d, EmitVectorInsert(context, d, ne, op.DstIndex, op.Size));
@@ -497,8 +504,12 @@ private static void EmitSse2VectorMoviMvniOp(ArmEmitterContext context, bool not
switch (op.Size)
{
- case 0: imm *= 0x01010101; break;
- case 1: imm *= 0x00010001; break;
+ case 0:
+ imm *= 0x01010101;
+ break;
+ case 1:
+ imm *= 0x00010001;
+ break;
}
if (not)
@@ -543,7 +554,7 @@ private static void EmitTableVectorLookup(ArmEmitterContext context, bool isTbl)
Operand n = GetVec(op.Rn);
Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, mask);
- mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m);
+ mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m);
res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mMask);
}
@@ -557,7 +568,7 @@ private static void EmitTableVectorLookup(ArmEmitterContext context, bool isTbl)
Operand mSubMask = context.AddIntrinsic(Intrinsic.X86Psubb, m, idxMask);
Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, mSubMask, mask);
- mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask);
+ mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask);
Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, ni, mMask);
@@ -566,7 +577,7 @@ private static void EmitTableVectorLookup(ArmEmitterContext context, bool isTbl)
if (!isTbl)
{
- Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L);
+ Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L);
Operand zeroMask = context.VectorZero();
Operand mPosMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, idxMask);
@@ -590,7 +601,7 @@ private static void EmitTableVectorLookup(ArmEmitterContext context, bool isTbl)
{
Operand d = GetVec(op.Rd);
- List args = new List();
+ List args = new();
if (!isTbl)
{
@@ -612,20 +623,36 @@ private static void EmitTableVectorLookup(ArmEmitterContext context, bool isTbl)
{
switch (op.Size)
{
- case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)); break;
- case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)); break;
- case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)); break;
- case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4)); break;
+ case 1:
+ info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1));
+ break;
+ case 2:
+ info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2));
+ break;
+ case 3:
+ info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3));
+ break;
+ case 4:
+ info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4));
+ break;
}
}
else
{
switch (op.Size)
{
- case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1)); break;
- case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)); break;
- case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)); break;
- case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)); break;
+ case 1:
+ info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1));
+ break;
+ case 2:
+ info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2));
+ break;
+ case 3:
+ info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3));
+ break;
+ case 4:
+ info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4));
+ break;
}
}
@@ -644,7 +671,7 @@ private static void EmitVectorTranspose(ArmEmitterContext context, int part)
if (op.Size < 3)
{
long maskE0 = EvenMasks[op.Size];
- long maskE1 = OddMasks [op.Size];
+ long maskE1 = OddMasks[op.Size];
mask = X86GetScalar(context, maskE0);
@@ -691,7 +718,7 @@ private static void EmitVectorTranspose(ArmEmitterContext context, int part)
Operand ne = EmitVectorExtractZx(context, op.Rn, pairIndex + part, op.Size);
Operand me = EmitVectorExtractZx(context, op.Rm, pairIndex + part, op.Size);
- res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
+ res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size);
}
@@ -712,7 +739,7 @@ private static void EmitVectorUnzip(ArmEmitterContext context, int part)
if (op.Size < 3)
{
long maskE0 = EvenMasks[op.Size];
- long maskE1 = OddMasks [op.Size];
+ long maskE1 = OddMasks[op.Size];
mask = X86GetScalar(context, maskE0);
@@ -784,7 +811,7 @@ private static void EmitVectorUnzip(ArmEmitterContext context, int part)
Operand ne = EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
Operand me = EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
- res = EmitVectorInsert(context, res, ne, index, op.Size);
+ res = EmitVectorInsert(context, res, ne, index, op.Size);
res = EmitVectorInsert(context, res, me, pairs + index, op.Size);
}
@@ -839,7 +866,7 @@ private static void EmitVectorZip(ArmEmitterContext context, int part)
Operand ne = EmitVectorExtractZx(context, op.Rn, baseIndex + index, op.Size);
Operand me = EmitVectorExtractZx(context, op.Rm, baseIndex + index, op.Size);
- res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
+ res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size);
}
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs b/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs
index b8b91b31d..9fa740997 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs
@@ -1,8 +1,7 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
@@ -17,13 +16,13 @@ static partial class InstEmit32
private static readonly long[] _masksE0_Uzp = new long[]
{
13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0,
- 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0
+ 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0,
};
private static readonly long[] _masksE1_Uzp = new long[]
{
15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0,
- 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0
+ 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0,
};
#endregion
@@ -220,7 +219,7 @@ public static void Vtbl(ArmEmitterContext context)
for (int index = 1; index < length; index++)
{
int newVn = (op.Vn + index) & 0x1F;
- (int qn, int ind) = GetQuadwordAndSubindex(newVn, op.RegisterSize);
+ (int qn, _) = GetQuadwordAndSubindex(newVn, op.RegisterSize);
Operand ni = EmitMoveDoubleWordToSide(context, GetVecA32(qn), newVn, 0);
Operand idxMask = X86GetAllElements(context, 0x0808080808080808L * index);
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdShift.cs b/src/ARMeilleure/Instructions/InstEmitSimdShift.cs
index 19e41119b..be0670645 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdShift.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdShift.cs
@@ -6,7 +6,6 @@
using System;
using System.Diagnostics;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -17,12 +16,12 @@ namespace ARMeilleure.Instructions
static partial class InstEmit
{
-#region "Masks"
+ #region "Masks"
private static readonly long[] _masks_SliSri = new long[] // Replication masks.
{
- 0x0101010101010101L, 0x0001000100010001L, 0x0000000100000001L, 0x0000000000000001L
+ 0x0101010101010101L, 0x0001000100010001L, 0x0000000100000001L, 0x0000000000000001L,
};
-#endregion
+ #endregion
public static void Rshrn_V(ArmEmitterContext context)
{
@@ -51,9 +50,15 @@ public static void Rshrn_V(ArmEmitterContext context)
switch (op.Size + 1)
{
- case 1: mask = X86GetAllElements(context, (int)roundConst * 0x00010001); break;
- case 2: mask = X86GetAllElements(context, (int)roundConst); break;
- case 3: mask = X86GetAllElements(context, roundConst); break;
+ case 1:
+ mask = X86GetAllElements(context, (int)roundConst * 0x00010001);
+ break;
+ case 2:
+ mask = X86GetAllElements(context, (int)roundConst);
+ break;
+ case 3:
+ mask = X86GetAllElements(context, roundConst);
+ break;
}
Intrinsic addInst = X86PaddInstruction[op.Size + 1];
@@ -1174,14 +1179,14 @@ private enum ShrImmFlags
Scalar = 1 << 0,
Signed = 1 << 1,
- Round = 1 << 2,
+ Round = 1 << 2,
Accumulate = 1 << 3,
ScalarSx = Scalar | Signed,
ScalarZx = Scalar,
VectorSx = Signed,
- VectorZx = 0
+ VectorZx = 0,
}
private static void EmitScalarShrImmOpSx(ArmEmitterContext context, ShrImmFlags flags)
@@ -1210,9 +1215,9 @@ private static void EmitShrImmOp(ArmEmitterContext context, ShrImmFlags flags)
Operand res = context.VectorZero();
- bool scalar = (flags & ShrImmFlags.Scalar) != 0;
- bool signed = (flags & ShrImmFlags.Signed) != 0;
- bool round = (flags & ShrImmFlags.Round) != 0;
+ bool scalar = (flags & ShrImmFlags.Scalar) != 0;
+ bool signed = (flags & ShrImmFlags.Signed) != 0;
+ bool round = (flags & ShrImmFlags.Round) != 0;
bool accumulate = (flags & ShrImmFlags.Accumulate) != 0;
int shift = GetImmShr(op);
@@ -1288,7 +1293,7 @@ private static void EmitVectorShrImmNarrowOpZx(ArmEmitterContext context, bool r
[Flags]
private enum ShrImmSaturatingNarrowFlags
{
- Scalar = 1 << 0,
+ Scalar = 1 << 0,
SignedSrc = 1 << 1,
SignedDst = 1 << 2,
@@ -1300,7 +1305,7 @@ private enum ShrImmSaturatingNarrowFlags
VectorSxSx = SignedSrc | SignedDst,
VectorSxZx = SignedSrc,
- VectorZxZx = 0
+ VectorZxZx = 0,
}
private static void EmitRoundShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrImmSaturatingNarrowFlags flags)
@@ -1312,10 +1317,10 @@ private static void EmitShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrI
{
OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
- bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
+ bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0;
bool signedDst = (flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0;
- bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0;
+ bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0;
int shift = GetImmShr(op);
@@ -1585,7 +1590,7 @@ private enum ShlRegFlags
Scalar = 1 << 0,
Signed = 1 << 1,
Round = 1 << 2,
- Saturating = 1 << 3
+ Saturating = 1 << 3,
}
private static void EmitShlRegOp(ArmEmitterContext context, ShlRegFlags flags = ShlRegFlags.None)
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs b/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs
index 9ac680884..e40600a47 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs
@@ -1,11 +1,10 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
using System.Diagnostics;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
@@ -291,7 +290,7 @@ private enum ShrImmSaturatingNarrowFlags
VectorSxSx = SignedSrc | SignedDst,
VectorSxZx = SignedSrc,
- VectorZxZx = 0
+ VectorZxZx = 0,
}
private static void EmitRoundShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrImmSaturatingNarrowFlags flags)
@@ -303,10 +302,10 @@ private static void EmitShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrI
{
OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
- bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
+ bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0;
bool signedDst = (flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0;
- bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0;
+ bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0;
if (scalar)
{
diff --git a/src/ARMeilleure/Instructions/InstEmitSystem.cs b/src/ARMeilleure/Instructions/InstEmitSystem.cs
index f84829aa1..8c430fc23 100644
--- a/src/ARMeilleure/Instructions/InstEmitSystem.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSystem.cs
@@ -28,18 +28,39 @@ public static void Mrs(ArmEmitterContext context)
switch (GetPackedId(op))
{
- case 0b11_011_0000_0000_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0)); break;
- case 0b11_011_0000_0000_111: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0)); break;
- case 0b11_011_0100_0010_000: EmitGetNzcv(context); return;
- case 0b11_011_0100_0100_000: EmitGetFpcr(context); return;
- case 0b11_011_0100_0100_001: EmitGetFpsr(context); return;
- case 0b11_011_1101_0000_010: EmitGetTpidrEl0(context); return;
- case 0b11_011_1101_0000_011: EmitGetTpidrroEl0(context); return;
- case 0b11_011_1110_0000_000: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntfrqEl0)); break;
- case 0b11_011_1110_0000_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break;
- case 0b11_011_1110_0000_010: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntvctEl0)); break;
-
- default: throw new NotImplementedException($"Unknown MRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
+ case 0b11_011_0000_0000_001:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0));
+ break;
+ case 0b11_011_0000_0000_111:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0));
+ break;
+ case 0b11_011_0100_0010_000:
+ EmitGetNzcv(context);
+ return;
+ case 0b11_011_0100_0100_000:
+ EmitGetFpcr(context);
+ return;
+ case 0b11_011_0100_0100_001:
+ EmitGetFpsr(context);
+ return;
+ case 0b11_011_1101_0000_010:
+ EmitGetTpidrEl0(context);
+ return;
+ case 0b11_011_1101_0000_011:
+ EmitGetTpidrroEl0(context);
+ return;
+ case 0b11_011_1110_0000_000:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntfrqEl0));
+ break;
+ case 0b11_011_1110_0000_001:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0));
+ break;
+ case 0b11_011_1110_0000_010:
+ info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntvctEl0));
+ break;
+
+ default:
+ throw new NotImplementedException($"Unknown MRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
}
SetIntOrZR(context, op.Rt, context.Call(info));
@@ -51,12 +72,21 @@ public static void Msr(ArmEmitterContext context)
switch (GetPackedId(op))
{
- case 0b11_011_0100_0010_000: EmitSetNzcv(context); return;
- case 0b11_011_0100_0100_000: EmitSetFpcr(context); return;
- case 0b11_011_0100_0100_001: EmitSetFpsr(context); return;
- case 0b11_011_1101_0000_010: EmitSetTpidrEl0(context); return;
-
- default: throw new NotImplementedException($"Unknown MSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
+ case 0b11_011_0100_0010_000:
+ EmitSetNzcv(context);
+ return;
+ case 0b11_011_0100_0100_000:
+ EmitSetFpcr(context);
+ return;
+ case 0b11_011_0100_0100_001:
+ EmitSetFpsr(context);
+ return;
+ case 0b11_011_1101_0000_010:
+ EmitSetTpidrEl0(context);
+ return;
+
+ default:
+ throw new NotImplementedException($"Unknown MSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
}
}
@@ -75,19 +105,19 @@ public static void Sys(ArmEmitterContext context)
switch (GetPackedId(op))
{
case 0b11_011_0111_0100_001:
- {
- // DC ZVA
- Operand t = GetIntOrZR(context, op.Rt);
-
- for (long offset = 0; offset < DczSizeInBytes; offset += 8)
{
- Operand address = context.Add(t, Const(offset));
+ // DC ZVA
+ Operand t = GetIntOrZR(context, op.Rt);
- InstEmitMemoryHelper.EmitStore(context, address, RegisterConsts.ZeroIndex, 3);
- }
+ for (long offset = 0; offset < DczSizeInBytes; offset += 8)
+ {
+ Operand address = context.Add(t, Const(offset));
- break;
- }
+ InstEmitMemoryHelper.EmitStore(context, address, RegisterConsts.ZeroIndex, 3);
+ }
+
+ break;
+ }
// No-op
case 0b11_011_0111_1110_001: // DC CIVAC
@@ -104,7 +134,7 @@ private static int GetPackedId(OpCodeSystem op)
{
int id;
- id = op.Op2 << 0;
+ id = op.Op2 << 0;
id |= op.CRm << 3;
id |= op.CRn << 7;
id |= op.Op1 << 11;
@@ -188,7 +218,7 @@ private static void EmitSetNzcv(ArmEmitterContext context)
OpCodeSystem op = (OpCodeSystem)context.CurrOp;
Operand nzcv = GetIntOrZR(context, op.Rt);
- nzcv = context.ConvertI64ToI32(nzcv);
+ nzcv = context.ConvertI64ToI32(nzcv);
SetFlag(context, PState.VFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const((int)PState.VFlag)), Const(1)));
SetFlag(context, PState.CFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const((int)PState.CFlag)), Const(1)));
@@ -201,7 +231,7 @@ private static void EmitSetFpcr(ArmEmitterContext context)
OpCodeSystem op = (OpCodeSystem)context.CurrOp;
Operand fpcr = GetIntOrZR(context, op.Rt);
- fpcr = context.ConvertI64ToI32(fpcr);
+ fpcr = context.ConvertI64ToI32(fpcr);
for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++)
{
@@ -221,7 +251,7 @@ private static void EmitSetFpsr(ArmEmitterContext context)
context.ClearQcFlagIfModified();
Operand fpsr = GetIntOrZR(context, op.Rt);
- fpsr = context.ConvertI64ToI32(fpsr);
+ fpsr = context.ConvertI64ToI32(fpsr);
for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++)
{
diff --git a/src/ARMeilleure/Instructions/InstEmitSystem32.cs b/src/ARMeilleure/Instructions/InstEmitSystem32.cs
index f2732c998..74d6169c6 100644
--- a/src/ARMeilleure/Instructions/InstEmitSystem32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSystem32.cs
@@ -1,10 +1,9 @@
-using ARMeilleure.Decoders;
+using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
using System.Reflection;
-
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
@@ -34,7 +33,8 @@ public static void Mcr(ArmEmitterContext context)
switch (op.Opc2)
{
case 2:
- EmitSetTpidrEl0(context); return;
+ EmitSetTpidrEl0(context);
+ return;
default:
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
@@ -83,17 +83,13 @@ public static void Mrc(ArmEmitterContext context)
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
}
- switch (op.Opc2)
+ result = op.Opc2 switch
{
- case 2:
- result = EmitGetTpidrEl0(context); break;
-
- case 3:
- result = EmitGetTpidrroEl0(context); break;
-
- default:
- throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
- }
+ 2 => EmitGetTpidrEl0(context),
+ 3 => EmitGetTpidrroEl0(context),
+ _ => throw new NotImplementedException(
+ $"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."),
+ };
break;
@@ -126,27 +122,16 @@ public static void Mrrc(ArmEmitterContext context)
}
int opc = op.MrrcOp;
-
- MethodInfo info;
-
- switch (op.CRm)
+ MethodInfo info = op.CRm switch
{
- case 14: // Timer.
- switch (opc)
- {
- case 0:
- info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break;
-
- default:
- throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
- }
-
- break;
-
- default:
- throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
- }
-
+ // Timer.
+ 14 => opc switch
+ {
+ 0 => typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)),
+ _ => throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."),
+ },
+ _ => throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}."),
+ };
Operand result = context.Call(info);
SetIntA32(context, op.Rt, context.ConvertI64ToI32(result));
@@ -235,7 +220,8 @@ public static void Vmrs(ArmEmitterContext context)
case 0b0000: // FPSID
throw new NotImplementedException("Supervisor Only");
case 0b0001: // FPSCR
- EmitGetFpscr(context); return;
+ EmitGetFpscr(context);
+ return;
case 0b0101: // MVFR2
throw new NotImplementedException("MVFR2");
case 0b0110: // MVFR1
@@ -258,7 +244,8 @@ public static void Vmsr(ArmEmitterContext context)
case 0b0000: // FPSID
throw new NotImplementedException("Supervisor Only");
case 0b0001: // FPSCR
- EmitSetFpscr(context); return;
+ EmitSetFpscr(context);
+ return;
case 0b0101: // MVFR2
throw new NotImplementedException("MVFR2");
case 0b0110: // MVFR1
diff --git a/src/ARMeilleure/Instructions/InstName.cs b/src/ARMeilleure/Instructions/InstName.cs
index fd71d92e6..32ae38dad 100644
--- a/src/ARMeilleure/Instructions/InstName.cs
+++ b/src/ARMeilleure/Instructions/InstName.cs
@@ -228,6 +228,7 @@ enum InstName
Fmaxnmp_S,
Fmaxnmp_V,
Fmaxnmv_V,
+ Fmaxp_S,
Fmaxp_V,
Fmaxv_V,
Fmin_S,
@@ -237,6 +238,7 @@ enum InstName
Fminnmp_S,
Fminnmp_V,
Fminnmv_V,
+ Fminp_S,
Fminp_V,
Fminv_V,
Fmla_Se,
diff --git a/src/ARMeilleure/Instructions/NativeInterface.cs b/src/ARMeilleure/Instructions/NativeInterface.cs
index 2c35387a6..d1b2e353c 100644
--- a/src/ARMeilleure/Instructions/NativeInterface.cs
+++ b/src/ARMeilleure/Instructions/NativeInterface.cs
@@ -64,12 +64,12 @@ public static void Undefined(ulong address, int opCode)
#region "System registers"
public static ulong GetCtrEl0()
{
- return (ulong)GetContext().CtrEl0;
+ return GetContext().CtrEl0;
}
public static ulong GetDczidEl0()
{
- return (ulong)GetContext().DczidEl0;
+ return GetContext().DczidEl0;
}
public static ulong GetCntfrqEl0()
@@ -192,4 +192,4 @@ public static IMemoryManager GetMemoryManager()
return Context.Memory;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Instructions/SoftFallback.cs b/src/ARMeilleure/Instructions/SoftFallback.cs
index 06d76a67c..c4fe677bf 100644
--- a/src/ARMeilleure/Instructions/SoftFallback.cs
+++ b/src/ARMeilleure/Instructions/SoftFallback.cs
@@ -5,7 +5,7 @@ namespace ARMeilleure.Instructions
{
static class SoftFallback
{
-#region "ShrImm64"
+ #region "ShrImm64"
public static long SignedShrImm64(long value, long roundConst, int shift)
{
if (roundConst == 0L)
@@ -89,12 +89,15 @@ public static ulong UnsignedShrImm64(ulong value, long roundConst, int shift)
}
}
}
-#endregion
+ #endregion
-#region "Saturation"
+ #region "Saturation"
public static int SatF32ToS32(float value)
{
- if (float.IsNaN(value)) return 0;
+ if (float.IsNaN(value))
+ {
+ return 0;
+ }
return value >= int.MaxValue ? int.MaxValue :
value <= int.MinValue ? int.MinValue : (int)value;
@@ -102,7 +105,10 @@ public static int SatF32ToS32(float value)
public static long SatF32ToS64(float value)
{
- if (float.IsNaN(value)) return 0;
+ if (float.IsNaN(value))
+ {
+ return 0;
+ }
return value >= long.MaxValue ? long.MaxValue :
value <= long.MinValue ? long.MinValue : (long)value;
@@ -110,7 +116,10 @@ public static long SatF32ToS64(float value)
public static uint SatF32ToU32(float value)
{
- if (float.IsNaN(value)) return 0;
+ if (float.IsNaN(value))
+ {
+ return 0;
+ }
return value >= uint.MaxValue ? uint.MaxValue :
value <= uint.MinValue ? uint.MinValue : (uint)value;
@@ -118,7 +127,10 @@ public static uint SatF32ToU32(float value)
public static ulong SatF32ToU64(float value)
{
- if (float.IsNaN(value)) return 0;
+ if (float.IsNaN(value))
+ {
+ return 0;
+ }
return value >= ulong.MaxValue ? ulong.MaxValue :
value <= ulong.MinValue ? ulong.MinValue : (ulong)value;
@@ -126,7 +138,10 @@ public static ulong SatF32ToU64(float value)
public static int SatF64ToS32(double value)
{
- if (double.IsNaN(value)) return 0;
+ if (double.IsNaN(value))
+ {
+ return 0;
+ }
return value >= int.MaxValue ? int.MaxValue :
value <= int.MinValue ? int.MinValue : (int)value;
@@ -134,7 +149,10 @@ public static int SatF64ToS32(double value)
public static long SatF64ToS64(double value)
{
- if (double.IsNaN(value)) return 0;
+ if (double.IsNaN(value))
+ {
+ return 0;
+ }
return value >= long.MaxValue ? long.MaxValue :
value <= long.MinValue ? long.MinValue : (long)value;
@@ -142,7 +160,10 @@ public static long SatF64ToS64(double value)
public static uint SatF64ToU32(double value)
{
- if (double.IsNaN(value)) return 0;
+ if (double.IsNaN(value))
+ {
+ return 0;
+ }
return value >= uint.MaxValue ? uint.MaxValue :
value <= uint.MinValue ? uint.MinValue : (uint)value;
@@ -150,14 +171,17 @@ public static uint SatF64ToU32(double value)
public static ulong SatF64ToU64(double value)
{
- if (double.IsNaN(value)) return 0;
+ if (double.IsNaN(value))
+ {
+ return 0;
+ }
return value >= ulong.MaxValue ? ulong.MaxValue :
value <= ulong.MinValue ? ulong.MinValue : (ulong)value;
}
-#endregion
+ #endregion
-#region "Count"
+ #region "Count"
public static ulong CountLeadingSigns(ulong value, int size) // size is 8, 16, 32 or 64 (SIMD&FP or Base Inst.).
{
value ^= value >> 1;
@@ -197,9 +221,9 @@ public static ulong CountLeadingZeros(ulong value, int size) // size is 8, 16, 3
return (ulong)count;
}
-#endregion
+ #endregion
-#region "Table"
+ #region "Table"
public static V128 Tbl1(V128 vector, int bytes, V128 tb0)
{
return TblOrTbx(default, vector, bytes, tb0);
@@ -270,21 +294,21 @@ private static V128 TblOrTbx(V128 dest, V128 vector, int bytes, params V128[] tb
return new V128(res);
}
-#endregion
+ #endregion
-#region "Crc32"
- private const uint Crc32RevPoly = 0xedb88320;
+ #region "Crc32"
+ private const uint Crc32RevPoly = 0xedb88320;
private const uint Crc32cRevPoly = 0x82f63b78;
- public static uint Crc32b(uint crc, byte value) => Crc32 (crc, Crc32RevPoly, value);
+ public static uint Crc32b(uint crc, byte value) => Crc32(crc, Crc32RevPoly, value);
public static uint Crc32h(uint crc, ushort value) => Crc32h(crc, Crc32RevPoly, value);
- public static uint Crc32w(uint crc, uint value) => Crc32w(crc, Crc32RevPoly, value);
- public static uint Crc32x(uint crc, ulong value) => Crc32x(crc, Crc32RevPoly, value);
+ public static uint Crc32w(uint crc, uint value) => Crc32w(crc, Crc32RevPoly, value);
+ public static uint Crc32x(uint crc, ulong value) => Crc32x(crc, Crc32RevPoly, value);
- public static uint Crc32cb(uint crc, byte value) => Crc32 (crc, Crc32cRevPoly, value);
+ public static uint Crc32cb(uint crc, byte value) => Crc32(crc, Crc32cRevPoly, value);
public static uint Crc32ch(uint crc, ushort value) => Crc32h(crc, Crc32cRevPoly, value);
- public static uint Crc32cw(uint crc, uint value) => Crc32w(crc, Crc32cRevPoly, value);
- public static uint Crc32cx(uint crc, ulong value) => Crc32x(crc, Crc32cRevPoly, value);
+ public static uint Crc32cw(uint crc, uint value) => Crc32w(crc, Crc32cRevPoly, value);
+ public static uint Crc32cx(uint crc, ulong value) => Crc32x(crc, Crc32cRevPoly, value);
private static uint Crc32h(uint crc, uint poly, ushort val)
{
@@ -331,9 +355,9 @@ private static uint Crc32(uint crc, uint poly, byte val)
return crc;
}
-#endregion
+ #endregion
-#region "Aes"
+ #region "Aes"
public static V128 Decrypt(V128 value, V128 roundKey)
{
return CryptoHelper.AesInvSubBytes(CryptoHelper.AesInvShiftRows(value ^ roundKey));
@@ -353,9 +377,9 @@ public static V128 MixColumns(V128 value)
{
return CryptoHelper.AesMixColumns(value);
}
-#endregion
+ #endregion
-#region "Sha1"
+ #region "Sha1"
public static V128 HashChoose(V128 hash_abcd, uint hash_e, V128 wk)
{
for (int e = 0; e <= 3; e++)
@@ -426,7 +450,7 @@ public static V128 Sha1SchedulePart1(V128 w0_3, V128 w4_7, V128 w8_11)
ulong t2 = w4_7.Extract(0);
ulong t1 = w0_3.Extract(1);
- V128 result = new V128(t1, t2);
+ V128 result = new(t1, t2);
return result ^ (w0_3 ^ w8_11);
}
@@ -472,9 +496,9 @@ private static uint Rol(this uint value, int count)
{
return (value << count) | (value >> (32 - count));
}
-#endregion
+ #endregion
-#region "Sha256"
+ #region "Sha256"
public static V128 HashLower(V128 hash_abcd, V128 hash_efgh, V128 wk)
{
return Sha256Hash(hash_abcd, hash_efgh, wk, part1: true);
@@ -487,7 +511,7 @@ public static V128 HashUpper(V128 hash_abcd, V128 hash_efgh, V128 wk)
public static V128 Sha256SchedulePart1(V128 w0_3, V128 w4_7)
{
- V128 result = new V128();
+ V128 result = new();
for (int e = 0; e <= 3; e++)
{
@@ -505,7 +529,7 @@ public static V128 Sha256SchedulePart1(V128 w0_3, V128 w4_7)
public static V128 Sha256SchedulePart2(V128 w0_3, V128 w8_11, V128 w12_15)
{
- V128 result = new V128();
+ V128 result = new();
ulong t1 = w12_15.Extract(1);
@@ -602,13 +626,13 @@ private static uint ULongPart(this ulong value, int part)
? (uint)(value & 0xFFFFFFFFUL)
: (uint)(value >> 32);
}
-#endregion
+ #endregion
public static V128 PolynomialMult64_128(ulong op1, ulong op2)
{
V128 result = V128.Zero;
- V128 op2_128 = new V128(op2, 0);
+ V128 op2_128 = new(op2, 0);
for (int i = 0; i < 64; i++)
{
diff --git a/src/ARMeilleure/Instructions/SoftFloat.cs b/src/ARMeilleure/Instructions/SoftFloat.cs
index 9e3db68d9..a67349e6e 100644
--- a/src/ARMeilleure/Instructions/SoftFloat.cs
+++ b/src/ARMeilleure/Instructions/SoftFloat.cs
@@ -8,7 +8,7 @@ static class SoftFloat
{
static SoftFloat()
{
- RecipEstimateTable = BuildRecipEstimateTable();
+ RecipEstimateTable = BuildRecipEstimateTable();
RecipSqrtEstimateTable = BuildRecipSqrtEstimateTable();
}
@@ -63,7 +63,7 @@ private static byte[] BuildRecipSqrtEstimateTable()
while (src * (aux + 1u) * (aux + 1u) < (1u << 28))
{
- aux = aux + 1u;
+ aux++;
}
uint dst = (aux + 1u) >> 1;
@@ -133,8 +133,8 @@ public static double FPUnpackCv(
{
sign = (~(uint)valueBits & 0x8000u) == 0u;
- uint exp16 = ((uint)valueBits & 0x7C00u) >> 10;
- uint frac16 = (uint)valueBits & 0x03FFu;
+ uint exp16 = ((uint)valueBits & 0x7C00u) >> 10;
+ uint frac16 = (uint)valueBits & 0x03FFu;
double real;
@@ -175,22 +175,22 @@ public static double FPUnpackCv(
public static ushort FPRoundCv(double real, ExecutionContext context)
{
- const int minimumExp = -14;
+ const int MinimumExp = -14;
- const int e = 5;
- const int f = 10;
+ const int E = 5;
+ const int F = 10;
- bool sign;
+ bool sign;
double mantissa;
if (real < 0d)
{
- sign = true;
+ sign = true;
mantissa = -real;
}
else
{
- sign = false;
+ sign = false;
mantissa = real;
}
@@ -208,15 +208,15 @@ public static ushort FPRoundCv(double real, ExecutionContext context)
exponent++;
}
- uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0);
+ uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0);
if (biasedExp == 0u)
{
- mantissa /= Math.Pow(2d, minimumExp - exponent);
+ mantissa /= Math.Pow(2d, MinimumExp - exponent);
}
- uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f));
- double error = mantissa * Math.Pow(2d, f) - (double)intMant;
+ uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, F));
+ double error = mantissa * Math.Pow(2d, F) - (double)intMant;
if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0))
{
@@ -228,38 +228,40 @@ public static ushort FPRoundCv(double real, ExecutionContext context)
switch (context.Fpcr.GetRoundingMode())
{
- default:
case FPRoundingMode.ToNearest:
- roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u));
+ roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u));
overflowToInf = true;
break;
case FPRoundingMode.TowardsPlusInfinity:
- roundUp = (error != 0d && !sign);
+ roundUp = (error != 0d && !sign);
overflowToInf = !sign;
break;
case FPRoundingMode.TowardsMinusInfinity:
- roundUp = (error != 0d && sign);
+ roundUp = (error != 0d && sign);
overflowToInf = sign;
break;
case FPRoundingMode.TowardsZero:
- roundUp = false;
+ roundUp = false;
overflowToInf = false;
break;
+
+ default:
+ throw new ArgumentException($"Invalid rounding mode \"{context.Fpcr.GetRoundingMode()}\".");
}
if (roundUp)
{
intMant++;
- if (intMant == 1u << f)
+ if (intMant == 1u << F)
{
biasedExp = 1u;
}
- if (intMant == 1u << (f + 1))
+ if (intMant == 1u << (F + 1))
{
biasedExp++;
intMant >>= 1;
@@ -270,7 +272,7 @@ public static ushort FPRoundCv(double real, ExecutionContext context)
if ((context.Fpcr & FPCR.Ahp) == 0)
{
- if (biasedExp >= (1u << e) - 1u)
+ if (biasedExp >= (1u << E) - 1u)
{
resultBits = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign);
@@ -285,7 +287,7 @@ public static ushort FPRoundCv(double real, ExecutionContext context)
}
else
{
- if (biasedExp >= 1u << e)
+ if (biasedExp >= 1u << E)
{
resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu);
@@ -352,22 +354,22 @@ public static float FPConvert(ushort valueBits)
private static float FPRoundCv(double real, ExecutionContext context)
{
- const int minimumExp = -126;
+ const int MinimumExp = -126;
- const int e = 8;
- const int f = 23;
+ const int E = 8;
+ const int F = 23;
- bool sign;
+ bool sign;
double mantissa;
if (real < 0d)
{
- sign = true;
+ sign = true;
mantissa = -real;
}
else
{
- sign = false;
+ sign = false;
mantissa = real;
}
@@ -385,22 +387,22 @@ private static float FPRoundCv(double real, ExecutionContext context)
exponent++;
}
- if ((context.Fpcr & FPCR.Fz) != 0 && exponent < minimumExp)
+ if ((context.Fpcr & FPCR.Fz) != 0 && exponent < MinimumExp)
{
context.Fpsr |= FPSR.Ufc;
return SoftFloat32.FPZero(sign);
}
- uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0);
+ uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0);
if (biasedExp == 0u)
{
- mantissa /= Math.Pow(2d, minimumExp - exponent);
+ mantissa /= Math.Pow(2d, MinimumExp - exponent);
}
- uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f));
- double error = mantissa * Math.Pow(2d, f) - (double)intMant;
+ uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, F));
+ double error = mantissa * Math.Pow(2d, F) - (double)intMant;
if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0))
{
@@ -412,38 +414,40 @@ private static float FPRoundCv(double real, ExecutionContext context)
switch (context.Fpcr.GetRoundingMode())
{
- default:
case FPRoundingMode.ToNearest:
- roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u));
+ roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u));
overflowToInf = true;
break;
case FPRoundingMode.TowardsPlusInfinity:
- roundUp = (error != 0d && !sign);
+ roundUp = (error != 0d && !sign);
overflowToInf = !sign;
break;
case FPRoundingMode.TowardsMinusInfinity:
- roundUp = (error != 0d && sign);
+ roundUp = (error != 0d && sign);
overflowToInf = sign;
break;
case FPRoundingMode.TowardsZero:
- roundUp = false;
+ roundUp = false;
overflowToInf = false;
break;
+
+ default:
+ throw new ArgumentException($"Invalid rounding mode \"{context.Fpcr.GetRoundingMode()}\".");
}
if (roundUp)
{
intMant++;
- if (intMant == 1u << f)
+ if (intMant == 1u << F)
{
biasedExp = 1u;
}
- if (intMant == 1u << (f + 1))
+ if (intMant == 1u << (F + 1))
{
biasedExp++;
intMant >>= 1;
@@ -452,7 +456,7 @@ private static float FPRoundCv(double real, ExecutionContext context)
float result;
- if (biasedExp >= (1u << e) - 1u)
+ if (biasedExp >= (1u << E) - 1u)
{
result = overflowToInf ? SoftFloat32.FPInfinity(sign) : SoftFloat32.FPMaxNormal(sign);
@@ -525,22 +529,22 @@ public static double FPConvert(ushort valueBits)
private static double FPRoundCv(double real, ExecutionContext context)
{
- const int minimumExp = -1022;
+ const int MinimumExp = -1022;
- const int e = 11;
- const int f = 52;
+ const int E = 11;
+ const int F = 52;
- bool sign;
+ bool sign;
double mantissa;
if (real < 0d)
{
- sign = true;
+ sign = true;
mantissa = -real;
}
else
{
- sign = false;
+ sign = false;
mantissa = real;
}
@@ -558,22 +562,22 @@ private static double FPRoundCv(double real, ExecutionContext context)
exponent++;
}
- if ((context.Fpcr & FPCR.Fz) != 0 && exponent < minimumExp)
+ if ((context.Fpcr & FPCR.Fz) != 0 && exponent < MinimumExp)
{
context.Fpsr |= FPSR.Ufc;
return SoftFloat64.FPZero(sign);
}
- uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0);
+ uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0);
if (biasedExp == 0u)
{
- mantissa /= Math.Pow(2d, minimumExp - exponent);
+ mantissa /= Math.Pow(2d, MinimumExp - exponent);
}
- ulong intMant = (ulong)Math.Floor(mantissa * Math.Pow(2d, f));
- double error = mantissa * Math.Pow(2d, f) - (double)intMant;
+ ulong intMant = (ulong)Math.Floor(mantissa * Math.Pow(2d, F));
+ double error = mantissa * Math.Pow(2d, F) - (double)intMant;
if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0))
{
@@ -585,38 +589,40 @@ private static double FPRoundCv(double real, ExecutionContext context)
switch (context.Fpcr.GetRoundingMode())
{
- default:
case FPRoundingMode.ToNearest:
- roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u));
+ roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u));
overflowToInf = true;
break;
case FPRoundingMode.TowardsPlusInfinity:
- roundUp = (error != 0d && !sign);
+ roundUp = (error != 0d && !sign);
overflowToInf = !sign;
break;
case FPRoundingMode.TowardsMinusInfinity:
- roundUp = (error != 0d && sign);
+ roundUp = (error != 0d && sign);
overflowToInf = sign;
break;
case FPRoundingMode.TowardsZero:
- roundUp = false;
+ roundUp = false;
overflowToInf = false;
break;
+
+ default:
+ throw new ArgumentException($"Invalid rounding mode \"{context.Fpcr.GetRoundingMode()}\".");
}
if (roundUp)
{
intMant++;
- if (intMant == 1ul << f)
+ if (intMant == 1ul << F)
{
biasedExp = 1u;
}
- if (intMant == 1ul << (f + 1))
+ if (intMant == 1ul << (F + 1))
{
biasedExp++;
intMant >>= 1;
@@ -625,7 +631,7 @@ private static double FPRoundCv(double real, ExecutionContext context)
double result;
- if (biasedExp >= (1u << e) - 1u)
+ if (biasedExp >= (1u << E) - 1u)
{
result = overflowToInf ? SoftFloat64.FPInfinity(sign) : SoftFloat64.FPMaxNormal(sign);
@@ -722,8 +728,8 @@ private static double FPUnpackCv(
sign = (~valueBits & 0x80000000u) == 0u;
- uint exp32 = (valueBits & 0x7F800000u) >> 23;
- uint frac32 = valueBits & 0x007FFFFFu;
+ uint exp32 = (valueBits & 0x7F800000u) >> 23;
+ uint frac32 = valueBits & 0x007FFFFFu;
double real;
@@ -792,8 +798,10 @@ public static float FPAddFpscr(float value1, float value2, bool standardFpscr)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if (inf1 && inf2 && sign1 == !sign2)
{
@@ -834,8 +842,8 @@ public static int FPCompare(float value1, float value2, bool signalNaNs)
ExecutionContext context = NativeInterface.GetContext();
FPCR fpcr = context.Fpcr;
- value1 = value1.FPUnpack(out FPType type1, out bool sign1, out _, context, fpcr);
- value2 = value2.FPUnpack(out FPType type2, out bool sign2, out _, context, fpcr);
+ value1 = value1.FPUnpack(out FPType type1, out _, out _, context, fpcr);
+ value2 = value2.FPUnpack(out FPType type2, out _, out _, context, fpcr);
int result;
@@ -989,8 +997,10 @@ public static float FPDiv(float value1, float value2)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && inf2) || (zero1 && zero2))
{
@@ -1226,8 +1236,10 @@ public static float FPMulFpscr(float value1, float value2, bool standardFpscr)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && zero2) || (zero1 && inf2))
{
@@ -1270,11 +1282,13 @@ public static float FPMulAddFpscr(float valueA, float value1, float value2, bool
FPCR fpcr = standardFpscr ? context.StandardFpcrValue : context.Fpcr;
valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out uint addend, context, fpcr);
- value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr);
- value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr);
+ value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr);
+ value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr);
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
float result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, out bool done, context, fpcr);
@@ -1287,10 +1301,11 @@ public static float FPMulAddFpscr(float valueA, float value1, float value2, bool
if (!done)
{
- bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero;
+ bool infA = typeA == FPType.Infinity;
+ bool zeroA = typeA == FPType.Zero;
- bool signP = sign1 ^ sign2;
- bool infP = inf1 || inf2;
+ bool signP = sign1 ^ sign2;
+ bool infP = inf1 || inf2;
bool zeroP = zero1 || zero2;
if ((inf1 && zero2) || (zero1 && inf2) || (infA && infP && signA != signP))
@@ -1353,8 +1368,10 @@ public static float FPMulX(float value1, float value2)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && zero2) || (zero1 && inf2))
{
@@ -1429,21 +1446,18 @@ public static float FPRecipEstimateFpscr(float value, bool standardFpscr)
}
else if (MathF.Abs(value) < MathF.Pow(2f, -128))
{
- bool overflowToInf;
-
- switch (fpcr.GetRoundingMode())
+ var overflowToInf = fpcr.GetRoundingMode() switch
{
- default:
- case FPRoundingMode.ToNearest: overflowToInf = true; break;
- case FPRoundingMode.TowardsPlusInfinity: overflowToInf = !sign; break;
- case FPRoundingMode.TowardsMinusInfinity: overflowToInf = sign; break;
- case FPRoundingMode.TowardsZero: overflowToInf = false; break;
- }
-
+ FPRoundingMode.ToNearest => true,
+ FPRoundingMode.TowardsPlusInfinity => !sign,
+ FPRoundingMode.TowardsMinusInfinity => sign,
+ FPRoundingMode.TowardsZero => false,
+ _ => throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."),
+ };
result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign);
SoftFloat.FPProcessException(FPException.Overflow, context, fpcr);
- SoftFloat.FPProcessException(FPException.Inexact, context, fpcr);
+ SoftFloat.FPProcessException(FPException.Inexact, context, fpcr);
}
else if ((fpcr & FPCR.Fz) != 0 && (MathF.Abs(value) >= MathF.Pow(2f, 126)))
{
@@ -1499,15 +1513,17 @@ public static float FPRecipStep(float value1, float value2)
ExecutionContext context = NativeInterface.GetContext();
FPCR fpcr = context.StandardFpcrValue;
- value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr);
- value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr);
+ value1 = value1.FPUnpack(out FPType type1, out _, out uint op1, context, fpcr);
+ value2 = value2.FPUnpack(out FPType type2, out _, out uint op2, context, fpcr);
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr);
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
float product;
@@ -1540,8 +1556,10 @@ public static float FPRecipStepFused(float value1, float value2)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && zero2) || (zero1 && inf2))
{
@@ -1672,8 +1690,10 @@ public static float FPHalvedSub(float value1, float value2, ExecutionContext con
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if (inf1 && inf2 && sign1 == sign2)
{
@@ -1714,15 +1734,17 @@ public static float FPRSqrtStep(float value1, float value2)
ExecutionContext context = NativeInterface.GetContext();
FPCR fpcr = context.StandardFpcrValue;
- value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr);
- value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr);
+ value1 = value1.FPUnpack(out FPType type1, out _, out uint op1, context, fpcr);
+ value2 = value2.FPUnpack(out FPType type2, out _, out uint op2, context, fpcr);
float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr);
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
float product;
@@ -1755,8 +1777,10 @@ public static float FPRSqrtStepFused(float value1, float value2)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && zero2) || (zero1 && inf2))
{
@@ -1841,8 +1865,10 @@ public static float FPSubFpscr(float value1, float value2, bool standardFpscr)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if (inf1 && inf2 && sign1 == sign2)
{
@@ -1939,7 +1965,7 @@ private static float FPUnpack(
{
if ((valueBits & 0x007FFFFFu) == 0u || (fpcr & FPCR.Fz) != 0)
{
- type = FPType.Zero;
+ type = FPType.Zero;
value = FPZero(sign);
if ((valueBits & 0x007FFFFFu) != 0u)
@@ -1960,7 +1986,7 @@ private static float FPUnpack(
}
else
{
- type = (~valueBits & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN;
+ type = (~valueBits & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN;
value = FPZero(sign);
}
}
@@ -2134,8 +2160,8 @@ private static double FPUnpackCv(
sign = (~valueBits & 0x8000000000000000ul) == 0u;
- ulong exp64 = (valueBits & 0x7FF0000000000000ul) >> 52;
- ulong frac64 = valueBits & 0x000FFFFFFFFFFFFFul;
+ ulong exp64 = (valueBits & 0x7FF0000000000000ul) >> 52;
+ ulong frac64 = valueBits & 0x000FFFFFFFFFFFFFul;
double real;
@@ -2204,8 +2230,10 @@ public static double FPAddFpscr(double value1, double value2, bool standardFpscr
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if (inf1 && inf2 && sign1 == !sign2)
{
@@ -2246,8 +2274,8 @@ public static int FPCompare(double value1, double value2, bool signalNaNs)
ExecutionContext context = NativeInterface.GetContext();
FPCR fpcr = context.Fpcr;
- value1 = value1.FPUnpack(out FPType type1, out bool sign1, out _, context, fpcr);
- value2 = value2.FPUnpack(out FPType type2, out bool sign2, out _, context, fpcr);
+ value1 = value1.FPUnpack(out FPType type1, out _, out _, context, fpcr);
+ value2 = value2.FPUnpack(out FPType type2, out _, out _, context, fpcr);
int result;
@@ -2401,8 +2429,10 @@ public static double FPDiv(double value1, double value2)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && inf2) || (zero1 && zero2))
{
@@ -2638,8 +2668,10 @@ public static double FPMulFpscr(double value1, double value2, bool standardFpscr
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && zero2) || (zero1 && inf2))
{
@@ -2682,11 +2714,13 @@ public static double FPMulAddFpscr(double valueA, double value1, double value2,
FPCR fpcr = standardFpscr ? context.StandardFpcrValue : context.Fpcr;
valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out ulong addend, context, fpcr);
- value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr);
- value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr);
+ value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr);
+ value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr);
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
double result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, out bool done, context, fpcr);
@@ -2699,10 +2733,11 @@ public static double FPMulAddFpscr(double valueA, double value1, double value2,
if (!done)
{
- bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero;
+ bool infA = typeA == FPType.Infinity;
+ bool zeroA = typeA == FPType.Zero;
- bool signP = sign1 ^ sign2;
- bool infP = inf1 || inf2;
+ bool signP = sign1 ^ sign2;
+ bool infP = inf1 || inf2;
bool zeroP = zero1 || zero2;
if ((inf1 && zero2) || (zero1 && inf2) || (infA && infP && signA != signP))
@@ -2765,8 +2800,10 @@ public static double FPMulX(double value1, double value2)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && zero2) || (zero1 && inf2))
{
@@ -2841,21 +2878,18 @@ public static double FPRecipEstimateFpscr(double value, bool standardFpscr)
}
else if (Math.Abs(value) < Math.Pow(2d, -1024))
{
- bool overflowToInf;
-
- switch (fpcr.GetRoundingMode())
+ var overflowToInf = fpcr.GetRoundingMode() switch
{
- default:
- case FPRoundingMode.ToNearest: overflowToInf = true; break;
- case FPRoundingMode.TowardsPlusInfinity: overflowToInf = !sign; break;
- case FPRoundingMode.TowardsMinusInfinity: overflowToInf = sign; break;
- case FPRoundingMode.TowardsZero: overflowToInf = false; break;
- }
-
+ FPRoundingMode.ToNearest => true,
+ FPRoundingMode.TowardsPlusInfinity => !sign,
+ FPRoundingMode.TowardsMinusInfinity => sign,
+ FPRoundingMode.TowardsZero => false,
+ _ => throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."),
+ };
result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign);
SoftFloat.FPProcessException(FPException.Overflow, context, fpcr);
- SoftFloat.FPProcessException(FPException.Inexact, context, fpcr);
+ SoftFloat.FPProcessException(FPException.Inexact, context, fpcr);
}
else if ((fpcr & FPCR.Fz) != 0 && (Math.Abs(value) >= Math.Pow(2d, 1022)))
{
@@ -2911,15 +2945,17 @@ public static double FPRecipStep(double value1, double value2)
ExecutionContext context = NativeInterface.GetContext();
FPCR fpcr = context.StandardFpcrValue;
- value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr);
- value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr);
+ value1 = value1.FPUnpack(out FPType type1, out _, out ulong op1, context, fpcr);
+ value2 = value2.FPUnpack(out FPType type2, out _, out ulong op2, context, fpcr);
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr);
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
double product;
@@ -2952,8 +2988,10 @@ public static double FPRecipStepFused(double value1, double value2)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && zero2) || (zero1 && inf2))
{
@@ -3084,8 +3122,10 @@ public static double FPHalvedSub(double value1, double value2, ExecutionContext
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if (inf1 && inf2 && sign1 == sign2)
{
@@ -3126,15 +3166,17 @@ public static double FPRSqrtStep(double value1, double value2)
ExecutionContext context = NativeInterface.GetContext();
FPCR fpcr = context.StandardFpcrValue;
- value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr);
- value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr);
+ value1 = value1.FPUnpack(out FPType type1, out _, out ulong op1, context, fpcr);
+ value2 = value2.FPUnpack(out FPType type2, out _, out ulong op2, context, fpcr);
double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr);
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
double product;
@@ -3167,8 +3209,10 @@ public static double FPRSqrtStepFused(double value1, double value2)
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if ((inf1 && zero2) || (zero1 && inf2))
{
@@ -3253,8 +3297,10 @@ public static double FPSubFpscr(double value1, double value2, bool standardFpscr
if (!done)
{
- bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero;
- bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero;
+ bool inf1 = type1 == FPType.Infinity;
+ bool zero1 = type1 == FPType.Zero;
+ bool inf2 = type2 == FPType.Infinity;
+ bool zero2 = type2 == FPType.Zero;
if (inf1 && inf2 && sign1 == sign2)
{
@@ -3351,7 +3397,7 @@ private static double FPUnpack(
{
if ((valueBits & 0x000FFFFFFFFFFFFFul) == 0ul || (fpcr & FPCR.Fz) != 0)
{
- type = FPType.Zero;
+ type = FPType.Zero;
value = FPZero(sign);
if ((valueBits & 0x000FFFFFFFFFFFFFul) != 0ul)
@@ -3372,7 +3418,7 @@ private static double FPUnpack(
}
else
{
- type = (~valueBits & 0x0008000000000000ul) == 0ul ? FPType.QNaN : FPType.SNaN;
+ type = (~valueBits & 0x0008000000000000ul) == 0ul ? FPType.QNaN : FPType.SNaN;
value = FPZero(sign);
}
}
diff --git a/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs b/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs
index 07bd8b672..810461d7c 100644
--- a/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs
@@ -10,7 +10,7 @@ class BasicBlock : IEquatable, IIntrusiveListNode
private int _succCount;
private BasicBlock _succ0;
- private BasicBlock _succ1;
+ private readonly BasicBlock _succ1;
private HashSet _domFrontiers;
public int Index { get; set; }
@@ -27,10 +27,7 @@ public HashSet DominanceFrontiers
{
get
{
- if (_domFrontiers == null)
- {
- _domFrontiers = new HashSet();
- }
+ _domFrontiers ??= new HashSet();
return _domFrontiers;
}
@@ -108,7 +105,7 @@ public void SetSuccessor(int index, BasicBlock block)
oldBlock.Predecessors.Remove(this);
block.Predecessors.Add(this);
-
+
oldBlock = block;
}
@@ -156,4 +153,4 @@ public override int GetHashCode()
return base.GetHashCode();
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs b/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs
index 96cfee35a..e4f7ae809 100644
--- a/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs
@@ -1,8 +1,8 @@
-namespace ARMeilleure.IntermediateRepresentation
+namespace ARMeilleure.IntermediateRepresentation
{
enum BasicBlockFrequency
{
Default,
- Cold
+ Cold,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/Comparison.cs b/src/ARMeilleure/IntermediateRepresentation/Comparison.cs
index 628ce1051..3d6a9d818 100644
--- a/src/ARMeilleure/IntermediateRepresentation/Comparison.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/Comparison.cs
@@ -1,17 +1,17 @@
-namespace ARMeilleure.IntermediateRepresentation
+namespace ARMeilleure.IntermediateRepresentation
{
enum Comparison
{
- Equal = 0,
- NotEqual = 1,
- Greater = 2,
- LessOrEqual = 3,
- GreaterUI = 4,
- LessOrEqualUI = 5,
- GreaterOrEqual = 6,
- Less = 7,
- GreaterOrEqualUI = 8,
- LessUI = 9
+ Equal = 0,
+ NotEqual = 1,
+ Greater = 2,
+ LessOrEqual = 3,
+ GreaterUI = 4,
+ LessOrEqualUI = 5,
+ GreaterOrEqual = 6,
+ Less = 7,
+ GreaterOrEqualUI = 8,
+ LessUI = 9,
}
static class ComparisonExtensions
diff --git a/src/ARMeilleure/IntermediateRepresentation/IIntrusiveListNode.cs b/src/ARMeilleure/IntermediateRepresentation/IIntrusiveListNode.cs
index caa9b83fe..05be8a5ae 100644
--- a/src/ARMeilleure/IntermediateRepresentation/IIntrusiveListNode.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/IIntrusiveListNode.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.IntermediateRepresentation
+namespace ARMeilleure.IntermediateRepresentation
{
interface IIntrusiveListNode
{
diff --git a/src/ARMeilleure/IntermediateRepresentation/Instruction.cs b/src/ARMeilleure/IntermediateRepresentation/Instruction.cs
index b55fe1dac..9bae8d1fb 100644
--- a/src/ARMeilleure/IntermediateRepresentation/Instruction.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/Instruction.cs
@@ -67,6 +67,6 @@ enum Instruction : ushort
Phi,
Spill,
SpillArg,
- StoreToContext
+ StoreToContext,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs b/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs
index f5a776fa2..b9cab6674 100644
--- a/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs
@@ -1,5 +1,10 @@
+using System;
+using System.Diagnostics.CodeAnalysis;
+
namespace ARMeilleure.IntermediateRepresentation
{
+ [Flags]
+ [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
enum Intrinsic : ushort
{
// X86 (SSE and AVX)
@@ -631,6 +636,6 @@ enum Intrinsic : ushort
Arm64VByte = 0 << Arm64VSizeShift,
Arm64VHWord = 1 << Arm64VSizeShift,
Arm64VWord = 2 << Arm64VSizeShift,
- Arm64VDWord = 3 << Arm64VSizeShift
+ Arm64VDWord = 3 << Arm64VSizeShift,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/IntrusiveList.cs b/src/ARMeilleure/IntermediateRepresentation/IntrusiveList.cs
index 184df87c8..8d300075d 100644
--- a/src/ARMeilleure/IntermediateRepresentation/IntrusiveList.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/IntrusiveList.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
using System.Collections.Generic;
using System.Diagnostics;
using System.Runtime.CompilerServices;
diff --git a/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs b/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs
index 07d2633b4..9b3df8ca4 100644
--- a/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs
@@ -4,11 +4,11 @@
namespace ARMeilleure.IntermediateRepresentation
{
- unsafe struct MemoryOperand
+ readonly unsafe struct MemoryOperand
{
private struct Data
{
-#pragma warning disable CS0649
+#pragma warning disable CS0649 // Field is never assigned to
public byte Kind;
public byte Type;
#pragma warning restore CS0649
@@ -18,7 +18,7 @@ private struct Data
public int Displacement;
}
- private Data* _data;
+ private readonly Data* _data;
public MemoryOperand(Operand operand)
{
@@ -30,13 +30,13 @@ public MemoryOperand(Operand operand)
public Operand BaseAddress
{
get => _data->BaseAddress;
- set => _data->BaseAddress = value;
+ set => _data->BaseAddress = value;
}
public Operand Index
{
get => _data->Index;
- set => _data->Index = value;
+ set => _data->Index = value;
}
public Multiplier Scale
@@ -51,4 +51,4 @@ public int Displacement
set => _data->Displacement = value;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs b/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs
index d6bc7d994..6bcdda014 100644
--- a/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs
@@ -6,6 +6,6 @@ enum Multiplier
x2 = 1,
x4 = 2,
x8 = 3,
- x16 = 4
+ x16 = 4,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/Operand.cs b/src/ARMeilleure/IntermediateRepresentation/Operand.cs
index 9e8de3ba4..89aefacb1 100644
--- a/src/ARMeilleure/IntermediateRepresentation/Operand.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/Operand.cs
@@ -27,25 +27,25 @@ internal struct Data
private Data* _data;
- public OperandKind Kind
+ public readonly OperandKind Kind
{
get => (OperandKind)_data->Kind;
private set => _data->Kind = (byte)value;
}
- public OperandType Type
+ public readonly OperandType Type
{
get => (OperandType)_data->Type;
private set => _data->Type = (byte)value;
}
- public ulong Value
+ public readonly ulong Value
{
get => _data->Value;
private set => _data->Value = value;
}
- public Symbol Symbol
+ public readonly Symbol Symbol
{
get
{
@@ -69,7 +69,7 @@ private set
}
}
- public ReadOnlySpan Assignments
+ public readonly ReadOnlySpan Assignments
{
get
{
@@ -79,7 +79,7 @@ public ReadOnlySpan Assignments
}
}
- public ReadOnlySpan Uses
+ public readonly ReadOnlySpan Uses
{
get
{
@@ -89,13 +89,13 @@ public ReadOnlySpan Uses
}
}
- public int UsesCount => (int)_data->UsesCount;
- public int AssignmentsCount => _data->AssignmentsCount;
+ public readonly int UsesCount => (int)_data->UsesCount;
+ public readonly int AssignmentsCount => _data->AssignmentsCount;
- public bool Relocatable => Symbol.Type != SymbolType.None;
+ public readonly bool Relocatable => Symbol.Type != SymbolType.None;
[MethodImpl(MethodImplOptions.AggressiveInlining)]
- public Register GetRegister()
+ public readonly Register GetRegister()
{
Debug.Assert(Kind == OperandKind.Register);
@@ -103,52 +103,52 @@ public Register GetRegister()
}
[MethodImpl(MethodImplOptions.AggressiveInlining)]
- public MemoryOperand GetMemory()
+ public readonly MemoryOperand GetMemory()
{
Debug.Assert(Kind == OperandKind.Memory);
return new MemoryOperand(this);
}
- public int GetLocalNumber()
+ public readonly int GetLocalNumber()
{
Debug.Assert(Kind == OperandKind.LocalVariable);
return (int)Value;
}
- public byte AsByte()
+ public readonly byte AsByte()
{
return (byte)Value;
}
- public short AsInt16()
+ public readonly short AsInt16()
{
return (short)Value;
}
- public int AsInt32()
+ public readonly int AsInt32()
{
return (int)Value;
}
- public long AsInt64()
+ public readonly long AsInt64()
{
return (long)Value;
}
- public float AsFloat()
+ public readonly float AsFloat()
{
return BitConverter.Int32BitsToSingle((int)Value);
}
- public double AsDouble()
+ public readonly double AsDouble()
{
return BitConverter.Int64BitsToDouble((long)Value);
}
[MethodImpl(MethodImplOptions.AggressiveInlining)]
- internal ref ulong GetValueUnsafe()
+ internal readonly ref ulong GetValueUnsafe()
{
return ref _data->Value;
}
@@ -163,7 +163,7 @@ internal void NumberLocal(int number)
Value = (ulong)number;
}
- public void AddAssignment(Operation operation)
+ public readonly void AddAssignment(Operation operation)
{
if (Kind == OperandKind.LocalVariable)
{
@@ -187,7 +187,7 @@ public void AddAssignment(Operation operation)
}
}
- public void RemoveAssignment(Operation operation)
+ public readonly void RemoveAssignment(Operation operation)
{
if (Kind == OperandKind.LocalVariable)
{
@@ -211,7 +211,7 @@ public void RemoveAssignment(Operation operation)
}
}
- public void AddUse(Operation operation)
+ public readonly void AddUse(Operation operation)
{
if (Kind == OperandKind.LocalVariable)
{
@@ -235,7 +235,7 @@ public void AddUse(Operation operation)
}
}
- public void RemoveUse(Operation operation)
+ public readonly void RemoveUse(Operation operation)
{
if (Kind == OperandKind.LocalVariable)
{
@@ -259,7 +259,7 @@ public void RemoveUse(Operation operation)
}
}
- public Span GetUses(ref Span buffer)
+ public readonly Span GetUses(ref Span buffer)
{
ReadOnlySpan uses = Uses;
@@ -270,7 +270,7 @@ public Span GetUses(ref Span buffer)
uses.CopyTo(buffer);
- return buffer.Slice(0, uses.Length);
+ return buffer[..uses.Length];
}
private static void New(ref T* data, ref ushort count, ref ushort capacity, ushort initialCapacity) where T : unmanaged
@@ -360,7 +360,7 @@ private static void Remove(in T item, ref T* data, ref ushort count) where T
{
if (i + 1 < count)
{
- span.Slice(i + 1).CopyTo(span.Slice(i));
+ span[(i + 1)..].CopyTo(span[i..]);
}
count--;
@@ -380,7 +380,7 @@ private static void Remove(in T item, ref T* data, ref uint count) where T :
{
if (i + 1 < count)
{
- span.Slice(i + 1).CopyTo(span.Slice(i));
+ span[(i + 1)..].CopyTo(span[i..]);
}
count--;
@@ -390,17 +390,17 @@ private static void Remove(in T item, ref T* data, ref uint count) where T :
}
}
- public override int GetHashCode()
+ public readonly override int GetHashCode()
{
return ((ulong)_data).GetHashCode();
}
- public bool Equals(Operand operand)
+ public readonly bool Equals(Operand operand)
{
return operand._data == _data;
}
- public override bool Equals(object obj)
+ public readonly override bool Equals(object obj)
{
return obj is Operand operand && Equals(operand);
}
@@ -453,8 +453,10 @@ private static Operand Make(OperandKind kind, OperandType type, ulong value, Sym
// Look in the next InternTableProbeLength slots for a match.
for (uint i = 0; i < InternTableProbeLength; i++)
{
- Operand interned = new();
- interned._data = &InternTable[(hash + i) % InternTableSize];
+ Operand interned = new()
+ {
+ _data = &InternTable[(hash + i) % InternTableSize],
+ };
// If slot matches the allocation request then return that slot.
if (interned.Kind == kind && interned.Type == type && interned.Value == value && interned.Symbol == symbol)
@@ -479,11 +481,13 @@ private static Operand Make(OperandKind kind, OperandType type, ulong value, Sym
*data = default;
- Operand result = new();
- result._data = data;
- result.Value = value;
- result.Kind = kind;
- result.Type = type;
+ Operand result = new()
+ {
+ _data = data,
+ Value = value,
+ Kind = kind,
+ Type = type,
+ };
if (kind != OperandKind.Memory)
{
@@ -591,4 +595,4 @@ public static Operand MemoryOp(
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs b/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs
index adb835614..2b973f006 100644
--- a/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs
@@ -8,6 +8,6 @@ enum OperandKind
LocalVariable,
Memory,
Register,
- Undefined
+ Undefined,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/OperandType.cs b/src/ARMeilleure/IntermediateRepresentation/OperandType.cs
index 81b22cf56..67ebdcde4 100644
--- a/src/ARMeilleure/IntermediateRepresentation/OperandType.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/OperandType.cs
@@ -9,7 +9,7 @@ enum OperandType
I64,
FP32,
FP64,
- V128
+ V128,
}
static class OperandTypeExtensions
@@ -22,44 +22,41 @@ public static bool IsInteger(this OperandType type)
public static RegisterType ToRegisterType(this OperandType type)
{
- switch (type)
+ return type switch
{
- case OperandType.FP32: return RegisterType.Vector;
- case OperandType.FP64: return RegisterType.Vector;
- case OperandType.I32: return RegisterType.Integer;
- case OperandType.I64: return RegisterType.Integer;
- case OperandType.V128: return RegisterType.Vector;
- }
-
- throw new InvalidOperationException($"Invalid operand type \"{type}\".");
+ OperandType.FP32 => RegisterType.Vector,
+ OperandType.FP64 => RegisterType.Vector,
+ OperandType.I32 => RegisterType.Integer,
+ OperandType.I64 => RegisterType.Integer,
+ OperandType.V128 => RegisterType.Vector,
+ _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."),
+ };
}
public static int GetSizeInBytes(this OperandType type)
{
- switch (type)
+ return type switch
{
- case OperandType.FP32: return 4;
- case OperandType.FP64: return 8;
- case OperandType.I32: return 4;
- case OperandType.I64: return 8;
- case OperandType.V128: return 16;
- }
-
- throw new InvalidOperationException($"Invalid operand type \"{type}\".");
+ OperandType.FP32 => 4,
+ OperandType.FP64 => 8,
+ OperandType.I32 => 4,
+ OperandType.I64 => 8,
+ OperandType.V128 => 16,
+ _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."),
+ };
}
public static int GetSizeInBytesLog2(this OperandType type)
{
- switch (type)
+ return type switch
{
- case OperandType.FP32: return 2;
- case OperandType.FP64: return 3;
- case OperandType.I32: return 2;
- case OperandType.I64: return 3;
- case OperandType.V128: return 4;
- }
-
- throw new InvalidOperationException($"Invalid operand type \"{type}\".");
+ OperandType.FP32 => 2,
+ OperandType.FP64 => 3,
+ OperandType.I32 => 2,
+ OperandType.I64 => 3,
+ OperandType.V128 => 4,
+ _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."),
+ };
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/Operation.cs b/src/ARMeilleure/IntermediateRepresentation/Operation.cs
index c71e143c3..bc3a71b31 100644
--- a/src/ARMeilleure/IntermediateRepresentation/Operation.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/Operation.cs
@@ -20,60 +20,60 @@ internal struct Data
private Data* _data;
- public Instruction Instruction
+ public readonly Instruction Instruction
{
get => (Instruction)_data->Instruction;
private set => _data->Instruction = (ushort)value;
}
- public Intrinsic Intrinsic
+ public readonly Intrinsic Intrinsic
{
get => (Intrinsic)_data->Intrinsic;
private set => _data->Intrinsic = (ushort)value;
}
- public Operation ListPrevious
+ public readonly Operation ListPrevious
{
get => _data->ListPrevious;
set => _data->ListPrevious = value;
}
- public Operation ListNext
+ public readonly Operation ListNext
{
get => _data->ListNext;
set => _data->ListNext = value;
}
- public Operand Destination
+ public readonly Operand Destination
{
get => _data->DestinationsCount != 0 ? GetDestination(0) : default;
set => SetDestination(value);
}
- public int DestinationsCount => _data->DestinationsCount;
- public int SourcesCount => _data->SourcesCount;
+ public readonly int DestinationsCount => _data->DestinationsCount;
+ public readonly int SourcesCount => _data->SourcesCount;
- internal Span DestinationsUnsafe => new(_data->Destinations, _data->DestinationsCount);
- internal Span SourcesUnsafe => new(_data->Sources, _data->SourcesCount);
+ internal readonly Span DestinationsUnsafe => new(_data->Destinations, _data->DestinationsCount);
+ internal readonly Span SourcesUnsafe => new(_data->Sources, _data->SourcesCount);
- public PhiOperation AsPhi()
+ public readonly PhiOperation AsPhi()
{
Debug.Assert(Instruction == Instruction.Phi);
return new PhiOperation(this);
}
- public Operand GetDestination(int index)
+ public readonly Operand GetDestination(int index)
{
return DestinationsUnsafe[index];
}
- public Operand GetSource(int index)
+ public readonly Operand GetSource(int index)
{
return SourcesUnsafe[index];
}
- public void SetDestination(int index, Operand dest)
+ public readonly void SetDestination(int index, Operand dest)
{
ref Operand curDest = ref DestinationsUnsafe[index];
@@ -83,7 +83,7 @@ public void SetDestination(int index, Operand dest)
curDest = dest;
}
- public void SetSource(int index, Operand src)
+ public readonly void SetSource(int index, Operand src)
{
ref Operand curSrc = ref SourcesUnsafe[index];
@@ -93,7 +93,7 @@ public void SetSource(int index, Operand src)
curSrc = src;
}
- private void RemoveOldDestinations()
+ private readonly void RemoveOldDestinations()
{
for (int i = 0; i < _data->DestinationsCount; i++)
{
@@ -101,7 +101,7 @@ private void RemoveOldDestinations()
}
}
- public void SetDestination(Operand dest)
+ public readonly void SetDestination(Operand dest)
{
RemoveOldDestinations();
@@ -119,7 +119,7 @@ public void SetDestination(Operand dest)
}
}
- public void SetDestinations(Operand[] dests)
+ public readonly void SetDestinations(Operand[] dests)
{
RemoveOldDestinations();
@@ -135,7 +135,7 @@ public void SetDestinations(Operand[] dests)
}
}
- private void RemoveOldSources()
+ private readonly void RemoveOldSources()
{
for (int index = 0; index < _data->SourcesCount; index++)
{
@@ -143,7 +143,7 @@ private void RemoveOldSources()
}
}
- public void SetSource(Operand src)
+ public readonly void SetSource(Operand src)
{
RemoveOldSources();
@@ -161,7 +161,7 @@ public void SetSource(Operand src)
}
}
- public void SetSources(Operand[] srcs)
+ public readonly void SetSources(Operand[] srcs)
{
RemoveOldSources();
@@ -184,7 +184,7 @@ public void TurnIntoCopy(Operand source)
SetSource(source);
}
- private void AddAssignment(Operand op)
+ private readonly void AddAssignment(Operand op)
{
if (op != default)
{
@@ -192,7 +192,7 @@ private void AddAssignment(Operand op)
}
}
- private void RemoveAssignment(Operand op)
+ private readonly void RemoveAssignment(Operand op)
{
if (op != default)
{
@@ -200,7 +200,7 @@ private void RemoveAssignment(Operand op)
}
}
- private void AddUse(Operand op)
+ private readonly void AddUse(Operand op)
{
if (op != default)
{
@@ -208,7 +208,7 @@ private void AddUse(Operand op)
}
}
- private void RemoveUse(Operand op)
+ private readonly void RemoveUse(Operand op)
{
if (op != default)
{
@@ -216,17 +216,17 @@ private void RemoveUse(Operand op)
}
}
- public bool Equals(Operation operation)
+ public readonly bool Equals(Operation operation)
{
return operation._data == _data;
}
- public override bool Equals(object obj)
+ public readonly override bool Equals(object obj)
{
return obj is Operation operation && Equals(operation);
}
- public override int GetHashCode()
+ public readonly override int GetHashCode()
{
return HashCode.Combine((IntPtr)_data);
}
@@ -267,9 +267,11 @@ private static Operation Make(Instruction inst, int destCount, int srcCount)
Data* data = Allocators.Operations.Allocate();
*data = default;
- Operation result = new();
- result._data = data;
- result.Instruction = inst;
+ Operation result = new()
+ {
+ _data = data,
+ Instruction = inst,
+ };
EnsureCapacity(ref result._data->Destinations, ref result._data->DestinationsCount, destCount);
EnsureCapacity(ref result._data->Sources, ref result._data->SourcesCount, srcCount);
@@ -373,4 +375,4 @@ public static Operation PhiOperation(Operand dest, int srcCount)
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/PhiOperation.cs b/src/ARMeilleure/IntermediateRepresentation/PhiOperation.cs
index d2a3cf218..672c280fa 100644
--- a/src/ARMeilleure/IntermediateRepresentation/PhiOperation.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/PhiOperation.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Translation;
+using ARMeilleure.Translation;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.IntermediateRepresentation
diff --git a/src/ARMeilleure/IntermediateRepresentation/Register.cs b/src/ARMeilleure/IntermediateRepresentation/Register.cs
index 241e4d13d..208f94be1 100644
--- a/src/ARMeilleure/IntermediateRepresentation/Register.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/Register.cs
@@ -11,7 +11,7 @@ namespace ARMeilleure.IntermediateRepresentation
public Register(int index, RegisterType type)
{
Index = index;
- Type = type;
+ Type = type;
}
public override int GetHashCode()
@@ -37,7 +37,7 @@ public override bool Equals(object obj)
public bool Equals(Register other)
{
return other.Index == Index &&
- other.Type == Type;
+ other.Type == Type;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs b/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs
index 88ac6c124..2b4c9068c 100644
--- a/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs
+++ b/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs
@@ -5,6 +5,6 @@ enum RegisterType
Integer,
Vector,
Flag,
- FpFlag
+ FpFlag,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Memory/IJitMemoryAllocator.cs b/src/ARMeilleure/Memory/IJitMemoryAllocator.cs
index 19b696b0a..ff64bf13e 100644
--- a/src/ARMeilleure/Memory/IJitMemoryAllocator.cs
+++ b/src/ARMeilleure/Memory/IJitMemoryAllocator.cs
@@ -1,10 +1,8 @@
-namespace ARMeilleure.Memory
+namespace ARMeilleure.Memory
{
public interface IJitMemoryAllocator
{
IJitMemoryBlock Allocate(ulong size);
IJitMemoryBlock Reserve(ulong size);
-
- ulong GetPageSize();
}
}
diff --git a/src/ARMeilleure/Memory/IJitMemoryBlock.cs b/src/ARMeilleure/Memory/IJitMemoryBlock.cs
index 670f2862d..c103fe8d1 100644
--- a/src/ARMeilleure/Memory/IJitMemoryBlock.cs
+++ b/src/ARMeilleure/Memory/IJitMemoryBlock.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.Memory
{
@@ -6,8 +6,9 @@ public interface IJitMemoryBlock : IDisposable
{
IntPtr Pointer { get; }
- bool Commit(ulong offset, ulong size);
+ void Commit(ulong offset, ulong size);
+ void MapAsRw(ulong offset, ulong size);
void MapAsRx(ulong offset, ulong size);
void MapAsRwx(ulong offset, ulong size);
}
diff --git a/src/ARMeilleure/Memory/IMemoryManager.cs b/src/ARMeilleure/Memory/IMemoryManager.cs
index 5eb1fadd6..952cd2b4f 100644
--- a/src/ARMeilleure/Memory/IMemoryManager.cs
+++ b/src/ARMeilleure/Memory/IMemoryManager.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.Memory
{
@@ -74,4 +74,4 @@ public interface IMemoryManager
/// Optional ID of the handles that should not be signalled
void SignalMemoryTracking(ulong va, ulong size, bool write, bool precise = false, int? exemptId = null);
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Memory/MemoryManagerType.cs b/src/ARMeilleure/Memory/MemoryManagerType.cs
index ce84ccaf3..b1cdbb069 100644
--- a/src/ARMeilleure/Memory/MemoryManagerType.cs
+++ b/src/ARMeilleure/Memory/MemoryManagerType.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.Memory
+namespace ARMeilleure.Memory
{
///
/// Indicates the type of a memory manager and the method it uses for memory mapping
@@ -28,10 +28,10 @@ public enum MemoryManagerType
/// Same as the host mapped memory manager type, but without masking the address within the address space.
/// Allows invalid access from JIT code to the rest of the program, but is faster.
///
- HostMappedUnsafe
+ HostMappedUnsafe,
}
- static class MemoryManagerTypeExtensions
+ public static class MemoryManagerTypeExtensions
{
public static bool IsHostMapped(this MemoryManagerType type)
{
diff --git a/src/ARMeilleure/Memory/ReservedRegion.cs b/src/ARMeilleure/Memory/ReservedRegion.cs
index 2197afad9..3870d4c84 100644
--- a/src/ARMeilleure/Memory/ReservedRegion.cs
+++ b/src/ARMeilleure/Memory/ReservedRegion.cs
@@ -1,8 +1,8 @@
-using System;
+using System;
namespace ARMeilleure.Memory
{
- class ReservedRegion
+ public class ReservedRegion
{
public const int DefaultGranularity = 65536; // Mapping granularity in Windows.
diff --git a/src/ARMeilleure/Native/JitSupportDarwin.cs b/src/ARMeilleure/Native/JitSupportDarwin.cs
index 7d6a8634a..339460397 100644
--- a/src/ARMeilleure/Native/JitSupportDarwin.cs
+++ b/src/ARMeilleure/Native/JitSupportDarwin.cs
@@ -5,7 +5,7 @@
namespace ARMeilleure.Native
{
[SupportedOSPlatform("macos")]
- public static partial class JitSupportDarwin
+ static partial class JitSupportDarwin
{
[LibraryImport("libarmeilleure-jitsupport", EntryPoint = "armeilleure_jit_memcpy")]
public static partial void Copy(IntPtr dst, IntPtr src, ulong n);
diff --git a/src/ARMeilleure/Optimizations.cs b/src/ARMeilleure/Optimizations.cs
index a84a4dc4f..8fe478e47 100644
--- a/src/ARMeilleure/Optimizations.cs
+++ b/src/ARMeilleure/Optimizations.cs
@@ -1,5 +1,3 @@
-using System.Runtime.Intrinsics.Arm;
-
namespace ARMeilleure
{
using Arm64HardwareCapabilities = ARMeilleure.CodeGen.Arm64.HardwareCapabilities;
@@ -9,30 +7,31 @@ public static class Optimizations
{
public static bool FastFP { get; set; } = true;
- public static bool AllowLcqInFunctionTable { get; set; } = true;
+ public static bool AllowLcqInFunctionTable { get; set; } = true;
public static bool UseUnmanagedDispatchLoop { get; set; } = true;
- public static bool UseAdvSimdIfAvailable { get; set; } = true;
+ public static bool UseAdvSimdIfAvailable { get; set; } = true;
+ public static bool UseArm64AesIfAvailable { get; set; } = true;
public static bool UseArm64PmullIfAvailable { get; set; } = true;
- public static bool UseSseIfAvailable { get; set; } = true;
- public static bool UseSse2IfAvailable { get; set; } = true;
- public static bool UseSse3IfAvailable { get; set; } = true;
- public static bool UseSsse3IfAvailable { get; set; } = true;
- public static bool UseSse41IfAvailable { get; set; } = true;
- public static bool UseSse42IfAvailable { get; set; } = true;
- public static bool UsePopCntIfAvailable { get; set; } = true;
- public static bool UseAvxIfAvailable { get; set; } = true;
- public static bool UseAvx512FIfAvailable { get; set; } = true;
- public static bool UseAvx512VlIfAvailable { get; set; } = true;
- public static bool UseAvx512BwIfAvailable { get; set; } = true;
- public static bool UseAvx512DqIfAvailable { get; set; } = true;
- public static bool UseF16cIfAvailable { get; set; } = true;
- public static bool UseFmaIfAvailable { get; set; } = true;
- public static bool UseAesniIfAvailable { get; set; } = true;
+ public static bool UseSseIfAvailable { get; set; } = true;
+ public static bool UseSse2IfAvailable { get; set; } = true;
+ public static bool UseSse3IfAvailable { get; set; } = true;
+ public static bool UseSsse3IfAvailable { get; set; } = true;
+ public static bool UseSse41IfAvailable { get; set; } = true;
+ public static bool UseSse42IfAvailable { get; set; } = true;
+ public static bool UsePopCntIfAvailable { get; set; } = true;
+ public static bool UseAvxIfAvailable { get; set; } = true;
+ public static bool UseAvx512FIfAvailable { get; set; } = true;
+ public static bool UseAvx512VlIfAvailable { get; set; } = true;
+ public static bool UseAvx512BwIfAvailable { get; set; } = true;
+ public static bool UseAvx512DqIfAvailable { get; set; } = true;
+ public static bool UseF16cIfAvailable { get; set; } = true;
+ public static bool UseFmaIfAvailable { get; set; } = true;
+ public static bool UseAesniIfAvailable { get; set; } = true;
public static bool UsePclmulqdqIfAvailable { get; set; } = true;
- public static bool UseShaIfAvailable { get; set; } = true;
- public static bool UseGfniIfAvailable { get; set; } = true;
+ public static bool UseShaIfAvailable { get; set; } = true;
+ public static bool UseGfniIfAvailable { get; set; } = true;
public static bool ForceLegacySse
{
@@ -40,7 +39,9 @@ public static bool ForceLegacySse
set => X86HardwareCapabilities.ForceLegacySse = value;
}
+#pragma warning disable IDE0055 // Disable formatting
internal static bool UseAdvSimd => UseAdvSimdIfAvailable && Arm64HardwareCapabilities.SupportsAdvSimd;
+ internal static bool UseArm64Aes => UseArm64AesIfAvailable && Arm64HardwareCapabilities.SupportsAes;
internal static bool UseArm64Pmull => UseArm64PmullIfAvailable && Arm64HardwareCapabilities.SupportsPmull;
internal static bool UseSse => UseSseIfAvailable && X86HardwareCapabilities.SupportsSse;
@@ -61,6 +62,7 @@ public static bool ForceLegacySse
internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && X86HardwareCapabilities.SupportsPclmulqdq;
internal static bool UseSha => UseShaIfAvailable && X86HardwareCapabilities.SupportsSha;
internal static bool UseGfni => UseGfniIfAvailable && X86HardwareCapabilities.SupportsGfni;
+#pragma warning restore IDE0055
internal static bool UseAvx512Ortho => UseAvx512F && UseAvx512Vl;
internal static bool UseAvx512OrthoFloat => UseAvx512Ortho && UseAvx512Dq;
diff --git a/src/ARMeilleure/Signal/NativeSignalHandler.cs b/src/ARMeilleure/Signal/NativeSignalHandlerGenerator.cs
similarity index 57%
rename from src/ARMeilleure/Signal/NativeSignalHandler.cs
rename to src/ARMeilleure/Signal/NativeSignalHandlerGenerator.cs
index cddeb8174..c5e708e16 100644
--- a/src/ARMeilleure/Signal/NativeSignalHandler.cs
+++ b/src/ARMeilleure/Signal/NativeSignalHandlerGenerator.cs
@@ -1,64 +1,14 @@
-using ARMeilleure.IntermediateRepresentation;
-using ARMeilleure.Memory;
+using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
-using ARMeilleure.Translation.Cache;
using System;
-using System.Runtime.CompilerServices;
using System.Runtime.InteropServices;
-
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Signal
{
- [StructLayout(LayoutKind.Sequential, Pack = 1)]
- struct SignalHandlerRange
- {
- public int IsActive;
- public nuint RangeAddress;
- public nuint RangeEndAddress;
- public IntPtr ActionPointer;
- }
-
- [StructLayout(LayoutKind.Sequential, Pack = 1)]
- struct SignalHandlerConfig
+ public static class NativeSignalHandlerGenerator
{
- ///
- /// The byte offset of the faulting address in the SigInfo or ExceptionRecord struct.
- ///
- public int StructAddressOffset;
-
- ///
- /// The byte offset of the write flag in the SigInfo or ExceptionRecord struct.
- ///
- public int StructWriteOffset;
-
- ///
- /// The sigaction handler that was registered before this one. (unix only)
- ///
- public nuint UnixOldSigaction;
-
- ///
- /// The type of the previous sigaction. True for the 3 argument variant. (unix only)
- ///
- public int UnixOldSigaction3Arg;
-
- public SignalHandlerRange Range0;
- public SignalHandlerRange Range1;
- public SignalHandlerRange Range2;
- public SignalHandlerRange Range3;
- public SignalHandlerRange Range4;
- public SignalHandlerRange Range5;
- public SignalHandlerRange Range6;
- public SignalHandlerRange Range7;
- }
-
- public static class NativeSignalHandler
- {
- private delegate void UnixExceptionHandler(int sig, IntPtr info, IntPtr ucontext);
- [UnmanagedFunctionPointer(CallingConvention.Winapi)]
- private delegate int VectoredExceptionHandler(IntPtr exceptionInfo);
-
- private const int MaxTrackedRanges = 8;
+ public const int MaxTrackedRanges = 8;
private const int StructAddressOffset = 0;
private const int StructWriteOffset = 4;
@@ -71,119 +21,10 @@ public static class NativeSignalHandler
private const uint EXCEPTION_ACCESS_VIOLATION = 0xc0000005;
- private static ulong _pageSize;
- private static ulong _pageMask;
-
- private static IntPtr _handlerConfig;
- private static IntPtr _signalHandlerPtr;
- private static IntPtr _signalHandlerHandle;
-
- private static readonly object _lock = new object();
- private static bool _initialized;
-
- static NativeSignalHandler()
- {
- _handlerConfig = Marshal.AllocHGlobal(Unsafe.SizeOf());
- ref SignalHandlerConfig config = ref GetConfigRef();
-
- config = new SignalHandlerConfig();
- }
-
- public static void Initialize(IJitMemoryAllocator allocator)
- {
- JitCache.Initialize(allocator);
- }
-
- public static void InitializeSignalHandler(ulong pageSize, Func customSignalHandlerFactory = null)
- {
- if (_initialized) return;
-
- lock (_lock)
- {
- if (_initialized) return;
-
- _pageSize = pageSize;
- _pageMask = pageSize - 1;
-
- ref SignalHandlerConfig config = ref GetConfigRef();
-
- if (OperatingSystem.IsLinux() || OperatingSystem.IsMacOS())
- {
- _signalHandlerPtr = Marshal.GetFunctionPointerForDelegate(GenerateUnixSignalHandler(_handlerConfig));
-
- if (customSignalHandlerFactory != null)
- {
- _signalHandlerPtr = customSignalHandlerFactory(UnixSignalHandlerRegistration.GetSegfaultExceptionHandler().sa_handler, _signalHandlerPtr);
- }
-
- var old = UnixSignalHandlerRegistration.RegisterExceptionHandler(_signalHandlerPtr);
-
- config.UnixOldSigaction = (nuint)(ulong)old.sa_handler;
- config.UnixOldSigaction3Arg = old.sa_flags & 4;
- }
- else
- {
- config.StructAddressOffset = 40; // ExceptionInformation1
- config.StructWriteOffset = 32; // ExceptionInformation0
-
- _signalHandlerPtr = Marshal.GetFunctionPointerForDelegate(GenerateWindowsSignalHandler(_handlerConfig));
-
- if (customSignalHandlerFactory != null)
- {
- _signalHandlerPtr = customSignalHandlerFactory(IntPtr.Zero, _signalHandlerPtr);
- }
-
- _signalHandlerHandle = WindowsSignalHandlerRegistration.RegisterExceptionHandler(_signalHandlerPtr);
- }
-
- _initialized = true;
- }
- }
-
- private static unsafe ref SignalHandlerConfig GetConfigRef()
- {
- return ref Unsafe.AsRef((void*)_handlerConfig);
- }
-
- public static unsafe bool AddTrackedRegion(nuint address, nuint endAddress, IntPtr action)
- {
- var ranges = &((SignalHandlerConfig*)_handlerConfig)->Range0;
-
- for (int i = 0; i < MaxTrackedRanges; i++)
- {
- if (ranges[i].IsActive == 0)
- {
- ranges[i].RangeAddress = address;
- ranges[i].RangeEndAddress = endAddress;
- ranges[i].ActionPointer = action;
- ranges[i].IsActive = 1;
-
- return true;
- }
- }
-
- return false;
- }
-
- public static unsafe bool RemoveTrackedRegion(nuint address)
+ private static Operand EmitGenericRegionCheck(EmitterContext context, IntPtr signalStructPtr, Operand faultAddress, Operand isWrite, int rangeStructSize, ulong pageSize)
{
- var ranges = &((SignalHandlerConfig*)_handlerConfig)->Range0;
-
- for (int i = 0; i < MaxTrackedRanges; i++)
- {
- if (ranges[i].IsActive == 1 && ranges[i].RangeAddress == address)
- {
- ranges[i].IsActive = 0;
+ ulong pageMask = pageSize - 1;
- return true;
- }
- }
-
- return false;
- }
-
- private static Operand EmitGenericRegionCheck(EmitterContext context, IntPtr signalStructPtr, Operand faultAddress, Operand isWrite)
- {
Operand inRegionLocal = context.AllocateLocal(OperandType.I32);
context.Copy(inRegionLocal, Const(0));
@@ -191,7 +32,7 @@ private static Operand EmitGenericRegionCheck(EmitterContext context, IntPtr sig
for (int i = 0; i < MaxTrackedRanges; i++)
{
- ulong rangeBaseOffset = (ulong)(RangeOffset + i * Unsafe.SizeOf());
+ ulong rangeBaseOffset = (ulong)(RangeOffset + i * rangeStructSize);
Operand nextLabel = Label();
@@ -205,13 +46,12 @@ private static Operand EmitGenericRegionCheck(EmitterContext context, IntPtr sig
// Is the fault address within this tracked region?
Operand inRange = context.BitwiseAnd(
context.ICompare(faultAddress, rangeAddress, Comparison.GreaterOrEqualUI),
- context.ICompare(faultAddress, rangeEndAddress, Comparison.LessUI)
- );
+ context.ICompare(faultAddress, rangeEndAddress, Comparison.LessUI));
// Only call tracking if in range.
context.BranchIfFalse(nextLabel, inRange, BasicBlockFrequency.Cold);
- Operand offset = context.BitwiseAnd(context.Subtract(faultAddress, rangeAddress), Const(~_pageMask));
+ Operand offset = context.BitwiseAnd(context.Subtract(faultAddress, rangeAddress), Const(~pageMask));
// Call the tracking action, with the pointer's relative offset to the base address.
Operand trackingActionPtr = context.Load(OperandType.I64, Const((ulong)signalStructPtr + rangeBaseOffset + 20));
@@ -222,7 +62,7 @@ private static Operand EmitGenericRegionCheck(EmitterContext context, IntPtr sig
// Tracking action should be non-null to call it, otherwise assume false return.
context.BranchIfFalse(skipActionLabel, trackingActionPtr);
- Operand result = context.Call(trackingActionPtr, OperandType.I32, offset, Const(_pageSize), isWrite);
+ Operand result = context.Call(trackingActionPtr, OperandType.I32, offset, Const(pageSize), isWrite);
context.Copy(inRegionLocal, result);
context.MarkLabel(skipActionLabel);
@@ -255,20 +95,19 @@ private static Operand GenerateUnixWriteFlag(EmitterContext context, Operand uco
{
if (OperatingSystem.IsMacOS())
{
- const ulong mcontextOffset = 48; // uc_mcontext
- Operand ctxPtr = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(mcontextOffset)));
+ const ulong McontextOffset = 48; // uc_mcontext
+ Operand ctxPtr = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(McontextOffset)));
if (RuntimeInformation.ProcessArchitecture == Architecture.Arm64)
{
- const ulong esrOffset = 8; // __es.__esr
- Operand esr = context.Load(OperandType.I64, context.Add(ctxPtr, Const(esrOffset)));
+ const ulong EsrOffset = 8; // __es.__esr
+ Operand esr = context.Load(OperandType.I64, context.Add(ctxPtr, Const(EsrOffset)));
return context.BitwiseAnd(esr, Const(0x40ul));
}
-
- if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
+ else if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
{
- const ulong errOffset = 4; // __es.__err
- Operand err = context.Load(OperandType.I64, context.Add(ctxPtr, Const(errOffset)));
+ const ulong ErrOffset = 4; // __es.__err
+ Operand err = context.Load(OperandType.I64, context.Add(ctxPtr, Const(ErrOffset)));
return context.BitwiseAnd(err, Const(2ul));
}
}
@@ -281,10 +120,10 @@ private static Operand GenerateUnixWriteFlag(EmitterContext context, Operand uco
Operand loopLabel = Label();
Operand successLabel = Label();
- const ulong auxOffset = 464; // uc_mcontext.__reserved
- const uint esrMagic = 0x45535201;
+ const ulong AuxOffset = 464; // uc_mcontext.__reserved
+ const uint EsrMagic = 0x45535201;
- context.Copy(auxPtr, context.Add(ucontextPtr, Const(auxOffset)));
+ context.Copy(auxPtr, context.Add(ucontextPtr, Const(AuxOffset)));
context.MarkLabel(loopLabel);
@@ -293,7 +132,7 @@ private static Operand GenerateUnixWriteFlag(EmitterContext context, Operand uco
// _aarch64_ctx::size
Operand size = context.Load(OperandType.I32, context.Add(auxPtr, Const(4ul)));
- context.BranchIf(successLabel, magic, Const(esrMagic), Comparison.Equal);
+ context.BranchIf(successLabel, magic, Const(EsrMagic), Comparison.Equal);
context.Copy(auxPtr, context.Add(auxPtr, context.ZeroExtend32(OperandType.I64, size)));
@@ -305,11 +144,10 @@ private static Operand GenerateUnixWriteFlag(EmitterContext context, Operand uco
Operand esr = context.Load(OperandType.I64, context.Add(auxPtr, Const(8ul)));
return context.BitwiseAnd(esr, Const(0x40ul));
}
-
- if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
+ else if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
{
- const int errOffset = 192; // uc_mcontext.gregs[REG_ERR]
- Operand err = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(errOffset)));
+ const int ErrOffset = 192; // uc_mcontext.gregs[REG_ERR]
+ Operand err = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(ErrOffset)));
return context.BitwiseAnd(err, Const(2ul));
}
}
@@ -317,9 +155,9 @@ private static Operand GenerateUnixWriteFlag(EmitterContext context, Operand uco
throw new PlatformNotSupportedException();
}
- private static UnixExceptionHandler GenerateUnixSignalHandler(IntPtr signalStructPtr)
+ public static byte[] GenerateUnixSignalHandler(IntPtr signalStructPtr, int rangeStructSize, ulong pageSize)
{
- EmitterContext context = new EmitterContext();
+ EmitterContext context = new();
// (int sig, SigInfo* sigInfo, void* ucontext)
Operand sigInfoPtr = context.LoadArgument(OperandType.I64, 1);
@@ -330,7 +168,7 @@ private static UnixExceptionHandler GenerateUnixSignalHandler(IntPtr signalStruc
Operand isWrite = context.ICompareNotEqual(writeFlag, Const(0L)); // Normalize to 0/1.
- Operand isInRegion = EmitGenericRegionCheck(context, signalStructPtr, faultAddress, isWrite);
+ Operand isInRegion = EmitGenericRegionCheck(context, signalStructPtr, faultAddress, isWrite, rangeStructSize, pageSize);
Operand endLabel = Label();
@@ -362,12 +200,12 @@ private static UnixExceptionHandler GenerateUnixSignalHandler(IntPtr signalStruc
OperandType[] argTypes = new OperandType[] { OperandType.I32, OperandType.I64, OperandType.I64 };
- return Compiler.Compile(cfg, argTypes, OperandType.None, CompilerOptions.HighCq, RuntimeInformation.ProcessArchitecture).Map();
+ return Compiler.Compile(cfg, argTypes, OperandType.None, CompilerOptions.HighCq, RuntimeInformation.ProcessArchitecture).Code;
}
- private static VectoredExceptionHandler GenerateWindowsSignalHandler(IntPtr signalStructPtr)
+ public static byte[] GenerateWindowsSignalHandler(IntPtr signalStructPtr, int rangeStructSize, ulong pageSize)
{
- EmitterContext context = new EmitterContext();
+ EmitterContext context = new();
// (ExceptionPointers* exceptionInfo)
Operand exceptionInfoPtr = context.LoadArgument(OperandType.I64, 0);
@@ -394,7 +232,7 @@ private static VectoredExceptionHandler GenerateWindowsSignalHandler(IntPtr sign
Operand isWrite = context.ICompareNotEqual(writeFlag, Const(0L)); // Normalize to 0/1.
- Operand isInRegion = EmitGenericRegionCheck(context, signalStructPtr, faultAddress, isWrite);
+ Operand isInRegion = EmitGenericRegionCheck(context, signalStructPtr, faultAddress, isWrite, rangeStructSize, pageSize);
Operand endLabel = Label();
@@ -416,7 +254,7 @@ private static VectoredExceptionHandler GenerateWindowsSignalHandler(IntPtr sign
OperandType[] argTypes = new OperandType[] { OperandType.I64 };
- return Compiler.Compile(cfg, argTypes, OperandType.I32, CompilerOptions.HighCq, RuntimeInformation.ProcessArchitecture).Map();
+ return Compiler.Compile(cfg, argTypes, OperandType.I32, CompilerOptions.HighCq, RuntimeInformation.ProcessArchitecture).Code;
}
}
}
diff --git a/src/ARMeilleure/Signal/TestMethods.cs b/src/ARMeilleure/Signal/TestMethods.cs
index e2ecad242..0a8b3f5ff 100644
--- a/src/ARMeilleure/Signal/TestMethods.cs
+++ b/src/ARMeilleure/Signal/TestMethods.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.IntermediateRepresentation;
+using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using System;
using System.Runtime.InteropServices;
@@ -20,7 +20,7 @@ public static class TestMethods
public static DebugPartialUnmap GenerateDebugPartialUnmap()
{
- EmitterContext context = new EmitterContext();
+ EmitterContext context = new();
var result = WindowsPartialUnmapHandler.EmitRetryFromAccessViolation(context);
@@ -37,7 +37,7 @@ public static DebugPartialUnmap GenerateDebugPartialUnmap()
public static DebugThreadLocalMapGetOrReserve GenerateDebugThreadLocalMapGetOrReserve(IntPtr structPtr)
{
- EmitterContext context = new EmitterContext();
+ EmitterContext context = new();
var result = WindowsPartialUnmapHandler.EmitThreadLocalMapIntGetOrReserve(context, structPtr, context.LoadArgument(OperandType.I32, 0), context.LoadArgument(OperandType.I32, 1));
@@ -54,7 +54,7 @@ public static DebugThreadLocalMapGetOrReserve GenerateDebugThreadLocalMapGetOrRe
public static DebugNativeWriteLoop GenerateDebugNativeWriteLoop()
{
- EmitterContext context = new EmitterContext();
+ EmitterContext context = new();
// Loop a write to the target address until "running" is false.
diff --git a/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs b/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs
index 941e36e58..3bf6a4498 100644
--- a/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs
+++ b/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs
@@ -1,8 +1,8 @@
-using ARMeilleure.IntermediateRepresentation;
+using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using Ryujinx.Common.Memory.PartialUnmaps;
using System;
-
+using System.Runtime.InteropServices;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Signal
@@ -10,8 +10,28 @@ namespace ARMeilleure.Signal
///
/// Methods to handle signals caused by partial unmaps. See the structs for C# implementations of the methods.
///
- internal static class WindowsPartialUnmapHandler
+ internal static partial class WindowsPartialUnmapHandler
{
+ [LibraryImport("kernel32.dll", SetLastError = true, EntryPoint = "LoadLibraryA")]
+ private static partial IntPtr LoadLibrary([MarshalAs(UnmanagedType.LPStr)] string lpFileName);
+
+ [LibraryImport("kernel32.dll", SetLastError = true)]
+ private static partial IntPtr GetProcAddress(IntPtr hModule, [MarshalAs(UnmanagedType.LPStr)] string procName);
+
+ private static IntPtr _getCurrentThreadIdPtr;
+
+ public static IntPtr GetCurrentThreadIdFunc()
+ {
+ if (_getCurrentThreadIdPtr == IntPtr.Zero)
+ {
+ IntPtr handle = LoadLibrary("kernel32.dll");
+
+ _getCurrentThreadIdPtr = GetProcAddress(handle, "GetCurrentThreadId");
+ }
+
+ return _getCurrentThreadIdPtr;
+ }
+
public static Operand EmitRetryFromAccessViolation(EmitterContext context)
{
IntPtr partialRemapStatePtr = PartialUnmapState.GlobalState;
@@ -20,7 +40,7 @@ public static Operand EmitRetryFromAccessViolation(EmitterContext context)
// Get the lock first.
EmitNativeReaderLockAcquire(context, IntPtr.Add(partialRemapStatePtr, PartialUnmapState.PartialUnmapLockOffset));
- IntPtr getCurrentThreadId = WindowsSignalHandlerRegistration.GetCurrentThreadIdFunc();
+ IntPtr getCurrentThreadId = GetCurrentThreadIdFunc();
Operand threadId = context.Call(Const((ulong)getCurrentThreadId), OperandType.I32);
Operand threadIndex = EmitThreadLocalMapIntGetOrReserve(context, localCountsPtr, threadId, Const(0));
@@ -137,15 +157,6 @@ private static Operand EmitThreadLocalMapIntGetValuePtr(EmitterContext context,
return context.Add(structsPtr, context.SignExtend32(OperandType.I64, offset));
}
- private static void EmitThreadLocalMapIntRelease(EmitterContext context, IntPtr threadLocalMapPtr, Operand threadId, Operand index)
- {
- Operand offset = context.Multiply(index, Const(sizeof(int)));
- Operand idsPtr = Const((ulong)IntPtr.Add(threadLocalMapPtr, ThreadLocalMap.ThreadIdsOffset));
- Operand idPtr = context.Add(idsPtr, context.SignExtend32(OperandType.I64, offset));
-
- context.CompareAndSwap(idPtr, threadId, Const(0));
- }
-
private static void EmitAtomicAddI32(EmitterContext context, Operand ptr, Operand additive)
{
Operand loop = Label();
diff --git a/src/ARMeilleure/Signal/WindowsSignalHandlerRegistration.cs b/src/ARMeilleure/Signal/WindowsSignalHandlerRegistration.cs
deleted file mode 100644
index 3219e015d..000000000
--- a/src/ARMeilleure/Signal/WindowsSignalHandlerRegistration.cs
+++ /dev/null
@@ -1,44 +0,0 @@
-using System;
-using System.Runtime.InteropServices;
-
-namespace ARMeilleure.Signal
-{
- unsafe partial class WindowsSignalHandlerRegistration
- {
- [LibraryImport("kernel32.dll")]
- private static partial IntPtr AddVectoredExceptionHandler(uint first, IntPtr handler);
-
- [LibraryImport("kernel32.dll")]
- private static partial ulong RemoveVectoredExceptionHandler(IntPtr handle);
-
- [LibraryImport("kernel32.dll", SetLastError = true, EntryPoint = "LoadLibraryA")]
- private static partial IntPtr LoadLibrary([MarshalAs(UnmanagedType.LPStr)] string lpFileName);
-
- [LibraryImport("kernel32.dll", SetLastError = true)]
- private static partial IntPtr GetProcAddress(IntPtr hModule, [MarshalAs(UnmanagedType.LPStr)] string procName);
-
- private static IntPtr _getCurrentThreadIdPtr;
-
- public static IntPtr RegisterExceptionHandler(IntPtr action)
- {
- return AddVectoredExceptionHandler(1, action);
- }
-
- public static bool RemoveExceptionHandler(IntPtr handle)
- {
- return RemoveVectoredExceptionHandler(handle) != 0;
- }
-
- public static IntPtr GetCurrentThreadIdFunc()
- {
- if (_getCurrentThreadIdPtr == IntPtr.Zero)
- {
- IntPtr handle = LoadLibrary("kernel32.dll");
-
- _getCurrentThreadIdPtr = GetProcAddress(handle, "GetCurrentThreadId");
- }
-
- return _getCurrentThreadIdPtr;
- }
- }
-}
diff --git a/src/ARMeilleure/State/Aarch32Mode.cs b/src/ARMeilleure/State/Aarch32Mode.cs
index 395e288aa..add1cd26f 100644
--- a/src/ARMeilleure/State/Aarch32Mode.cs
+++ b/src/ARMeilleure/State/Aarch32Mode.cs
@@ -2,14 +2,14 @@ namespace ARMeilleure.State
{
enum Aarch32Mode
{
- User = 0b10000,
- Fiq = 0b10001,
- Irq = 0b10010,
+ User = 0b10000,
+ Fiq = 0b10001,
+ Irq = 0b10010,
Supervisor = 0b10011,
- Monitor = 0b10110,
- Abort = 0b10111,
+ Monitor = 0b10110,
+ Abort = 0b10111,
Hypervisor = 0b11010,
- Undefined = 0b11011,
- System = 0b11111
+ Undefined = 0b11011,
+ System = 0b11111,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/State/ExceptionCallback.cs b/src/ARMeilleure/State/ExceptionCallback.cs
index 38d6eef78..2a4e9656a 100644
--- a/src/ARMeilleure/State/ExceptionCallback.cs
+++ b/src/ARMeilleure/State/ExceptionCallback.cs
@@ -2,4 +2,4 @@ namespace ARMeilleure.State
{
public delegate void ExceptionCallbackNoArgs(ExecutionContext context);
public delegate void ExceptionCallback(ExecutionContext context, ulong address, int id);
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/State/ExecutionContext.cs b/src/ARMeilleure/State/ExecutionContext.cs
index 859fb3a5d..ce10a591c 100644
--- a/src/ARMeilleure/State/ExecutionContext.cs
+++ b/src/ARMeilleure/State/ExecutionContext.cs
@@ -7,7 +7,7 @@ public class ExecutionContext
{
private const int MinCountForCheck = 4000;
- private NativeContext _nativeContext;
+ private readonly NativeContext _nativeContext;
internal IntPtr NativeContextPtr => _nativeContext.BasePtr;
@@ -17,8 +17,10 @@ public class ExecutionContext
public ulong Pc => _nativeContext.GetPc();
+#pragma warning disable CA1822 // Mark member as static
public uint CtrEl0 => 0x8444c004;
public uint DczidEl0 => 0x00000004;
+#pragma warning restore CA1822
public ulong CntfrqEl0 => _counter.Frequency;
public ulong CntpctEl0 => _counter.Counter;
@@ -170,4 +172,4 @@ public void Dispose()
_nativeContext.Dispose();
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/State/ExecutionMode.cs b/src/ARMeilleure/State/ExecutionMode.cs
index 29154a255..e1fb722bd 100644
--- a/src/ARMeilleure/State/ExecutionMode.cs
+++ b/src/ARMeilleure/State/ExecutionMode.cs
@@ -1,9 +1,9 @@
namespace ARMeilleure.State
{
- enum ExecutionMode : int
+ enum ExecutionMode
{
Aarch32Arm = 0,
Aarch32Thumb = 1,
- Aarch64 = 2
+ Aarch64 = 2,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/State/FPCR.cs b/src/ARMeilleure/State/FPCR.cs
index 6f707de7d..427300add 100644
--- a/src/ARMeilleure/State/FPCR.cs
+++ b/src/ARMeilleure/State/FPCR.cs
@@ -13,10 +13,10 @@ public enum FPCR : uint
Ide = 1u << 15,
RMode0 = 1u << 22,
RMode1 = 1u << 23,
- Fz = 1u << 24,
- Dn = 1u << 25,
+ Fz = 1u << 24,
+ Dn = 1u << 25,
Ahp = 1u << 26,
- Mask = Ahp | Dn | Fz | RMode1 | RMode0 | Ide | Ixe | Ufe | Ofe | Dze | Ioe // 0x07C09F00u
+ Mask = Ahp | Dn | Fz | RMode1 | RMode0 | Ide | Ixe | Ufe | Ofe | Dze | Ioe, // 0x07C09F00u
}
}
diff --git a/src/ARMeilleure/State/FPException.cs b/src/ARMeilleure/State/FPException.cs
index e24e07af1..5b13659ab 100644
--- a/src/ARMeilleure/State/FPException.cs
+++ b/src/ARMeilleure/State/FPException.cs
@@ -2,11 +2,11 @@ namespace ARMeilleure.State
{
enum FPException
{
- InvalidOp = 0,
+ InvalidOp = 0,
DivideByZero = 1,
- Overflow = 2,
- Underflow = 3,
- Inexact = 4,
- InputDenorm = 7
+ Overflow = 2,
+ Underflow = 3,
+ Inexact = 4,
+ InputDenorm = 7,
}
}
diff --git a/src/ARMeilleure/State/FPRoundingMode.cs b/src/ARMeilleure/State/FPRoundingMode.cs
index 8d757a151..0913175e7 100644
--- a/src/ARMeilleure/State/FPRoundingMode.cs
+++ b/src/ARMeilleure/State/FPRoundingMode.cs
@@ -2,10 +2,10 @@ namespace ARMeilleure.State
{
public enum FPRoundingMode
{
- ToNearest = 0, // With ties to even.
- TowardsPlusInfinity = 1,
+ ToNearest = 0, // With ties to even.
+ TowardsPlusInfinity = 1,
TowardsMinusInfinity = 2,
- TowardsZero = 3,
- ToNearestAway = 4 // With ties to away.
+ TowardsZero = 3,
+ ToNearestAway = 4, // With ties to away.
}
}
diff --git a/src/ARMeilleure/State/FPSCR.cs b/src/ARMeilleure/State/FPSCR.cs
index d6d2fc26a..65a060ebd 100644
--- a/src/ARMeilleure/State/FPSCR.cs
+++ b/src/ARMeilleure/State/FPSCR.cs
@@ -10,6 +10,6 @@ public enum FPSCR : uint
Z = 1u << 30,
N = 1u << 31,
- Mask = N | Z | C | V | FPSR.Mask | FPCR.Mask // 0xFFC09F9Fu
+ Mask = N | Z | C | V | FPSR.Mask | FPCR.Mask, // 0xFFC09F9Fu
}
}
diff --git a/src/ARMeilleure/State/FPSR.cs b/src/ARMeilleure/State/FPSR.cs
index 5e66d5ce1..915b2fb31 100644
--- a/src/ARMeilleure/State/FPSR.cs
+++ b/src/ARMeilleure/State/FPSR.cs
@@ -13,6 +13,6 @@ public enum FPSR : uint
Idc = 1u << 7,
Qc = 1u << 27,
- Mask = Qc | Idc | Ixc | Ufc | Ofc | Dzc | Ioc // 0x0800009Fu
+ Mask = Qc | Idc | Ixc | Ufc | Ofc | Dzc | Ioc, // 0x0800009Fu
}
}
diff --git a/src/ARMeilleure/State/FPState.cs b/src/ARMeilleure/State/FPState.cs
index fa6ab9d46..e76f48240 100644
--- a/src/ARMeilleure/State/FPState.cs
+++ b/src/ARMeilleure/State/FPState.cs
@@ -1,4 +1,4 @@
-namespace ARMeilleure.State
+namespace ARMeilleure.State
{
public enum FPState
{
@@ -26,6 +26,6 @@ public enum FPState
RMode1Flag = 23,
FzFlag = 24,
DnFlag = 25,
- AhpFlag = 26
+ AhpFlag = 26,
}
}
diff --git a/src/ARMeilleure/State/FPType.cs b/src/ARMeilleure/State/FPType.cs
index 84e0db8da..367082ffc 100644
--- a/src/ARMeilleure/State/FPType.cs
+++ b/src/ARMeilleure/State/FPType.cs
@@ -6,6 +6,6 @@ enum FPType
Zero,
Infinity,
QNaN,
- SNaN
+ SNaN,
}
}
diff --git a/src/ARMeilleure/State/ICounter.cs b/src/ARMeilleure/State/ICounter.cs
index 93e721ea3..7aa1cce73 100644
--- a/src/ARMeilleure/State/ICounter.cs
+++ b/src/ARMeilleure/State/ICounter.cs
@@ -15,4 +15,4 @@ public interface ICounter
///
ulong Counter { get; }
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/State/NativeContext.cs b/src/ARMeilleure/State/NativeContext.cs
index 3189bdd8a..5403042ea 100644
--- a/src/ARMeilleure/State/NativeContext.cs
+++ b/src/ARMeilleure/State/NativeContext.cs
@@ -23,7 +23,7 @@ private unsafe struct NativeCtxStorage
public int Running;
}
- private static NativeCtxStorage _dummyStorage = new NativeCtxStorage();
+ private static NativeCtxStorage _dummyStorage = new();
private readonly IJitMemoryBlock _block;
@@ -266,4 +266,4 @@ private static int StorageOffset(ref NativeCtxStorage storage, ref T target)
public void Dispose() => _block.Dispose();
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/State/PState.cs b/src/ARMeilleure/State/PState.cs
index 9a80bc570..d4ddc8656 100644
--- a/src/ARMeilleure/State/PState.cs
+++ b/src/ARMeilleure/State/PState.cs
@@ -12,6 +12,6 @@ public enum PState
VFlag = 28,
CFlag = 29,
ZFlag = 30,
- NFlag = 31
+ NFlag = 31,
}
}
diff --git a/src/ARMeilleure/State/RegisterAlias.cs b/src/ARMeilleure/State/RegisterAlias.cs
index 7ebfa2753..a95740891 100644
--- a/src/ARMeilleure/State/RegisterAlias.cs
+++ b/src/ARMeilleure/State/RegisterAlias.cs
@@ -2,13 +2,13 @@ namespace ARMeilleure.State
{
static class RegisterAlias
{
- public const int R8Usr = 8;
- public const int R9Usr = 9;
+ public const int R8Usr = 8;
+ public const int R9Usr = 9;
public const int R10Usr = 10;
public const int R11Usr = 11;
public const int R12Usr = 12;
- public const int SpUsr = 13;
- public const int LrUsr = 14;
+ public const int SpUsr = 13;
+ public const int LrUsr = 14;
public const int SpHyp = 15;
@@ -24,13 +24,13 @@ static class RegisterAlias
public const int LrUnd = 22;
public const int SpUnd = 23;
- public const int R8Fiq = 24;
- public const int R9Fiq = 25;
+ public const int R8Fiq = 24;
+ public const int R9Fiq = 25;
public const int R10Fiq = 26;
public const int R11Fiq = 27;
public const int R12Fiq = 28;
- public const int SpFiq = 29;
- public const int LrFiq = 30;
+ public const int SpFiq = 29;
+ public const int LrFiq = 30;
public const int Aarch32Sp = 13;
public const int Aarch32Lr = 14;
@@ -39,4 +39,4 @@ static class RegisterAlias
public const int Lr = 30;
public const int Zr = 31;
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/State/RegisterConsts.cs b/src/ARMeilleure/State/RegisterConsts.cs
index d62940808..b43f8d646 100644
--- a/src/ARMeilleure/State/RegisterConsts.cs
+++ b/src/ARMeilleure/State/RegisterConsts.cs
@@ -2,14 +2,14 @@ namespace ARMeilleure.State
{
static class RegisterConsts
{
- public const int IntRegsCount = 32;
- public const int VecRegsCount = 32;
- public const int FlagsCount = 32;
- public const int FpFlagsCount = 32;
+ public const int IntRegsCount = 32;
+ public const int VecRegsCount = 32;
+ public const int FlagsCount = 32;
+ public const int FpFlagsCount = 32;
public const int IntAndVecRegsCount = IntRegsCount + VecRegsCount;
- public const int FpFlagsOffset = IntRegsCount + VecRegsCount + FlagsCount;
- public const int TotalCount = IntRegsCount + VecRegsCount + FlagsCount + FpFlagsCount;
+ public const int FpFlagsOffset = IntRegsCount + VecRegsCount + FlagsCount;
+ public const int TotalCount = IntRegsCount + VecRegsCount + FlagsCount + FpFlagsCount;
public const int ZeroIndex = 31;
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/State/V128.cs b/src/ARMeilleure/State/V128.cs
index 3fa9f9a99..cbcaddfc2 100644
--- a/src/ARMeilleure/State/V128.cs
+++ b/src/ARMeilleure/State/V128.cs
@@ -13,13 +13,13 @@ public struct V128 : IEquatable
// _e0 & _e1 could be marked as readonly, however they are not readonly because we modify them through the Unsafe
// APIs. This also means that one should be careful when changing the layout of this struct.
- private ulong _e0;
- private ulong _e1;
+ private readonly ulong _e0;
+ private readonly ulong _e1;
///
/// Gets a new with all bits set to zero.
///
- public static V128 Zero => new V128(0, 0);
+ public static V128 Zero => new(0, 0);
///
/// Initializes a new instance of the struct with the specified value
@@ -55,9 +55,9 @@ public V128(float value) : this(value, 0, 0, 0) { }
/// Element 3
public V128(float e0, float e1, float e2, float e3)
{
- _e0 = (ulong)(uint)BitConverter.SingleToInt32Bits(e0) << 0;
+ _e0 = (ulong)(uint)BitConverter.SingleToInt32Bits(e0) << 0;
_e0 |= (ulong)(uint)BitConverter.SingleToInt32Bits(e1) << 32;
- _e1 = (ulong)(uint)BitConverter.SingleToInt32Bits(e2) << 0;
+ _e1 = (ulong)(uint)BitConverter.SingleToInt32Bits(e2) << 0;
_e1 |= (ulong)(uint)BitConverter.SingleToInt32Bits(e3) << 32;
}
@@ -98,9 +98,9 @@ public V128(int e0, int e1, int e2, int e3) : this((uint)e0, (uint)e1, (uint)e2,
/// Element 3
public V128(uint e0, uint e1, uint e2, uint e3)
{
- _e0 = (ulong)e0 << 0;
+ _e0 = (ulong)e0 << 0;
_e0 |= (ulong)e1 << 32;
- _e1 = (ulong)e2 << 0;
+ _e1 = (ulong)e2 << 0;
_e1 |= (ulong)e3 << 32;
}
@@ -137,7 +137,9 @@ public T As() where T : unmanaged
public T Extract(int index) where T : unmanaged
{
if ((uint)index >= GetElementCount())
+ {
ThrowIndexOutOfRange();
+ }
// Performs:
// return *((*T)this + index);
@@ -156,7 +158,9 @@ public T Extract(int index) where T : unmanaged
public void Insert(int index, T value) where T : unmanaged
{
if ((uint)index >= GetElementCount())
+ {
ThrowIndexOutOfRange();
+ }
// Performs:
// *((*T)this + index) = value;
@@ -167,13 +171,13 @@ public void Insert(int index, T value) where T : unmanaged
/// Returns a new array which represents the .
///
/// A new array which represents the
- public byte[] ToArray()
+ public readonly byte[] ToArray()
{
- byte[] data = new byte[16];
+ byte[] data = new byte[16];
Span span = data;
BitConverter.TryWriteBytes(span, _e0);
- BitConverter.TryWriteBytes(span.Slice(8), _e1);
+ BitConverter.TryWriteBytes(span[8..], _e1);
return data;
}
@@ -225,7 +229,7 @@ public byte[] ToArray()
///
/// Target
/// Result of not operation
- public static V128 operator ~(V128 x) => new V128(~x._e0, ~x._e1);
+ public static V128 operator ~(V128 x) => new(~x._e0, ~x._e1);
///
/// Performs a bitwise and on the specified instances.
@@ -233,7 +237,7 @@ public byte[] ToArray()
/// First instance
/// Second instance
/// Result of and operation
- public static V128 operator &(V128 x, V128 y) => new V128(x._e0 & y._e0, x._e1 & y._e1);
+ public static V128 operator &(V128 x, V128 y) => new(x._e0 & y._e0, x._e1 & y._e1);
///
/// Performs a bitwise or on the specified instances.
@@ -241,7 +245,7 @@ public byte[] ToArray()
/// First instance
/// Second instance
/// Result of or operation
- public static V128 operator |(V128 x, V128 y) => new V128(x._e0 | y._e0, x._e1 | y._e1);
+ public static V128 operator |(V128 x, V128 y) => new(x._e0 | y._e0, x._e1 | y._e1);
///
/// Performs a bitwise exlusive or on the specified instances.
@@ -249,7 +253,7 @@ public byte[] ToArray()
/// First instance
/// Second instance
/// Result of exclusive or operation
- public static V128 operator ^(V128 x, V128 y) => new V128(x._e0 ^ y._e0, x._e1 ^ y._e1);
+ public static V128 operator ^(V128 x, V128 y) => new(x._e0 ^ y._e0, x._e1 ^ y._e1);
///
/// Determines if the specified instances are equal.
@@ -272,7 +276,7 @@ public byte[] ToArray()
///
/// Other instance
/// true if equal; otherwise false
- public bool Equals(V128 other)
+ public readonly bool Equals(V128 other)
{
return other._e0 == _e0 && other._e1 == _e1;
}
@@ -282,24 +286,24 @@ public bool Equals(V128 other)
///
/// Other instance
/// true if equal; otherwise false
- public override bool Equals(object obj)
+ public readonly override bool Equals(object obj)
{
return obj is V128 vector && Equals(vector);
}
///
- public override int GetHashCode()
+ public readonly override int GetHashCode()
{
return HashCode.Combine(_e0, _e1);
}
///
- public override string ToString()
+ public readonly override string ToString()
{
return $"0x{_e1:X16}{_e0:X16}";
}
- private uint GetElementCount() where T : unmanaged
+ private static uint GetElementCount() where T : unmanaged
{
return (uint)(Unsafe.SizeOf() / Unsafe.SizeOf());
}
@@ -309,4 +313,4 @@ private static void ThrowIndexOutOfRange()
throw new ArgumentOutOfRangeException("index");
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Statistics.cs b/src/ARMeilleure/Statistics.cs
index fbc647082..2f873bcfa 100644
--- a/src/ARMeilleure/Statistics.cs
+++ b/src/ARMeilleure/Statistics.cs
@@ -1,4 +1,6 @@
+#if M_PROFILE
using System;
+#endif
using System.Collections.Concurrent;
using System.Collections.Generic;
using System.Diagnostics;
@@ -11,12 +13,12 @@ public static class Statistics
{
private const int ReportMaxFunctions = 100;
-#pragma warning disable CS0169
+#if M_PROFILE
[ThreadStatic]
private static Stopwatch _executionTimer;
-#pragma warning restore CS0169
+#endif
- private static ConcurrentDictionary _ticksPerFunction;
+ private static readonly ConcurrentDictionary _ticksPerFunction;
static Statistics()
{
@@ -47,7 +49,7 @@ internal static void StopTimer(ulong funcAddr)
long ticks = _executionTimer.ElapsedTicks;
- _ticksPerFunction.AddOrUpdate(funcAddr, ticks, (key, oldTicks) => oldTicks + ticks);
+ TicksPerFunction.AddOrUpdate(funcAddr, ticks, (key, oldTicks) => oldTicks + ticks);
#endif
}
@@ -69,7 +71,7 @@ public static string GetReport()
{
int count = 0;
- StringBuilder sb = new StringBuilder();
+ StringBuilder sb = new();
sb.AppendLine(" Function address | Time");
sb.AppendLine("--------------------------");
@@ -91,4 +93,4 @@ public static string GetReport()
return sb.ToString();
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/ArmEmitterContext.cs b/src/ARMeilleure/Translation/ArmEmitterContext.cs
index 565d2aada..e24074739 100644
--- a/src/ARMeilleure/Translation/ArmEmitterContext.cs
+++ b/src/ARMeilleure/Translation/ArmEmitterContext.cs
@@ -55,7 +55,7 @@ public Block CurrBlock
public Aarch32Mode Mode { get; }
private int _ifThenBlockStateIndex = 0;
- private Condition[] _ifThenBlockState = { };
+ private Condition[] _ifThenBlockState = Array.Empty();
public bool IsInIfThenBlock => _ifThenBlockStateIndex < _ifThenBlockState.Length;
public Condition CurrentIfThenBlockCond => _ifThenBlockState[_ifThenBlockStateIndex];
@@ -96,7 +96,7 @@ public override Operand Call(MethodInfo info, params Operand[] callArgs)
OperandType returnType = GetOperandType(info.ReturnType);
- Symbol symbol = new Symbol(SymbolType.DelegateTable, (ulong)index);
+ Symbol symbol = new(SymbolType.DelegateTable, (ulong)index);
Symbols.Add((ulong)funcPtr.ToInt64(), info.Name);
@@ -219,6 +219,7 @@ public Operand TryGetComparisonResult(Condition condition)
{
switch (condition)
{
+#pragma warning disable IDE0055 // Disable formatting
case Condition.Eq: return ICompareEqual (n, m);
case Condition.Ne: return ICompareNotEqual (n, m);
case Condition.GeUn: return ICompareGreaterOrEqualUI(n, m);
@@ -229,6 +230,7 @@ public Operand TryGetComparisonResult(Condition condition)
case Condition.Lt: return ICompareLess (n, m);
case Condition.Gt: return ICompareGreater (n, m);
case Condition.Le: return ICompareLessOrEqual (n, m);
+#pragma warning restore IDE0055
}
}
else if (cmpName == InstName.Adds && _optOpLastCompare is IOpCodeAluImm op)
@@ -253,12 +255,14 @@ public Operand TryGetComparisonResult(Condition condition)
switch (condition)
{
+#pragma warning disable IDE0055 // Disable formatting
case Condition.Eq: return ICompareEqual (n, m);
case Condition.Ne: return ICompareNotEqual (n, m);
case Condition.Ge: return ICompareGreaterOrEqual(n, m);
case Condition.Lt: return ICompareLess (n, m);
case Condition.Gt: return ICompareGreater (n, m);
case Condition.Le: return ICompareLessOrEqual (n, m);
+#pragma warning restore IDE0055
}
}
@@ -279,4 +283,4 @@ public void AdvanceIfThenBlockState()
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/Cache/CacheEntry.cs b/src/ARMeilleure/Translation/Cache/CacheEntry.cs
index dc5503b18..25b06f781 100644
--- a/src/ARMeilleure/Translation/Cache/CacheEntry.cs
+++ b/src/ARMeilleure/Translation/Cache/CacheEntry.cs
@@ -7,14 +7,14 @@ namespace ARMeilleure.Translation.Cache
readonly struct CacheEntry : IComparable
{
public int Offset { get; }
- public int Size { get; }
+ public int Size { get; }
public UnwindInfo UnwindInfo { get; }
public CacheEntry(int offset, int size, UnwindInfo unwindInfo)
{
- Offset = offset;
- Size = size;
+ Offset = offset;
+ Size = size;
UnwindInfo = unwindInfo;
}
@@ -23,4 +23,4 @@ public int CompareTo([AllowNull] CacheEntry other)
return Offset.CompareTo(other.Offset);
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs b/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs
index 4c22de40e..f36bf7a3d 100644
--- a/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs
+++ b/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
using System.Collections.Generic;
using System.Diagnostics.CodeAnalysis;
@@ -23,7 +23,7 @@ public int CompareTo([AllowNull] MemoryBlock other)
}
}
- private readonly List _blocks = new List();
+ private readonly List _blocks = new();
public CacheMemoryAllocator(int capacity)
{
diff --git a/src/ARMeilleure/Translation/Cache/JitCache.cs b/src/ARMeilleure/Translation/Cache/JitCache.cs
index f496a8e9c..e2b5e2d10 100644
--- a/src/ARMeilleure/Translation/Cache/JitCache.cs
+++ b/src/ARMeilleure/Translation/Cache/JitCache.cs
@@ -2,17 +2,19 @@
using ARMeilleure.CodeGen.Unwinding;
using ARMeilleure.Memory;
using ARMeilleure.Native;
+using Ryujinx.Memory;
using System;
using System.Collections.Generic;
using System.Diagnostics;
using System.Runtime.InteropServices;
+using System.Runtime.Versioning;
namespace ARMeilleure.Translation.Cache
{
- static class JitCache
+ static partial class JitCache
{
- private const int PageSize = 4 * 1024;
- private const int PageMask = PageSize - 1;
+ private static readonly int _pageSize = (int)MemoryBlock.GetPageSize();
+ private static readonly int _pageMask = _pageSize - 1;
private const int CodeAlignment = 4; // Bytes.
private const int CacheSize = 2047 * 1024 * 1024;
@@ -22,27 +24,41 @@ static class JitCache
private static CacheMemoryAllocator _cacheAllocator;
- private static readonly List _cacheEntries = new List();
+ private static readonly List _cacheEntries = new();
- private static readonly object _lock = new object();
+ private static readonly object _lock = new();
private static bool _initialized;
+ [SupportedOSPlatform("windows")]
+ [LibraryImport("kernel32.dll", SetLastError = true)]
+ public static partial IntPtr FlushInstructionCache(IntPtr hProcess, IntPtr lpAddress, UIntPtr dwSize);
+
public static void Initialize(IJitMemoryAllocator allocator)
{
- if (_initialized) return;
+ if (_initialized)
+ {
+ return;
+ }
lock (_lock)
{
- if (_initialized) return;
+ if (_initialized)
+ {
+ return;
+ }
_jitRegion = new ReservedRegion(allocator, CacheSize);
- _jitCacheInvalidator = new JitCacheInvalidation(allocator);
+
+ if (!OperatingSystem.IsWindows() && !OperatingSystem.IsMacOS())
+ {
+ _jitCacheInvalidator = new JitCacheInvalidation(allocator);
+ }
_cacheAllocator = new CacheMemoryAllocator(CacheSize);
if (OperatingSystem.IsWindows())
{
- JitUnwindWindows.InstallFunctionTableHandler(_jitRegion.Pointer, CacheSize, _jitRegion.Pointer + Allocate(PageSize));
+ JitUnwindWindows.InstallFunctionTableHandler(_jitRegion.Pointer, CacheSize, _jitRegion.Pointer + Allocate(_pageSize));
}
_initialized = true;
@@ -65,7 +81,7 @@ public static IntPtr Map(CompiledFunction func)
{
unsafe
{
- fixed (byte *codePtr = code)
+ fixed (byte* codePtr = code)
{
JitSupportDarwin.Copy(funcPtr, (IntPtr)codePtr, (ulong)code.Length);
}
@@ -77,7 +93,14 @@ public static IntPtr Map(CompiledFunction func)
Marshal.Copy(code, 0, funcPtr, code.Length);
ReprotectAsExecutable(funcOffset, code.Length);
- _jitCacheInvalidator.Invalidate(funcPtr, (ulong)code.Length);
+ if (OperatingSystem.IsWindows() && RuntimeInformation.ProcessArchitecture == Architecture.Arm64)
+ {
+ FlushInstructionCache(Process.GetCurrentProcess().Handle, funcPtr, (UIntPtr)code.Length);
+ }
+ else
+ {
+ _jitCacheInvalidator?.Invalidate(funcPtr, (ulong)code.Length);
+ }
}
Add(funcOffset, code.Length, func.UnwindInfo);
@@ -94,12 +117,11 @@ public static void Unmap(IntPtr pointer)
int funcOffset = (int)(pointer.ToInt64() - _jitRegion.Pointer.ToInt64());
- bool result = TryFind(funcOffset, out CacheEntry entry);
- Debug.Assert(result);
-
- _cacheAllocator.Free(funcOffset, AlignCodeSize(entry.Size));
-
- Remove(funcOffset);
+ if (TryFind(funcOffset, out CacheEntry entry, out int entryIndex) && entry.Offset == funcOffset)
+ {
+ _cacheAllocator.Free(funcOffset, AlignCodeSize(entry.Size));
+ _cacheEntries.RemoveAt(entryIndex);
+ }
}
}
@@ -107,8 +129,8 @@ private static void ReprotectAsWritable(int offset, int size)
{
int endOffs = offset + size;
- int regionStart = offset & ~PageMask;
- int regionEnd = (endOffs + PageMask) & ~PageMask;
+ int regionStart = offset & ~_pageMask;
+ int regionEnd = (endOffs + _pageMask) & ~_pageMask;
_jitRegion.Block.MapAsRwx((ulong)regionStart, (ulong)(regionEnd - regionStart));
}
@@ -117,8 +139,8 @@ private static void ReprotectAsExecutable(int offset, int size)
{
int endOffs = offset + size;
- int regionStart = offset & ~PageMask;
- int regionEnd = (endOffs + PageMask) & ~PageMask;
+ int regionStart = offset & ~_pageMask;
+ int regionEnd = (endOffs + _pageMask) & ~_pageMask;
_jitRegion.Block.MapAsRx((ulong)regionStart, (ulong)(regionEnd - regionStart));
}
@@ -146,7 +168,7 @@ private static int AlignCodeSize(int codeSize)
private static void Add(int offset, int size, UnwindInfo unwindInfo)
{
- CacheEntry entry = new CacheEntry(offset, size, unwindInfo);
+ CacheEntry entry = new(offset, size, unwindInfo);
int index = _cacheEntries.BinarySearch(entry);
@@ -158,22 +180,7 @@ private static void Add(int offset, int size, UnwindInfo unwindInfo)
_cacheEntries.Insert(index, entry);
}
- private static void Remove(int offset)
- {
- int index = _cacheEntries.BinarySearch(new CacheEntry(offset, 0, default));
-
- if (index < 0)
- {
- index = ~index - 1;
- }
-
- if (index >= 0)
- {
- _cacheEntries.RemoveAt(index);
- }
- }
-
- public static bool TryFind(int offset, out CacheEntry entry)
+ public static bool TryFind(int offset, out CacheEntry entry, out int entryIndex)
{
lock (_lock)
{
@@ -187,12 +194,14 @@ public static bool TryFind(int offset, out CacheEntry entry)
if (index >= 0)
{
entry = _cacheEntries[index];
+ entryIndex = index;
return true;
}
}
entry = default;
+ entryIndex = 0;
return false;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs b/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs
index ec2ae73bb..3aa2e19f1 100644
--- a/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs
+++ b/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs
@@ -6,7 +6,7 @@ namespace ARMeilleure.Translation.Cache
{
class JitCacheInvalidation
{
- private static int[] _invalidationCode = new int[]
+ private static readonly int[] _invalidationCode = new int[]
{
unchecked((int)0xd53b0022), // mrs x2, ctr_el0
unchecked((int)0xd3504c44), // ubfx x4, x2, #16, #4
@@ -40,15 +40,15 @@ class JitCacheInvalidation
private delegate void InvalidateCache(ulong start, ulong end);
- private InvalidateCache _invalidateCache;
- private ReservedRegion _invalidateCacheCodeRegion;
+ private readonly InvalidateCache _invalidateCache;
+ private readonly ReservedRegion _invalidateCacheCodeRegion;
private readonly bool _needsInvalidation;
public JitCacheInvalidation(IJitMemoryAllocator allocator)
{
- // On macOS, a different path is used to write to the JIT cache, which does the invalidation.
- if (!OperatingSystem.IsMacOS() && RuntimeInformation.ProcessArchitecture == Architecture.Arm64)
+ // On macOS and Windows, a different path is used to write to the JIT cache, which does the invalidation.
+ if (RuntimeInformation.ProcessArchitecture == Architecture.Arm64)
{
ulong size = (ulong)_invalidationCode.Length * sizeof(int);
ulong mask = (ulong)ReservedRegion.DefaultGranularity - 1;
@@ -76,4 +76,4 @@ public void Invalidate(IntPtr basePointer, ulong size)
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs b/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs
index 77727bf16..3957a7559 100644
--- a/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs
+++ b/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs
@@ -29,15 +29,15 @@ private struct UnwindInfo
private enum UnwindOp
{
- PushNonvol = 0,
- AllocLarge = 1,
- AllocSmall = 2,
- SetFpreg = 3,
- SaveNonvol = 4,
+ PushNonvol = 0,
+ AllocLarge = 1,
+ AllocSmall = 2,
+ SetFpreg = 3,
+ SaveNonvol = 4,
SaveNonvolFar = 5,
- SaveXmm128 = 8,
+ SaveXmm128 = 8,
SaveXmm128Far = 9,
- PushMachframe = 10
+ PushMachframe = 10,
}
private unsafe delegate RuntimeFunction* GetRuntimeFunctionCallback(ulong controlPc, IntPtr context);
@@ -95,7 +95,7 @@ public static void InstallFunctionTableHandler(IntPtr codeCachePointer, uint cod
{
int offset = (int)((long)controlPc - context.ToInt64());
- if (!JitCache.TryFind(offset, out CacheEntry funcEntry))
+ if (!JitCache.TryFind(offset, out CacheEntry funcEntry, out _))
{
return null; // Not found.
}
@@ -111,72 +111,73 @@ public static void InstallFunctionTableHandler(IntPtr codeCachePointer, uint cod
switch (entry.PseudoOp)
{
case UnwindPseudoOp.SaveXmm128:
- {
- int stackOffset = entry.StackOffsetOrAllocSize;
-
- Debug.Assert(stackOffset % 16 == 0);
-
- if (stackOffset <= 0xFFFF0)
- {
- _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128, entry.PrologOffset, entry.RegIndex);
- _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset / 16);
- }
- else
{
- _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128Far, entry.PrologOffset, entry.RegIndex);
- _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 0);
- _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 16);
+ int stackOffset = entry.StackOffsetOrAllocSize;
+
+ Debug.Assert(stackOffset % 16 == 0);
+
+ if (stackOffset <= 0xFFFF0)
+ {
+ _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128, entry.PrologOffset, entry.RegIndex);
+ _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset / 16);
+ }
+ else
+ {
+ _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128Far, entry.PrologOffset, entry.RegIndex);
+ _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 0);
+ _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 16);
+ }
+
+ break;
}
- break;
- }
-
case UnwindPseudoOp.AllocStack:
- {
- int allocSize = entry.StackOffsetOrAllocSize;
-
- Debug.Assert(allocSize % 8 == 0);
-
- if (allocSize <= 128)
{
- _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocSmall, entry.PrologOffset, (allocSize / 8) - 1);
- }
- else if (allocSize <= 0x7FFF8)
- {
- _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 0);
- _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize / 8);
- }
- else
- {
- _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 1);
- _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 0);
- _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 16);
+ int allocSize = entry.StackOffsetOrAllocSize;
+
+ Debug.Assert(allocSize % 8 == 0);
+
+ if (allocSize <= 128)
+ {
+ _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocSmall, entry.PrologOffset, (allocSize / 8) - 1);
+ }
+ else if (allocSize <= 0x7FFF8)
+ {
+ _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 0);
+ _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize / 8);
+ }
+ else
+ {
+ _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 1);
+ _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 0);
+ _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 16);
+ }
+
+ break;
}
- break;
- }
-
case UnwindPseudoOp.PushReg:
- {
- _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.PushNonvol, entry.PrologOffset, entry.RegIndex);
+ {
+ _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.PushNonvol, entry.PrologOffset, entry.RegIndex);
- break;
- }
+ break;
+ }
- default: throw new NotImplementedException($"({nameof(entry.PseudoOp)} = {entry.PseudoOp})");
+ default:
+ throw new NotImplementedException($"({nameof(entry.PseudoOp)} = {entry.PseudoOp})");
}
}
Debug.Assert(codeIndex <= MaxUnwindCodesArraySize);
- _unwindInfo->VersionAndFlags = 1; // Flags: The function has no handler.
- _unwindInfo->SizeOfProlog = (byte)unwindInfo.PrologSize;
+ _unwindInfo->VersionAndFlags = 1; // Flags: The function has no handler.
+ _unwindInfo->SizeOfProlog = (byte)unwindInfo.PrologSize;
_unwindInfo->CountOfUnwindCodes = (byte)codeIndex;
- _unwindInfo->FrameRegister = 0;
+ _unwindInfo->FrameRegister = 0;
_runtimeFunction->BeginAddress = (uint)funcEntry.Offset;
- _runtimeFunction->EndAddress = (uint)(funcEntry.Offset + funcEntry.Size);
- _runtimeFunction->UnwindData = (uint)_sizeOfRuntimeFunction;
+ _runtimeFunction->EndAddress = (uint)(funcEntry.Offset + funcEntry.Size);
+ _runtimeFunction->UnwindData = (uint)_sizeOfRuntimeFunction;
return _runtimeFunction;
}
@@ -186,4 +187,4 @@ private static ushort PackUnwindOp(UnwindOp op, int prologOffset, int opInfo)
return (ushort)(prologOffset | ((int)op << 8) | (opInfo << 12));
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/Compiler.cs b/src/ARMeilleure/Translation/Compiler.cs
index d4aa5cd96..293e63496 100644
--- a/src/ARMeilleure/Translation/Compiler.cs
+++ b/src/ARMeilleure/Translation/Compiler.cs
@@ -11,10 +11,10 @@ static class Compiler
{
public static CompiledFunction Compile(
ControlFlowGraph cfg,
- OperandType[] argTypes,
- OperandType retType,
- CompilerOptions options,
- Architecture target)
+ OperandType[] argTypes,
+ OperandType retType,
+ CompilerOptions options,
+ Architecture target)
{
CompilerContext cctx = new(cfg, argTypes, retType, options);
@@ -65,4 +65,4 @@ public static CompiledFunction Compile(
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/CompilerContext.cs b/src/ARMeilleure/Translation/CompilerContext.cs
index 510dec58f..5b10686b3 100644
--- a/src/ARMeilleure/Translation/CompilerContext.cs
+++ b/src/ARMeilleure/Translation/CompilerContext.cs
@@ -6,21 +6,21 @@ readonly struct CompilerContext
{
public ControlFlowGraph Cfg { get; }
- public OperandType[] FuncArgTypes { get; }
- public OperandType FuncReturnType { get; }
+ public OperandType[] FuncArgTypes { get; }
+ public OperandType FuncReturnType { get; }
public CompilerOptions Options { get; }
public CompilerContext(
ControlFlowGraph cfg,
- OperandType[] funcArgTypes,
- OperandType funcReturnType,
- CompilerOptions options)
+ OperandType[] funcArgTypes,
+ OperandType funcReturnType,
+ CompilerOptions options)
{
- Cfg = cfg;
- FuncArgTypes = funcArgTypes;
+ Cfg = cfg;
+ FuncArgTypes = funcArgTypes;
FuncReturnType = funcReturnType;
- Options = options;
+ Options = options;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/CompilerOptions.cs b/src/ARMeilleure/Translation/CompilerOptions.cs
index 0a07ed4ab..d454de7f2 100644
--- a/src/ARMeilleure/Translation/CompilerOptions.cs
+++ b/src/ARMeilleure/Translation/CompilerOptions.cs
@@ -5,13 +5,13 @@ namespace ARMeilleure.Translation
[Flags]
enum CompilerOptions
{
- None = 0,
- SsaForm = 1 << 0,
- Optimize = 1 << 1,
- Lsra = 1 << 2,
+ None = 0,
+ SsaForm = 1 << 0,
+ Optimize = 1 << 1,
+ Lsra = 1 << 2,
Relocatable = 1 << 3,
MediumCq = SsaForm | Optimize,
- HighCq = SsaForm | Optimize | Lsra
+ HighCq = SsaForm | Optimize | Lsra,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/ControlFlowGraph.cs b/src/ARMeilleure/Translation/ControlFlowGraph.cs
index c935f1521..3ead49c93 100644
--- a/src/ARMeilleure/Translation/ControlFlowGraph.cs
+++ b/src/ARMeilleure/Translation/ControlFlowGraph.cs
@@ -130,7 +130,7 @@ private void RemoveUnreachableBlocks(IntrusiveList blocks)
public BasicBlock SplitEdge(BasicBlock predecessor, BasicBlock successor)
{
- BasicBlock splitBlock = new BasicBlock(Blocks.Count);
+ BasicBlock splitBlock = new(Blocks.Count);
for (int i = 0; i < predecessor.SuccessorsCount; i++)
{
@@ -152,4 +152,4 @@ public BasicBlock SplitEdge(BasicBlock predecessor, BasicBlock successor)
return splitBlock;
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/DelegateHelper.cs b/src/ARMeilleure/Translation/DelegateHelper.cs
deleted file mode 100644
index 43a39bab0..000000000
--- a/src/ARMeilleure/Translation/DelegateHelper.cs
+++ /dev/null
@@ -1,104 +0,0 @@
-using System;
-using System.Collections.Generic;
-using System.Linq;
-using System.Reflection;
-using System.Reflection.Emit;
-
-namespace ARMeilleure.Translation
-{
- static class DelegateHelper
- {
- private const string DelegateTypesAssemblyName = "JitDelegateTypes";
-
- private static readonly ModuleBuilder _modBuilder;
-
- private static readonly Dictionary _delegateTypesCache;
-
- static DelegateHelper()
- {
- AssemblyBuilder asmBuilder = AssemblyBuilder.DefineDynamicAssembly(new AssemblyName(DelegateTypesAssemblyName), AssemblyBuilderAccess.Run);
-
- _modBuilder = asmBuilder.DefineDynamicModule(DelegateTypesAssemblyName);
-
- _delegateTypesCache = new Dictionary();
- }
-
- public static Delegate GetDelegate(MethodInfo info)
- {
- ArgumentNullException.ThrowIfNull(info);
-
- Type[] parameters = info.GetParameters().Select(pI => pI.ParameterType).ToArray();
- Type returnType = info.ReturnType;
-
- Type delegateType = GetDelegateType(parameters, returnType);
-
- return Delegate.CreateDelegate(delegateType, info);
- }
-
- private static Type GetDelegateType(Type[] parameters, Type returnType)
- {
- string key = GetFunctionSignatureKey(parameters, returnType);
-
- if (!_delegateTypesCache.TryGetValue(key, out Type delegateType))
- {
- delegateType = MakeDelegateType(parameters, returnType, key);
-
- _delegateTypesCache.TryAdd(key, delegateType);
- }
-
- return delegateType;
- }
-
- private static string GetFunctionSignatureKey(Type[] parameters, Type returnType)
- {
- string sig = GetTypeName(returnType);
-
- foreach (Type type in parameters)
- {
- sig += '_' + GetTypeName(type);
- }
-
- return sig;
- }
-
- private static string GetTypeName(Type type)
- {
- return type.FullName.Replace(".", string.Empty);
- }
-
- private const MethodAttributes CtorAttributes =
- MethodAttributes.RTSpecialName |
- MethodAttributes.HideBySig |
- MethodAttributes.Public;
-
- private const TypeAttributes DelegateTypeAttributes =
- TypeAttributes.Class |
- TypeAttributes.Public |
- TypeAttributes.Sealed |
- TypeAttributes.AnsiClass |
- TypeAttributes.AutoClass;
-
- private const MethodImplAttributes ImplAttributes =
- MethodImplAttributes.Runtime |
- MethodImplAttributes.Managed;
-
- private const MethodAttributes InvokeAttributes =
- MethodAttributes.Public |
- MethodAttributes.HideBySig |
- MethodAttributes.NewSlot |
- MethodAttributes.Virtual;
-
- private static readonly Type[] _delegateCtorSignature = { typeof(object), typeof(IntPtr) };
-
- private static Type MakeDelegateType(Type[] parameters, Type returnType, string name)
- {
- TypeBuilder builder = _modBuilder.DefineType(name, DelegateTypeAttributes, typeof(MulticastDelegate));
-
- builder.DefineConstructor(CtorAttributes, CallingConventions.Standard, _delegateCtorSignature).SetImplementationFlags(ImplAttributes);
-
- builder.DefineMethod("Invoke", InvokeAttributes, returnType, parameters).SetImplementationFlags(ImplAttributes);
-
- return builder.CreateTypeInfo();
- }
- }
-}
diff --git a/src/ARMeilleure/Translation/DelegateInfo.cs b/src/ARMeilleure/Translation/DelegateInfo.cs
index 36320ac31..27479a003 100644
--- a/src/ARMeilleure/Translation/DelegateInfo.cs
+++ b/src/ARMeilleure/Translation/DelegateInfo.cs
@@ -5,7 +5,9 @@ namespace ARMeilleure.Translation
{
class DelegateInfo
{
+#pragma warning disable IDE0052 // Remove unread private member
private readonly Delegate _dlg; // Ensure that this delegate will not be garbage collected.
+#pragma warning restore IDE0052
public IntPtr FuncPtr { get; }
diff --git a/src/ARMeilleure/Translation/Delegates.cs b/src/ARMeilleure/Translation/Delegates.cs
index 55f1e5145..63db789df 100644
--- a/src/ARMeilleure/Translation/Delegates.cs
+++ b/src/ARMeilleure/Translation/Delegates.cs
@@ -1,4 +1,5 @@
using ARMeilleure.Instructions;
+using ARMeilleure.State;
using System;
using System.Collections.Generic;
using System.Reflection;
@@ -63,11 +64,9 @@ public static int GetDelegateIndex(MethodInfo info)
return index;
}
- private static void SetDelegateInfo(MethodInfo info)
+ private static void SetDelegateInfo(Delegate dlg)
{
- string key = GetKey(info);
-
- Delegate dlg = DelegateHelper.GetDelegate(info);
+ string key = GetKey(dlg.Method);
_delegates.Add(key, new DelegateInfo(dlg)); // ArgumentException (key).
}
@@ -83,179 +82,354 @@ static Delegates()
{
_delegates = new SortedList();
- SetDelegateInfo(typeof(Math).GetMethod(nameof(Math.Abs), new Type[] { typeof(double) }));
- SetDelegateInfo(typeof(Math).GetMethod(nameof(Math.Ceiling), new Type[] { typeof(double) }));
- SetDelegateInfo(typeof(Math).GetMethod(nameof(Math.Floor), new Type[] { typeof(double) }));
- SetDelegateInfo(typeof(Math).GetMethod(nameof(Math.Round), new Type[] { typeof(double), typeof(MidpointRounding) }));
- SetDelegateInfo(typeof(Math).GetMethod(nameof(Math.Truncate), new Type[] { typeof(double) }));
-
- SetDelegateInfo(typeof(MathF).GetMethod(nameof(MathF.Abs), new Type[] { typeof(float) }));
- SetDelegateInfo(typeof(MathF).GetMethod(nameof(MathF.Ceiling), new Type[] { typeof(float) }));
- SetDelegateInfo(typeof(MathF).GetMethod(nameof(MathF.Floor), new Type[] { typeof(float) }));
- SetDelegateInfo(typeof(MathF).GetMethod(nameof(MathF.Round), new Type[] { typeof(float), typeof(MidpointRounding) }));
- SetDelegateInfo(typeof(MathF).GetMethod(nameof(MathF.Truncate), new Type[] { typeof(float) }));
-
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.Break)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.CheckSynchronization)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.EnqueueForRejit)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntfrqEl0)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntvctEl0)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFunctionAddress)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.InvalidateCacheLine)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SignalMemoryTracking)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SupervisorCall)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.Undefined)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)));
- SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)));
-
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.CountLeadingSigns)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.CountLeadingZeros)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32b)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32cb)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32ch)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32cw)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32cx)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32h)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32w)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32x)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Decrypt)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Encrypt)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.FixedRotate)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.HashChoose)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.HashLower)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.HashMajority)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.HashParity)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.HashUpper)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.InverseMixColumns)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.MixColumns)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.PolynomialMult64_128)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS64)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU64)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS32)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToS64)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU32)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF64ToU64)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha1SchedulePart1)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha1SchedulePart2)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart1)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart2)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShrImm64)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)));
- SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShrImm64)));
-
- SetDelegateInfo(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)));
- SetDelegateInfo(typeof(SoftFloat16_64).GetMethod(nameof(SoftFloat16_64.FPConvert)));
-
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPAdd)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPAddFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompare)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareEQ)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareEQFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareGE)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareGEFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareGT)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareGTFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareLE)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareLEFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareLT)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPCompareLTFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPDiv)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMax)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMaxFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMaxNum)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMaxNumFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMin)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMinFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMinNum)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMinNumFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMul)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMulFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMulAdd)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMulAddFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMulSub)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMulSubFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPMulX)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPNegMulAdd)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPNegMulSub)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRecipEstimate)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRecipEstimateFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRecipStep))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRecipStepFused)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRecpX)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRSqrtEstimate)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRSqrtEstimateFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRSqrtStep))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPRSqrtStepFused)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPSqrt)));
- SetDelegateInfo(typeof(SoftFloat32).GetMethod(nameof(SoftFloat32.FPSub)));
-
- SetDelegateInfo(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)));
-
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPAdd)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPAddFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompare)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareEQ)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareEQFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareGE)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareGEFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareGT)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareGTFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareLE)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareLEFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareLT)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPCompareLTFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPDiv)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMax)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMaxFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMaxNum)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMaxNumFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMin)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMinFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMinNum)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMinNumFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMul)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMulFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMulAdd)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMulAddFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMulSub)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMulSubFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPMulX)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPNegMulAdd)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPNegMulSub)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRecipEstimate)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRecipEstimateFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRecipStep))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRecipStepFused)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRecpX)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRSqrtEstimate)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRSqrtEstimateFpscr))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRSqrtStep))); // A32 only.
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPRSqrtStepFused)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPSqrt)));
- SetDelegateInfo(typeof(SoftFloat64).GetMethod(nameof(SoftFloat64.FPSub)));
-
- SetDelegateInfo(typeof(SoftFloat64_16).GetMethod(nameof(SoftFloat64_16.FPConvert)));
+ SetDelegateInfo(new MathAbs(Math.Abs));
+ SetDelegateInfo(new MathCeiling(Math.Ceiling));
+ SetDelegateInfo(new MathFloor(Math.Floor));
+ SetDelegateInfo(new MathRound(Math.Round));
+ SetDelegateInfo(new MathTruncate(Math.Truncate));
+
+ SetDelegateInfo(new MathFAbs(MathF.Abs));
+ SetDelegateInfo(new MathFCeiling(MathF.Ceiling));
+ SetDelegateInfo(new MathFFloor(MathF.Floor));
+ SetDelegateInfo(new MathFRound(MathF.Round));
+ SetDelegateInfo(new MathFTruncate(MathF.Truncate));
+
+ SetDelegateInfo(new NativeInterfaceBreak(NativeInterface.Break));
+ SetDelegateInfo(new NativeInterfaceCheckSynchronization(NativeInterface.CheckSynchronization));
+ SetDelegateInfo(new NativeInterfaceEnqueueForRejit(NativeInterface.EnqueueForRejit));
+ SetDelegateInfo(new NativeInterfaceGetCntfrqEl0(NativeInterface.GetCntfrqEl0));
+ SetDelegateInfo(new NativeInterfaceGetCntpctEl0(NativeInterface.GetCntpctEl0));
+ SetDelegateInfo(new NativeInterfaceGetCntvctEl0(NativeInterface.GetCntvctEl0));
+ SetDelegateInfo(new NativeInterfaceGetCtrEl0(NativeInterface.GetCtrEl0));
+ SetDelegateInfo(new NativeInterfaceGetDczidEl0(NativeInterface.GetDczidEl0));
+ SetDelegateInfo(new NativeInterfaceGetFunctionAddress(NativeInterface.GetFunctionAddress));
+ SetDelegateInfo(new NativeInterfaceInvalidateCacheLine(NativeInterface.InvalidateCacheLine));
+ SetDelegateInfo(new NativeInterfaceReadByte(NativeInterface.ReadByte));
+ SetDelegateInfo(new NativeInterfaceReadUInt16(NativeInterface.ReadUInt16));
+ SetDelegateInfo(new NativeInterfaceReadUInt32(NativeInterface.ReadUInt32));
+ SetDelegateInfo(new NativeInterfaceReadUInt64(NativeInterface.ReadUInt64));
+ SetDelegateInfo(new NativeInterfaceReadVector128(NativeInterface.ReadVector128));
+ SetDelegateInfo(new NativeInterfaceSignalMemoryTracking(NativeInterface.SignalMemoryTracking));
+ SetDelegateInfo(new NativeInterfaceSupervisorCall(NativeInterface.SupervisorCall));
+ SetDelegateInfo(new NativeInterfaceThrowInvalidMemoryAccess(NativeInterface.ThrowInvalidMemoryAccess));
+ SetDelegateInfo(new NativeInterfaceUndefined(NativeInterface.Undefined));
+ SetDelegateInfo(new NativeInterfaceWriteByte(NativeInterface.WriteByte));
+ SetDelegateInfo(new NativeInterfaceWriteUInt16(NativeInterface.WriteUInt16));
+ SetDelegateInfo(new NativeInterfaceWriteUInt32(NativeInterface.WriteUInt32));
+ SetDelegateInfo(new NativeInterfaceWriteUInt64(NativeInterface.WriteUInt64));
+ SetDelegateInfo(new NativeInterfaceWriteVector128(NativeInterface.WriteVector128));
+
+ SetDelegateInfo(new SoftFallbackCountLeadingSigns(SoftFallback.CountLeadingSigns));
+ SetDelegateInfo(new SoftFallbackCountLeadingZeros(SoftFallback.CountLeadingZeros));
+ SetDelegateInfo(new SoftFallbackCrc32b(SoftFallback.Crc32b));
+ SetDelegateInfo(new SoftFallbackCrc32cb(SoftFallback.Crc32cb));
+ SetDelegateInfo(new SoftFallbackCrc32ch(SoftFallback.Crc32ch));
+ SetDelegateInfo(new SoftFallbackCrc32cw(SoftFallback.Crc32cw));
+ SetDelegateInfo(new SoftFallbackCrc32cx(SoftFallback.Crc32cx));
+ SetDelegateInfo(new SoftFallbackCrc32h(SoftFallback.Crc32h));
+ SetDelegateInfo(new SoftFallbackCrc32w(SoftFallback.Crc32w));
+ SetDelegateInfo(new SoftFallbackCrc32x(SoftFallback.Crc32x));
+ SetDelegateInfo(new SoftFallbackDecrypt(SoftFallback.Decrypt));
+ SetDelegateInfo(new SoftFallbackEncrypt(SoftFallback.Encrypt));
+ SetDelegateInfo(new SoftFallbackFixedRotate(SoftFallback.FixedRotate));
+ SetDelegateInfo(new SoftFallbackHashChoose(SoftFallback.HashChoose));
+ SetDelegateInfo(new SoftFallbackHashLower(SoftFallback.HashLower));
+ SetDelegateInfo(new SoftFallbackHashMajority(SoftFallback.HashMajority));
+ SetDelegateInfo(new SoftFallbackHashParity(SoftFallback.HashParity));
+ SetDelegateInfo(new SoftFallbackHashUpper(SoftFallback.HashUpper));
+ SetDelegateInfo(new SoftFallbackInverseMixColumns(SoftFallback.InverseMixColumns));
+ SetDelegateInfo(new SoftFallbackMixColumns(SoftFallback.MixColumns));
+ SetDelegateInfo(new SoftFallbackPolynomialMult64_128(SoftFallback.PolynomialMult64_128));
+ SetDelegateInfo(new SoftFallbackSatF32ToS32(SoftFallback.SatF32ToS32));
+ SetDelegateInfo(new SoftFallbackSatF32ToS64(SoftFallback.SatF32ToS64));
+ SetDelegateInfo(new SoftFallbackSatF32ToU32(SoftFallback.SatF32ToU32));
+ SetDelegateInfo(new SoftFallbackSatF32ToU64(SoftFallback.SatF32ToU64));
+ SetDelegateInfo(new SoftFallbackSatF64ToS32(SoftFallback.SatF64ToS32));
+ SetDelegateInfo(new SoftFallbackSatF64ToS64(SoftFallback.SatF64ToS64));
+ SetDelegateInfo(new SoftFallbackSatF64ToU32(SoftFallback.SatF64ToU32));
+ SetDelegateInfo(new SoftFallbackSatF64ToU64(SoftFallback.SatF64ToU64));
+ SetDelegateInfo(new SoftFallbackSha1SchedulePart1(SoftFallback.Sha1SchedulePart1));
+ SetDelegateInfo(new SoftFallbackSha1SchedulePart2(SoftFallback.Sha1SchedulePart2));
+ SetDelegateInfo(new SoftFallbackSha256SchedulePart1(SoftFallback.Sha256SchedulePart1));
+ SetDelegateInfo(new SoftFallbackSha256SchedulePart2(SoftFallback.Sha256SchedulePart2));
+ SetDelegateInfo(new SoftFallbackSignedShrImm64(SoftFallback.SignedShrImm64));
+ SetDelegateInfo(new SoftFallbackTbl1(SoftFallback.Tbl1));
+ SetDelegateInfo(new SoftFallbackTbl2(SoftFallback.Tbl2));
+ SetDelegateInfo(new SoftFallbackTbl3(SoftFallback.Tbl3));
+ SetDelegateInfo(new SoftFallbackTbl4(SoftFallback.Tbl4));
+ SetDelegateInfo(new SoftFallbackTbx1(SoftFallback.Tbx1));
+ SetDelegateInfo(new SoftFallbackTbx2(SoftFallback.Tbx2));
+ SetDelegateInfo(new SoftFallbackTbx3(SoftFallback.Tbx3));
+ SetDelegateInfo(new SoftFallbackTbx4(SoftFallback.Tbx4));
+ SetDelegateInfo(new SoftFallbackUnsignedShrImm64(SoftFallback.UnsignedShrImm64));
+
+ SetDelegateInfo(new SoftFloat16_32FPConvert(SoftFloat16_32.FPConvert));
+ SetDelegateInfo(new SoftFloat16_64FPConvert(SoftFloat16_64.FPConvert));
+
+ SetDelegateInfo(new SoftFloat32FPAdd(SoftFloat32.FPAdd));
+ SetDelegateInfo(new SoftFloat32FPAddFpscr(SoftFloat32.FPAddFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPCompare(SoftFloat32.FPCompare));
+ SetDelegateInfo(new SoftFloat32FPCompareEQ(SoftFloat32.FPCompareEQ));
+ SetDelegateInfo(new SoftFloat32FPCompareEQFpscr(SoftFloat32.FPCompareEQFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPCompareGE(SoftFloat32.FPCompareGE));
+ SetDelegateInfo(new SoftFloat32FPCompareGEFpscr(SoftFloat32.FPCompareGEFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPCompareGT(SoftFloat32.FPCompareGT));
+ SetDelegateInfo(new SoftFloat32FPCompareGTFpscr(SoftFloat32.FPCompareGTFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPCompareLE(SoftFloat32.FPCompareLE));
+ SetDelegateInfo(new SoftFloat32FPCompareLEFpscr(SoftFloat32.FPCompareLEFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPCompareLT(SoftFloat32.FPCompareLT));
+ SetDelegateInfo(new SoftFloat32FPCompareLTFpscr(SoftFloat32.FPCompareLTFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPDiv(SoftFloat32.FPDiv));
+ SetDelegateInfo(new SoftFloat32FPMax(SoftFloat32.FPMax));
+ SetDelegateInfo(new SoftFloat32FPMaxFpscr(SoftFloat32.FPMaxFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPMaxNum(SoftFloat32.FPMaxNum));
+ SetDelegateInfo(new SoftFloat32FPMaxNumFpscr(SoftFloat32.FPMaxNumFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPMin(SoftFloat32.FPMin));
+ SetDelegateInfo(new SoftFloat32FPMinFpscr(SoftFloat32.FPMinFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPMinNum(SoftFloat32.FPMinNum));
+ SetDelegateInfo(new SoftFloat32FPMinNumFpscr(SoftFloat32.FPMinNumFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPMul(SoftFloat32.FPMul));
+ SetDelegateInfo(new SoftFloat32FPMulFpscr(SoftFloat32.FPMulFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPMulAdd(SoftFloat32.FPMulAdd));
+ SetDelegateInfo(new SoftFloat32FPMulAddFpscr(SoftFloat32.FPMulAddFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPMulSub(SoftFloat32.FPMulSub));
+ SetDelegateInfo(new SoftFloat32FPMulSubFpscr(SoftFloat32.FPMulSubFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPMulX(SoftFloat32.FPMulX));
+ SetDelegateInfo(new SoftFloat32FPNegMulAdd(SoftFloat32.FPNegMulAdd));
+ SetDelegateInfo(new SoftFloat32FPNegMulSub(SoftFloat32.FPNegMulSub));
+ SetDelegateInfo(new SoftFloat32FPRecipEstimate(SoftFloat32.FPRecipEstimate));
+ SetDelegateInfo(new SoftFloat32FPRecipEstimateFpscr(SoftFloat32.FPRecipEstimateFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPRecipStep(SoftFloat32.FPRecipStep)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPRecipStepFused(SoftFloat32.FPRecipStepFused));
+ SetDelegateInfo(new SoftFloat32FPRecpX(SoftFloat32.FPRecpX));
+ SetDelegateInfo(new SoftFloat32FPRSqrtEstimate(SoftFloat32.FPRSqrtEstimate));
+ SetDelegateInfo(new SoftFloat32FPRSqrtEstimateFpscr(SoftFloat32.FPRSqrtEstimateFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPRSqrtStep(SoftFloat32.FPRSqrtStep)); // A32 only.
+ SetDelegateInfo(new SoftFloat32FPRSqrtStepFused(SoftFloat32.FPRSqrtStepFused));
+ SetDelegateInfo(new SoftFloat32FPSqrt(SoftFloat32.FPSqrt));
+ SetDelegateInfo(new SoftFloat32FPSub(SoftFloat32.FPSub));
+
+ SetDelegateInfo(new SoftFloat32_16FPConvert(SoftFloat32_16.FPConvert));
+
+ SetDelegateInfo(new SoftFloat64FPAdd(SoftFloat64.FPAdd));
+ SetDelegateInfo(new SoftFloat64FPAddFpscr(SoftFloat64.FPAddFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPCompare(SoftFloat64.FPCompare));
+ SetDelegateInfo(new SoftFloat64FPCompareEQ(SoftFloat64.FPCompareEQ));
+ SetDelegateInfo(new SoftFloat64FPCompareEQFpscr(SoftFloat64.FPCompareEQFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPCompareGE(SoftFloat64.FPCompareGE));
+ SetDelegateInfo(new SoftFloat64FPCompareGEFpscr(SoftFloat64.FPCompareGEFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPCompareGT(SoftFloat64.FPCompareGT));
+ SetDelegateInfo(new SoftFloat64FPCompareGTFpscr(SoftFloat64.FPCompareGTFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPCompareLE(SoftFloat64.FPCompareLE));
+ SetDelegateInfo(new SoftFloat64FPCompareLEFpscr(SoftFloat64.FPCompareLEFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPCompareLT(SoftFloat64.FPCompareLT));
+ SetDelegateInfo(new SoftFloat64FPCompareLTFpscr(SoftFloat64.FPCompareLTFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPDiv(SoftFloat64.FPDiv));
+ SetDelegateInfo(new SoftFloat64FPMax(SoftFloat64.FPMax));
+ SetDelegateInfo(new SoftFloat64FPMaxFpscr(SoftFloat64.FPMaxFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPMaxNum(SoftFloat64.FPMaxNum));
+ SetDelegateInfo(new SoftFloat64FPMaxNumFpscr(SoftFloat64.FPMaxNumFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPMin(SoftFloat64.FPMin));
+ SetDelegateInfo(new SoftFloat64FPMinFpscr(SoftFloat64.FPMinFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPMinNum(SoftFloat64.FPMinNum));
+ SetDelegateInfo(new SoftFloat64FPMinNumFpscr(SoftFloat64.FPMinNumFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPMul(SoftFloat64.FPMul));
+ SetDelegateInfo(new SoftFloat64FPMulFpscr(SoftFloat64.FPMulFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPMulAdd(SoftFloat64.FPMulAdd));
+ SetDelegateInfo(new SoftFloat64FPMulAddFpscr(SoftFloat64.FPMulAddFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPMulSub(SoftFloat64.FPMulSub));
+ SetDelegateInfo(new SoftFloat64FPMulSubFpscr(SoftFloat64.FPMulSubFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPMulX(SoftFloat64.FPMulX));
+ SetDelegateInfo(new SoftFloat64FPNegMulAdd(SoftFloat64.FPNegMulAdd));
+ SetDelegateInfo(new SoftFloat64FPNegMulSub(SoftFloat64.FPNegMulSub));
+ SetDelegateInfo(new SoftFloat64FPRecipEstimate(SoftFloat64.FPRecipEstimate));
+ SetDelegateInfo(new SoftFloat64FPRecipEstimateFpscr(SoftFloat64.FPRecipEstimateFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPRecipStep(SoftFloat64.FPRecipStep)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPRecipStepFused(SoftFloat64.FPRecipStepFused));
+ SetDelegateInfo(new SoftFloat64FPRecpX(SoftFloat64.FPRecpX));
+ SetDelegateInfo(new SoftFloat64FPRSqrtEstimate(SoftFloat64.FPRSqrtEstimate));
+ SetDelegateInfo(new SoftFloat64FPRSqrtEstimateFpscr(SoftFloat64.FPRSqrtEstimateFpscr)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPRSqrtStep(SoftFloat64.FPRSqrtStep)); // A32 only.
+ SetDelegateInfo(new SoftFloat64FPRSqrtStepFused(SoftFloat64.FPRSqrtStepFused));
+ SetDelegateInfo(new SoftFloat64FPSqrt(SoftFloat64.FPSqrt));
+ SetDelegateInfo(new SoftFloat64FPSub(SoftFloat64.FPSub));
+
+ SetDelegateInfo(new SoftFloat64_16FPConvert(SoftFloat64_16.FPConvert));
}
+
+ private delegate double MathAbs(double value);
+ private delegate double MathCeiling(double a);
+ private delegate double MathFloor(double d);
+ private delegate double MathRound(double value, MidpointRounding mode);
+ private delegate double MathTruncate(double d);
+
+ private delegate float MathFAbs(float x);
+ private delegate float MathFCeiling(float x);
+ private delegate float MathFFloor(float x);
+ private delegate float MathFRound(float x, MidpointRounding mode);
+ private delegate float MathFTruncate(float x);
+
+ private delegate void NativeInterfaceBreak(ulong address, int imm);
+ private delegate bool NativeInterfaceCheckSynchronization();
+ private delegate void NativeInterfaceEnqueueForRejit(ulong address);
+ private delegate ulong NativeInterfaceGetCntfrqEl0();
+ private delegate ulong NativeInterfaceGetCntpctEl0();
+ private delegate ulong NativeInterfaceGetCntvctEl0();
+ private delegate ulong NativeInterfaceGetCtrEl0();
+ private delegate ulong NativeInterfaceGetDczidEl0();
+ private delegate ulong NativeInterfaceGetFunctionAddress(ulong address);
+ private delegate void NativeInterfaceInvalidateCacheLine(ulong address);
+ private delegate byte NativeInterfaceReadByte(ulong address);
+ private delegate ushort NativeInterfaceReadUInt16(ulong address);
+ private delegate uint NativeInterfaceReadUInt32(ulong address);
+ private delegate ulong NativeInterfaceReadUInt64(ulong address);
+ private delegate V128 NativeInterfaceReadVector128(ulong address);
+ private delegate void NativeInterfaceSignalMemoryTracking(ulong address, ulong size, bool write);
+ private delegate void NativeInterfaceSupervisorCall(ulong address, int imm);
+ private delegate void NativeInterfaceThrowInvalidMemoryAccess(ulong address);
+ private delegate void NativeInterfaceUndefined(ulong address, int opCode);
+ private delegate void NativeInterfaceWriteByte(ulong address, byte value);
+ private delegate void NativeInterfaceWriteUInt16(ulong address, ushort value);
+ private delegate void NativeInterfaceWriteUInt32(ulong address, uint value);
+ private delegate void NativeInterfaceWriteUInt64(ulong address, ulong value);
+ private delegate void NativeInterfaceWriteVector128(ulong address, V128 value);
+
+ private delegate ulong SoftFallbackCountLeadingSigns(ulong value, int size);
+ private delegate ulong SoftFallbackCountLeadingZeros(ulong value, int size);
+ private delegate uint SoftFallbackCrc32b(uint crc, byte value);
+ private delegate uint SoftFallbackCrc32cb(uint crc, byte value);
+ private delegate uint SoftFallbackCrc32ch(uint crc, ushort value);
+ private delegate uint SoftFallbackCrc32cw(uint crc, uint value);
+ private delegate uint SoftFallbackCrc32cx(uint crc, ulong value);
+ private delegate uint SoftFallbackCrc32h(uint crc, ushort value);
+ private delegate uint SoftFallbackCrc32w(uint crc, uint value);
+ private delegate uint SoftFallbackCrc32x(uint crc, ulong value);
+ private delegate V128 SoftFallbackDecrypt(V128 value, V128 roundKey);
+ private delegate V128 SoftFallbackEncrypt(V128 value, V128 roundKey);
+ private delegate uint SoftFallbackFixedRotate(uint hash_e);
+ private delegate V128 SoftFallbackHashChoose(V128 hash_abcd, uint hash_e, V128 wk);
+ private delegate V128 SoftFallbackHashLower(V128 hash_abcd, V128 hash_efgh, V128 wk);
+ private delegate V128 SoftFallbackHashMajority(V128 hash_abcd, uint hash_e, V128 wk);
+ private delegate V128 SoftFallbackHashParity(V128 hash_abcd, uint hash_e, V128 wk);
+ private delegate V128 SoftFallbackHashUpper(V128 hash_abcd, V128 hash_efgh, V128 wk);
+ private delegate V128 SoftFallbackInverseMixColumns(V128 value);
+ private delegate V128 SoftFallbackMixColumns(V128 value);
+ private delegate V128 SoftFallbackPolynomialMult64_128(ulong op1, ulong op2);
+ private delegate int SoftFallbackSatF32ToS32(float value);
+ private delegate long SoftFallbackSatF32ToS64(float value);
+ private delegate uint SoftFallbackSatF32ToU32(float value);
+ private delegate ulong SoftFallbackSatF32ToU64(float value);
+ private delegate int SoftFallbackSatF64ToS32(double value);
+ private delegate long SoftFallbackSatF64ToS64(double value);
+ private delegate uint SoftFallbackSatF64ToU32(double value);
+ private delegate ulong SoftFallbackSatF64ToU64(double value);
+ private delegate V128 SoftFallbackSha1SchedulePart1(V128 w0_3, V128 w4_7, V128 w8_11);
+ private delegate V128 SoftFallbackSha1SchedulePart2(V128 tw0_3, V128 w12_15);
+ private delegate V128 SoftFallbackSha256SchedulePart1(V128 w0_3, V128 w4_7);
+ private delegate V128 SoftFallbackSha256SchedulePart2(V128 w0_3, V128 w8_11, V128 w12_15);
+ private delegate long SoftFallbackSignedShrImm64(long value, long roundConst, int shift);
+ private delegate V128 SoftFallbackTbl1(V128 vector, int bytes, V128 tb0);
+ private delegate V128 SoftFallbackTbl2(V128 vector, int bytes, V128 tb0, V128 tb1);
+ private delegate V128 SoftFallbackTbl3(V128 vector, int bytes, V128 tb0, V128 tb1, V128 tb2);
+ private delegate V128 SoftFallbackTbl4(V128 vector, int bytes, V128 tb0, V128 tb1, V128 tb2, V128 tb3);
+ private delegate V128 SoftFallbackTbx1(V128 dest, V128 vector, int bytes, V128 tb0);
+ private delegate V128 SoftFallbackTbx2(V128 dest, V128 vector, int bytes, V128 tb0, V128 tb1);
+ private delegate V128 SoftFallbackTbx3(V128 dest, V128 vector, int bytes, V128 tb0, V128 tb1, V128 tb2);
+ private delegate V128 SoftFallbackTbx4(V128 dest, V128 vector, int bytes, V128 tb0, V128 tb1, V128 tb2, V128 tb3);
+ private delegate ulong SoftFallbackUnsignedShrImm64(ulong value, long roundConst, int shift);
+
+ private delegate float SoftFloat16_32FPConvert(ushort valueBits);
+
+ private delegate double SoftFloat16_64FPConvert(ushort valueBits);
+
+ private delegate float SoftFloat32FPAdd(float value1, float value2);
+ private delegate float SoftFloat32FPAddFpscr(float value1, float value2, bool standardFpscr);
+ private delegate int SoftFloat32FPCompare(float value1, float value2, bool signalNaNs);
+ private delegate float SoftFloat32FPCompareEQ(float value1, float value2);
+ private delegate float SoftFloat32FPCompareEQFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPCompareGE(float value1, float value2);
+ private delegate float SoftFloat32FPCompareGEFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPCompareGT(float value1, float value2);
+ private delegate float SoftFloat32FPCompareGTFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPCompareLE(float value1, float value2);
+ private delegate float SoftFloat32FPCompareLEFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPCompareLT(float value1, float value2);
+ private delegate float SoftFloat32FPCompareLTFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPDiv(float value1, float value2);
+ private delegate float SoftFloat32FPMax(float value1, float value2);
+ private delegate float SoftFloat32FPMaxFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPMaxNum(float value1, float value2);
+ private delegate float SoftFloat32FPMaxNumFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPMin(float value1, float value2);
+ private delegate float SoftFloat32FPMinFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPMinNum(float value1, float value2);
+ private delegate float SoftFloat32FPMinNumFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPMul(float value1, float value2);
+ private delegate float SoftFloat32FPMulFpscr(float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPMulAdd(float valueA, float value1, float value2);
+ private delegate float SoftFloat32FPMulAddFpscr(float valueA, float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPMulSub(float valueA, float value1, float value2);
+ private delegate float SoftFloat32FPMulSubFpscr(float valueA, float value1, float value2, bool standardFpscr);
+ private delegate float SoftFloat32FPMulX(float value1, float value2);
+ private delegate float SoftFloat32FPNegMulAdd(float valueA, float value1, float value2);
+ private delegate float SoftFloat32FPNegMulSub(float valueA, float value1, float value2);
+ private delegate float SoftFloat32FPRecipEstimate(float value);
+ private delegate float SoftFloat32FPRecipEstimateFpscr(float value, bool standardFpscr);
+ private delegate float SoftFloat32FPRecipStep(float value1, float value2);
+ private delegate float SoftFloat32FPRecipStepFused(float value1, float value2);
+ private delegate float SoftFloat32FPRecpX(float value);
+ private delegate float SoftFloat32FPRSqrtEstimate(float value);
+ private delegate float SoftFloat32FPRSqrtEstimateFpscr(float value, bool standardFpscr);
+ private delegate float SoftFloat32FPRSqrtStep(float value1, float value2);
+ private delegate float SoftFloat32FPRSqrtStepFused(float value1, float value2);
+ private delegate float SoftFloat32FPSqrt(float value);
+ private delegate float SoftFloat32FPSub(float value1, float value2);
+
+ private delegate ushort SoftFloat32_16FPConvert(float value);
+
+ private delegate double SoftFloat64FPAdd(double value1, double value2);
+ private delegate double SoftFloat64FPAddFpscr(double value1, double value2, bool standardFpscr);
+ private delegate int SoftFloat64FPCompare(double value1, double value2, bool signalNaNs);
+ private delegate double SoftFloat64FPCompareEQ(double value1, double value2);
+ private delegate double SoftFloat64FPCompareEQFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPCompareGE(double value1, double value2);
+ private delegate double SoftFloat64FPCompareGEFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPCompareGT(double value1, double value2);
+ private delegate double SoftFloat64FPCompareGTFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPCompareLE(double value1, double value2);
+ private delegate double SoftFloat64FPCompareLEFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPCompareLT(double value1, double value2);
+ private delegate double SoftFloat64FPCompareLTFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPDiv(double value1, double value2);
+ private delegate double SoftFloat64FPMax(double value1, double value2);
+ private delegate double SoftFloat64FPMaxFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPMaxNum(double value1, double value2);
+ private delegate double SoftFloat64FPMaxNumFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPMin(double value1, double value2);
+ private delegate double SoftFloat64FPMinFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPMinNum(double value1, double value2);
+ private delegate double SoftFloat64FPMinNumFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPMul(double value1, double value2);
+ private delegate double SoftFloat64FPMulFpscr(double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPMulAdd(double valueA, double value1, double value2);
+ private delegate double SoftFloat64FPMulAddFpscr(double valueA, double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPMulSub(double valueA, double value1, double value2);
+ private delegate double SoftFloat64FPMulSubFpscr(double valueA, double value1, double value2, bool standardFpscr);
+ private delegate double SoftFloat64FPMulX(double value1, double value2);
+ private delegate double SoftFloat64FPNegMulAdd(double valueA, double value1, double value2);
+ private delegate double SoftFloat64FPNegMulSub(double valueA, double value1, double value2);
+ private delegate double SoftFloat64FPRecipEstimate(double value);
+ private delegate double SoftFloat64FPRecipEstimateFpscr(double value, bool standardFpscr);
+ private delegate double SoftFloat64FPRecipStep(double value1, double value2);
+ private delegate double SoftFloat64FPRecipStepFused(double value1, double value2);
+ private delegate double SoftFloat64FPRecpX(double value);
+ private delegate double SoftFloat64FPRSqrtEstimate(double value);
+ private delegate double SoftFloat64FPRSqrtEstimateFpscr(double value, bool standardFpscr);
+ private delegate double SoftFloat64FPRSqrtStep(double value1, double value2);
+ private delegate double SoftFloat64FPRSqrtStepFused(double value1, double value2);
+ private delegate double SoftFloat64FPSqrt(double value);
+ private delegate double SoftFloat64FPSub(double value1, double value2);
+
+ private delegate ushort SoftFloat64_16FPConvert(double value);
}
}
diff --git a/src/ARMeilleure/Translation/DispatcherFunction.cs b/src/ARMeilleure/Translation/DispatcherFunction.cs
index 7d5a3388e..649fa0f50 100644
--- a/src/ARMeilleure/Translation/DispatcherFunction.cs
+++ b/src/ARMeilleure/Translation/DispatcherFunction.cs
@@ -1,4 +1,4 @@
-using System;
+using System;
namespace ARMeilleure.Translation
{
diff --git a/src/ARMeilleure/Translation/Dominance.cs b/src/ARMeilleure/Translation/Dominance.cs
index b9b961d15..e2185bd85 100644
--- a/src/ARMeilleure/Translation/Dominance.cs
+++ b/src/ARMeilleure/Translation/Dominance.cs
@@ -29,7 +29,7 @@ BasicBlock Intersect(BasicBlock block1, BasicBlock block2)
cfg.Entry.ImmediateDominator = cfg.Entry;
- Debug.Assert(cfg.Entry == cfg.PostOrderBlocks[cfg.PostOrderBlocks.Length - 1]);
+ Debug.Assert(cfg.Entry == cfg.PostOrderBlocks[^1]);
bool modified;
@@ -92,4 +92,4 @@ public static void FindDominanceFrontiers(ControlFlowGraph cfg)
}
}
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/EmitterContext.cs b/src/ARMeilleure/Translation/EmitterContext.cs
index 8fcb4deec..88bfe1335 100644
--- a/src/ARMeilleure/Translation/EmitterContext.cs
+++ b/src/ARMeilleure/Translation/EmitterContext.cs
@@ -108,9 +108,9 @@ public virtual Operand Call(MethodInfo info, params Operand[] callArgs)
protected static OperandType GetOperandType(Type type)
{
- if (type == typeof(bool) || type == typeof(byte) ||
- type == typeof(char) || type == typeof(short) ||
- type == typeof(int) || type == typeof(sbyte) ||
+ if (type == typeof(bool) || type == typeof(byte) ||
+ type == typeof(char) || type == typeof(short) ||
+ type == typeof(int) || type == typeof(sbyte) ||
type == typeof(ushort) || type == typeof(uint))
{
return OperandType.I32;
@@ -635,7 +635,7 @@ public void MarkLabel(Operand label, BasicBlockFrequency nextFreq = default)
private void NewNextBlock()
{
- BasicBlock block = new BasicBlock(_irBlocks.Count);
+ BasicBlock block = new(_irBlocks.Count);
_irBlocks.AddLast(block);
diff --git a/src/ARMeilleure/Translation/GuestFunction.cs b/src/ARMeilleure/Translation/GuestFunction.cs
index ac131a0d1..6414d6bd0 100644
--- a/src/ARMeilleure/Translation/GuestFunction.cs
+++ b/src/ARMeilleure/Translation/GuestFunction.cs
@@ -3,4 +3,4 @@
namespace ARMeilleure.Translation
{
delegate ulong GuestFunction(IntPtr nativeContextPtr);
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/IntervalTree.cs b/src/ARMeilleure/Translation/IntervalTree.cs
index 9af01bea0..a5f9b5d5e 100644
--- a/src/ARMeilleure/Translation/IntervalTree.cs
+++ b/src/ARMeilleure/Translation/IntervalTree.cs
@@ -6,15 +6,15 @@ namespace ARMeilleure.Translation
///
/// An Augmented Interval Tree based off of the "TreeDictionary"'s Red-Black Tree. Allows fast overlap checking of ranges.
///
- /// Key
- /// Value
- class IntervalTree where K : IComparable
+ /// Key
+ /// Value
+ public class IntervalTree where TK : IComparable
{
private const int ArrayGrowthSize = 32;
private const bool Black = true;
private const bool Red = false;
- private IntervalTreeNode _root = null;
+ private IntervalTreeNode _root = null;
private int _count = 0;
public int Count => _count;
@@ -27,9 +27,9 @@ class IntervalTree where K : IComparable
/// Key of the node value to get
/// Value with the given
/// True if the key is on the dictionary, false otherwise
- public bool TryGet(K key, out V value)
+ public bool TryGet(TK key, out TV value)
{
- IntervalTreeNode node = GetNode(key);
+ IntervalTreeNode node = GetNode(key);
if (node == null)
{
@@ -49,7 +49,7 @@ public bool TryGet(K key, out V value)
/// Overlaps array to place results in
/// Index to start writing results into the array. Defaults to 0
/// Number of intervals found
- public int Get(K start, K end, ref K[] overlaps, int overlapCount = 0)
+ public int Get(TK start, TK end, ref TK[] overlaps, int overlapCount = 0)
{
GetKeys(_root, start, end, ref overlaps, ref overlapCount);
@@ -65,11 +65,11 @@ public int Get(K start, K end, ref K[] overlaps, int overlapCount = 0)
/// Optional factory used to create a new value if is already on the tree
/// is null
/// True if the value was added, false if the start key was already in the dictionary
- public bool AddOrUpdate(K start, K end, V value, Func updateFactoryCallback)
+ public bool AddOrUpdate(TK start, TK end, TV value, Func updateFactoryCallback)
{
ArgumentNullException.ThrowIfNull(value);
- return BSTInsert(start, end, value, updateFactoryCallback, out IntervalTreeNode node);
+ return BSTInsert(start, end, value, updateFactoryCallback, out _);
}
///
@@ -80,11 +80,11 @@ public bool AddOrUpdate(K start, K end, V value, Func updateFactoryCall
/// Value to add
/// is null
/// if is not yet on the tree, or the existing value otherwise
- public V GetOrAdd(K start, K end, V value)
+ public TV GetOrAdd(TK start, TK end, TV value)
{
ArgumentNullException.ThrowIfNull(value);
- BSTInsert(start, end, value, null, out IntervalTreeNode node);
+ BSTInsert(start, end, value, null, out IntervalTreeNode node);
return node.Value;
}
@@ -93,7 +93,7 @@ public V GetOrAdd(K start, K end, V value)
///
/// Key of the node to remove
/// Number of deleted values
- public int Remove(K key)
+ public int Remove(TK key)
{
int removed = Delete(key);
@@ -106,9 +106,9 @@ public int Remove(K key)
/// Adds all the nodes in the dictionary into .
///
/// A list of all values sorted by Key Order
- public List AsList()
+ public List AsList()
{
- List list = new List();
+ List list = new();
AddToList(_root, list);
@@ -124,7 +124,7 @@ public List AsList()
///
/// The node to search for values within
/// The list to add values to
- private void AddToList(IntervalTreeNode node, List list)
+ private void AddToList(IntervalTreeNode node, List list)
{
if (node == null)
{
@@ -144,11 +144,11 @@ private void AddToList(IntervalTreeNode node, List list)
/// Key of the node to get
/// is null
/// Node reference in the tree
- private IntervalTreeNode GetNode(K key)
+ private IntervalTreeNode GetNode(TK key)
{
ArgumentNullException.ThrowIfNull(key);
- IntervalTreeNode node = _root;
+ IntervalTreeNode node = _root;
while (node != null)
{
int cmp = key.CompareTo(node.Start);
@@ -175,7 +175,7 @@ private IntervalTreeNode GetNode(K key)
/// End of the range
/// Overlaps array to place results in
/// Overlaps count to update
- private void GetKeys(IntervalTreeNode node, K start, K end, ref K[] overlaps, ref int overlapCount)
+ private void GetKeys(IntervalTreeNode node, TK start, TK end, ref TK[] overlaps, ref int overlapCount)
{
if (node == null || start.CompareTo(node.Max) >= 0)
{
@@ -189,7 +189,7 @@ private void GetKeys(IntervalTreeNode node, K start, K end, ref K[] overla
{
if (start.CompareTo(node.End) < 0)
{
- if (overlaps.Length >= overlapCount)
+ if (overlaps.Length <= overlapCount)
{
Array.Resize(ref overlaps, overlapCount + ArrayGrowthSize);
}
@@ -206,10 +206,10 @@ private void GetKeys(IntervalTreeNode node, K start, K end, ref K[] overla
/// This should only be called if the max increases - not for rebalancing or removals.
///
/// The node to start propagating from
- private void PropagateIncrease(IntervalTreeNode node)
+ private static void PropagateIncrease(IntervalTreeNode node)
{
- K max = node.Max;
- IntervalTreeNode ptr = node;
+ TK max = node.Max;
+ IntervalTreeNode ptr = node;
while ((ptr = ptr.Parent) != null)
{
@@ -229,13 +229,13 @@ private void PropagateIncrease(IntervalTreeNode node)
/// This fully recalculates the max value from all children when there is potential for it to decrease.
///
/// The node to start propagating from
- private void PropagateFull(IntervalTreeNode node)
+ private static void PropagateFull(IntervalTreeNode node)
{
- IntervalTreeNode ptr = node;
+ IntervalTreeNode ptr = node;
do
{
- K max = ptr.End;
+ TK max = ptr.End;
if (ptr.Left != null && ptr.Left.Max.CompareTo(max) > 0)
{
@@ -263,10 +263,10 @@ private void PropagateFull(IntervalTreeNode node)
/// Optional factory used to create a new value if is already on the tree
/// Node that was inserted or modified
/// True if was not yet on the tree, false otherwise
- private bool BSTInsert(K start, K end, V value, Func updateFactoryCallback, out IntervalTreeNode outNode)
+ private bool BSTInsert(TK start, TK end, TV value, Func updateFactoryCallback, out IntervalTreeNode outNode)
{
- IntervalTreeNode parent = null;
- IntervalTreeNode node = _root;
+ IntervalTreeNode parent = null;
+ IntervalTreeNode node = _root;
while (node != null)
{
@@ -311,7 +311,7 @@ private bool BSTInsert(K start, K end, V value, Func updateFactoryCallb
return false;
}
}
- IntervalTreeNode newNode = new IntervalTreeNode(start, end, value, parent);
+ IntervalTreeNode newNode = new(start, end, value, parent);
if (newNode.Parent == null)
{
_root = newNode;
@@ -337,16 +337,16 @@ private bool BSTInsert(K start, K end, V value, Func updateFactoryCallb
///
/// Key to search for
/// Number of deleted values
- private int Delete(K key)
+ private int Delete(TK key)
{
- IntervalTreeNode nodeToDelete = GetNode(key);
+ IntervalTreeNode nodeToDelete = GetNode(key);
if (nodeToDelete == null)
{
return 0;
}
- IntervalTreeNode replacementNode;
+ IntervalTreeNode replacementNode;
if (LeftOf(nodeToDelete) == null || RightOf(nodeToDelete) == null)
{
@@ -357,7 +357,7 @@ private int Delete(K key)
replacementNode = PredecessorOf(nodeToDelete);
}
- IntervalTreeNode tmp = LeftOf(replacementNode) ?? RightOf(replacementNode);
+ IntervalTreeNode tmp = LeftOf(replacementNode) ?? RightOf(replacementNode);
if (tmp != null)
{
@@ -400,9 +400,9 @@ private int Delete(K key)
///
/// Root Node
/// Node with the maximum key in the tree of
- private static IntervalTreeNode Maximum(IntervalTreeNode node)
+ private static IntervalTreeNode Maximum(IntervalTreeNode node)
{
- IntervalTreeNode tmp = node;
+ IntervalTreeNode tmp = node;
while (tmp.Right != null)
{
tmp = tmp.Right;
@@ -416,13 +416,13 @@ private static IntervalTreeNode Maximum(IntervalTreeNode node)
///
/// Node to find the predecessor of
/// Predecessor of
- private static IntervalTreeNode PredecessorOf(IntervalTreeNode node)
+ private static IntervalTreeNode PredecessorOf(IntervalTreeNode node)
{
if (node.Left != null)
{
return Maximum(node.Left);
}
- IntervalTreeNode parent = node.Parent;
+ IntervalTreeNode parent = node.Parent;
while (parent != null && node == parent.Left)
{
node = parent;
@@ -435,15 +435,15 @@ private static IntervalTreeNode PredecessorOf(IntervalTreeNode node)
#region Private Methods (RBL)
- private void RestoreBalanceAfterRemoval(IntervalTreeNode balanceNode)
+ private void RestoreBalanceAfterRemoval(IntervalTreeNode balanceNode)
{
- IntervalTreeNode ptr = balanceNode;
+ IntervalTreeNode ptr = balanceNode;
while (ptr != _root && ColorOf(ptr) == Black)
{
if (ptr == LeftOf(ParentOf(ptr)))
{
- IntervalTreeNode sibling = RightOf(ParentOf(ptr));
+ IntervalTreeNode sibling = RightOf(ParentOf(ptr));
if (ColorOf(sibling) == Red)
{
@@ -475,7 +475,7 @@ private void RestoreBalanceAfterRemoval(IntervalTreeNode balanceNode)
}
else
{
- IntervalTreeNode sibling = LeftOf(ParentOf(ptr));
+ IntervalTreeNode sibling = LeftOf(ParentOf(ptr));
if (ColorOf(sibling) == Red)
{
@@ -509,14 +509,14 @@ private void RestoreBalanceAfterRemoval(IntervalTreeNode balanceNode)
SetColor(ptr, Black);
}
- private void RestoreBalanceAfterInsertion(IntervalTreeNode balanceNode)
+ private void RestoreBalanceAfterInsertion(IntervalTreeNode balanceNode)
{
SetColor(balanceNode, Red);
while (balanceNode != null && balanceNode != _root && ColorOf(ParentOf(balanceNode)) == Red)
{
if (ParentOf(balanceNode) == LeftOf(ParentOf(ParentOf(balanceNode))))
{
- IntervalTreeNode sibling = RightOf(ParentOf(ParentOf(balanceNode)));
+ IntervalTreeNode sibling = RightOf(ParentOf(ParentOf(balanceNode)));
if (ColorOf(sibling) == Red)
{
@@ -539,7 +539,7 @@ private void RestoreBalanceAfterInsertion(IntervalTreeNode balanceNode)
}
else
{
- IntervalTreeNode sibling = LeftOf(ParentOf(ParentOf(balanceNode)));
+ IntervalTreeNode sibling = LeftOf(ParentOf(ParentOf(balanceNode)));
if (ColorOf(sibling) == Red)
{
@@ -564,17 +564,17 @@ private void RestoreBalanceAfterInsertion(IntervalTreeNode balanceNode)
SetColor(_root, Black);
}
- private void RotateLeft(IntervalTreeNode node)
+ private void RotateLeft(IntervalTreeNode node)
{
if (node != null)
{
- IntervalTreeNode right = RightOf(node);
+ IntervalTreeNode right = RightOf(node);
node.Right = LeftOf(right);
if (node.Right != null)
{
node.Right.Parent = node;
}
- IntervalTreeNode nodeParent = ParentOf(node);
+ IntervalTreeNode nodeParent = ParentOf(node);
right.Parent = nodeParent;
if (nodeParent == null)
{
@@ -595,17 +595,17 @@ private void RotateLeft(IntervalTreeNode node)
}
}
- private void RotateRight(IntervalTreeNode node)
+ private void RotateRight(IntervalTreeNode node)
{
if (node != null)
{
- IntervalTreeNode left = LeftOf(node);
+ IntervalTreeNode left = LeftOf(node);
node.Left = RightOf(left);
if (node.Left != null)
{
node.Left.Parent = node;
}
- IntervalTreeNode nodeParent = ParentOf(node);
+ IntervalTreeNode nodeParent = ParentOf(node);
left.Parent = nodeParent;
if (nodeParent == null)
{
@@ -637,7 +637,7 @@ private void RotateRight(IntervalTreeNode node)
///
/// Node
/// The boolean color of , or black if null
- private static bool ColorOf(IntervalTreeNode node)
+ private static bool ColorOf(IntervalTreeNode node)
{
return node == null || node.Color;
}
@@ -649,7 +649,7 @@ private static bool ColorOf(IntervalTreeNode node)
///
/// Node to set the color of
/// Color (Boolean)
- private static void SetColor(IntervalTreeNode node, bool color)
+ private static void SetColor(IntervalTreeNode node, bool color)
{
if (node != null)
{
@@ -662,7 +662,7 @@ private static void SetColor(IntervalTreeNode node, bool color)
///
/// Node to retrieve the left child from
/// Left child of
- private static IntervalTreeNode LeftOf(IntervalTreeNode node)
+ private static IntervalTreeNode LeftOf(IntervalTreeNode node)
{
return node?.Left;
}
@@ -672,7 +672,7 @@ private static IntervalTreeNode LeftOf(IntervalTreeNode node)
///
/// Node to retrieve the right child from
/// Right child of
- private static IntervalTreeNode RightOf(IntervalTreeNode node)
+ private static IntervalTreeNode RightOf(IntervalTreeNode node)
{
return node?.Right;
}
@@ -682,14 +682,14 @@ private static IntervalTreeNode RightOf(IntervalTreeNode node)
///
/// Node to retrieve the parent from
/// Parent of
- private static IntervalTreeNode ParentOf(IntervalTreeNode node)
+ private static IntervalTreeNode ParentOf(IntervalTreeNode node)
{
return node?.Parent;
}
#endregion
- public bool ContainsKey(K key)
+ public bool ContainsKey(TK key)
{
return GetNode(key) != null;
}
@@ -704,36 +704,36 @@ public void Clear()
///
/// Represents a node in the IntervalTree which contains start and end keys of type K, and a value of generic type V.
///
- /// Key type of the node
- /// Value type of the node
- class IntervalTreeNode
+ /// Key type of the node
+ /// Value type of the node
+ class IntervalTreeNode
{
public bool Color = true;
- public IntervalTreeNode Left = null;
- public IntervalTreeNode Right = null;
- public IntervalTreeNode Parent = null;
+ public IntervalTreeNode Left = null;
+ public IntervalTreeNode Right = null;
+ public IntervalTreeNode Parent = null;
///
/// The start of the range.
///
- public K Start;
+ public TK Start;
///
/// The end of the range.
///
- public K End;
+ public TK End;
///
/// The maximum end value of this node and all its children.
///
- public K Max;
+ public TK Max;
///
/// Value stored on this node.
///
- public V Value;
+ public TV Value;
- public IntervalTreeNode(K start, K end, V value, IntervalTreeNode parent)
+ public IntervalTreeNode(TK start, TK end, TV value, IntervalTreeNode parent)
{
Start = start;
End = end;
diff --git a/src/ARMeilleure/Translation/PTC/EncodingCache.cs b/src/ARMeilleure/Translation/PTC/EncodingCache.cs
index 90d40c475..d9b38ace7 100644
--- a/src/ARMeilleure/Translation/PTC/EncodingCache.cs
+++ b/src/ARMeilleure/Translation/PTC/EncodingCache.cs
@@ -6,4 +6,4 @@ static class EncodingCache
{
public static readonly Encoding UTF8NoBOM = new UTF8Encoding(encoderShouldEmitUTF8Identifier: false, throwOnInvalidBytes: true);
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs b/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs
index 1b11ac0b5..efff45a9f 100644
--- a/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs
+++ b/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs
@@ -7,4 +7,4 @@ public interface IPtcLoadState
event Action PtcStateChanged;
void Continue();
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/PTC/Ptc.cs b/src/ARMeilleure/Translation/PTC/Ptc.cs
index ea4e715b5..6f6dfcadf 100644
--- a/src/ARMeilleure/Translation/PTC/Ptc.cs
+++ b/src/ARMeilleure/Translation/PTC/Ptc.cs
@@ -17,20 +17,19 @@
using System.Runtime.CompilerServices;
using System.Runtime.InteropServices;
using System.Threading;
-
using static ARMeilleure.Translation.PTC.PtcFormatter;
namespace ARMeilleure.Translation.PTC
{
- using Arm64HardwareCapabilities = ARMeilleure.CodeGen.Arm64.HardwareCapabilities;
- using X86HardwareCapabilities = ARMeilleure.CodeGen.X86.HardwareCapabilities;
+ using Arm64HardwareCapabilities = CodeGen.Arm64.HardwareCapabilities;
+ using X86HardwareCapabilities = CodeGen.X86.HardwareCapabilities;
class Ptc : IPtcLoadState
{
private const string OuterHeaderMagicString = "PTCohd\0\0";
private const string InnerHeaderMagicString = "PTCihd\0\0";
- private const uint InternalVersion = 4661; //! To be incremented manually for each change to the ARMeilleure project.
+ private const uint InternalVersion = 5518; //! To be incremented manually for each change to the ARMeilleure project.
private const string ActualDir = "0";
private const string BackupDir = "1";
@@ -187,8 +186,8 @@ private void PreLoad()
string fileNameActual = $"{CachePathActual}.cache";
string fileNameBackup = $"{CachePathBackup}.cache";
- FileInfo fileInfoActual = new FileInfo(fileNameActual);
- FileInfo fileInfoBackup = new FileInfo(fileNameBackup);
+ FileInfo fileInfoActual = new(fileNameActual);
+ FileInfo fileInfoBackup = new(fileNameBackup);
if (fileInfoActual.Exists && fileInfoActual.Length != 0L)
{
@@ -275,104 +274,102 @@ private unsafe bool Load(string fileName, bool isBackup)
{
intPtr = Marshal.AllocHGlobal(new IntPtr(outerHeader.UncompressedStreamSize));
- using (UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite))
+ using UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite);
+ try
{
- try
- {
- deflateStream.CopyTo(stream);
- }
- catch
- {
- InvalidateCompressedStream(compressedStream);
+ deflateStream.CopyTo(stream);
+ }
+ catch
+ {
+ InvalidateCompressedStream(compressedStream);
- return false;
- }
+ return false;
+ }
- Debug.Assert(stream.Position == stream.Length);
+ Debug.Assert(stream.Position == stream.Length);
- stream.Seek(0L, SeekOrigin.Begin);
+ stream.Seek(0L, SeekOrigin.Begin);
- InnerHeader innerHeader = DeserializeStructure(stream);
+ InnerHeader innerHeader = DeserializeStructure(stream);
- if (!innerHeader.IsHeaderValid())
- {
- InvalidateCompressedStream(compressedStream);
+ if (!innerHeader.IsHeaderValid())
+ {
+ InvalidateCompressedStream(compressedStream);
- return false;
- }
+ return false;
+ }
- if (innerHeader.Magic != _innerHeaderMagic)
- {
- InvalidateCompressedStream(compressedStream);
+ if (innerHeader.Magic != _innerHeaderMagic)
+ {
+ InvalidateCompressedStream(compressedStream);
- return false;
- }
+ return false;
+ }
- ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength);
- stream.Seek(innerHeader.InfosLength, SeekOrigin.Current);
+ ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength);
+ stream.Seek(innerHeader.InfosLength, SeekOrigin.Current);
- Hash128 infosHash = XXHash128.ComputeHash(infosBytes);
+ Hash128 infosHash = XXHash128.ComputeHash(infosBytes);
- if (innerHeader.InfosHash != infosHash)
- {
- InvalidateCompressedStream(compressedStream);
+ if (innerHeader.InfosHash != infosHash)
+ {
+ InvalidateCompressedStream(compressedStream);
- return false;
- }
+ return false;
+ }
- ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty;
- stream.Seek(innerHeader.CodesLength, SeekOrigin.Current);
+ ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty;
+ stream.Seek(innerHeader.CodesLength, SeekOrigin.Current);
- Hash128 codesHash = XXHash128.ComputeHash(codesBytes);
+ Hash128 codesHash = XXHash128.ComputeHash(codesBytes);
- if (innerHeader.CodesHash != codesHash)
- {
- InvalidateCompressedStream(compressedStream);
+ if (innerHeader.CodesHash != codesHash)
+ {
+ InvalidateCompressedStream(compressedStream);
- return false;
- }
+ return false;
+ }
- ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength);
- stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current);
+ ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength);
+ stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current);
- Hash128 relocsHash = XXHash128.ComputeHash(relocsBytes);
+ Hash128 relocsHash = XXHash128.ComputeHash(relocsBytes);
- if (innerHeader.RelocsHash != relocsHash)
- {
- InvalidateCompressedStream(compressedStream);
+ if (innerHeader.RelocsHash != relocsHash)
+ {
+ InvalidateCompressedStream(compressedStream);
- return false;
- }
+ return false;
+ }
- ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength);
- stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current);
+ ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength);
+ stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current);
- Hash128 unwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes);
+ Hash128 unwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes);
- if (innerHeader.UnwindInfosHash != unwindInfosHash)
- {
- InvalidateCompressedStream(compressedStream);
+ if (innerHeader.UnwindInfosHash != unwindInfosHash)
+ {
+ InvalidateCompressedStream(compressedStream);
- return false;
- }
+ return false;
+ }
- Debug.Assert(stream.Position == stream.Length);
+ Debug.Assert(stream.Position == stream.Length);
- stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin);
+ stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin);
- _infosStream.Write(infosBytes);
- stream.Seek(innerHeader.InfosLength, SeekOrigin.Current);
+ _infosStream.Write(infosBytes);
+ stream.Seek(innerHeader.InfosLength, SeekOrigin.Current);
- _codesList.ReadFrom(stream);
+ _codesList.ReadFrom(stream);
- _relocsStream.Write(relocsBytes);
- stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current);
+ _relocsStream.Write(relocsBytes);
+ stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current);
- _unwindInfosStream.Write(unwindInfosBytes);
- stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current);
+ _unwindInfosStream.Write(unwindInfosBytes);
+ stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current);
- Debug.Assert(stream.Position == stream.Length);
- }
+ Debug.Assert(stream.Position == stream.Length);
}
finally
{
@@ -390,7 +387,7 @@ private unsafe bool Load(string fileName, bool isBackup)
return true;
}
- private void InvalidateCompressedStream(FileStream compressedStream)
+ private static void InvalidateCompressedStream(FileStream compressedStream)
{
compressedStream.SetLength(0L);
}
@@ -404,7 +401,7 @@ private void PreSave()
string fileNameActual = $"{CachePathActual}.cache";
string fileNameBackup = $"{CachePathBackup}.cache";
- FileInfo fileInfoActual = new FileInfo(fileNameActual);
+ FileInfo fileInfoActual = new(fileNameActual);
if (fileInfoActual.Exists && fileInfoActual.Length != 0L)
{
@@ -427,32 +424,34 @@ private unsafe void Save(string fileName)
{
int translatedFuncsCount;
- InnerHeader innerHeader = new InnerHeader();
-
- innerHeader.Magic = _innerHeaderMagic;
-
- innerHeader.InfosLength = (int)_infosStream.Length;
- innerHeader.CodesLength = _codesList.Length();
- innerHeader.RelocsLength = (int)_relocsStream.Length;
- innerHeader.UnwindInfosLength = (int)_unwindInfosStream.Length;
+ InnerHeader innerHeader = new()
+ {
+ Magic = _innerHeaderMagic,
- OuterHeader outerHeader = new OuterHeader();
+ InfosLength = (int)_infosStream.Length,
+ CodesLength = _codesList.Length(),
+ RelocsLength = (int)_relocsStream.Length,
+ UnwindInfosLength = (int)_unwindInfosStream.Length,
+ };
- outerHeader.Magic = _outerHeaderMagic;
+ OuterHeader outerHeader = new()
+ {
+ Magic = _outerHeaderMagic,
- outerHeader.CacheFileVersion = InternalVersion;
- outerHeader.Endianness = GetEndianness();
- outerHeader.FeatureInfo = GetFeatureInfo();
- outerHeader.MemoryManagerMode = GetMemoryManagerMode();
- outerHeader.OSPlatform = GetOSPlatform();
- outerHeader.Architecture = (uint)RuntimeInformation.ProcessArchitecture;
+ CacheFileVersion = InternalVersion,
+ Endianness = GetEndianness(),
+ FeatureInfo = GetFeatureInfo(),
+ MemoryManagerMode = GetMemoryManagerMode(),
+ OSPlatform = GetOSPlatform(),
+ Architecture = (uint)RuntimeInformation.ProcessArchitecture,
- outerHeader.UncompressedStreamSize =
+ UncompressedStreamSize =
(long)Unsafe.SizeOf() +
innerHeader.InfosLength +
innerHeader.CodesLength +
innerHeader.RelocsLength +
- innerHeader.UnwindInfosLength;
+ innerHeader.UnwindInfosLength,
+ };
outerHeader.SetHeaderHash();
@@ -462,58 +461,54 @@ private unsafe void Save(string fileName)
{
intPtr = Marshal.AllocHGlobal(new IntPtr(outerHeader.UncompressedStreamSize));
- using (UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite))
- {
- stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin);
+ using UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite);
+ stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin);
- ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength);
- _infosStream.WriteTo(stream);
+ ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength);
+ _infosStream.WriteTo(stream);
- ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty;
- _codesList.WriteTo(stream);
+ ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty;
+ _codesList.WriteTo(stream);
- ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength);
- _relocsStream.WriteTo(stream);
+ ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength);
+ _relocsStream.WriteTo(stream);
- ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength);
- _unwindInfosStream.WriteTo(stream);
+ ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength);
+ _unwindInfosStream.WriteTo(stream);
- Debug.Assert(stream.Position == stream.Length);
+ Debug.Assert(stream.Position == stream.Length);
- innerHeader.InfosHash = XXHash128.ComputeHash(infosBytes);
- innerHeader.CodesHash = XXHash128.ComputeHash(codesBytes);
- innerHeader.RelocsHash = XXHash128.ComputeHash(relocsBytes);
- innerHeader.UnwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes);
+ innerHeader.InfosHash = XXHash128.ComputeHash(infosBytes);
+ innerHeader.CodesHash = XXHash128.ComputeHash(codesBytes);
+ innerHeader.RelocsHash = XXHash128.ComputeHash(relocsBytes);
+ innerHeader.UnwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes);
- innerHeader.SetHeaderHash();
+ innerHeader.SetHeaderHash();
- stream.Seek(0L, SeekOrigin.Begin);
- SerializeStructure(stream, innerHeader);
+ stream.Seek(0L, SeekOrigin.Begin);
+ SerializeStructure(stream, innerHeader);
- translatedFuncsCount = GetEntriesCount();
+ translatedFuncsCount = GetEntriesCount();
- ResetCarriersIfNeeded();
+ ResetCarriersIfNeeded();
- using (FileStream compressedStream = new(fileName, FileMode.OpenOrCreate))
- using (DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true))
- {
- try
- {
- SerializeStructure(compressedStream, outerHeader);
+ using FileStream compressedStream = new(fileName, FileMode.OpenOrCreate);
+ using DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true);
+ try
+ {
+ SerializeStructure(compressedStream, outerHeader);
- stream.Seek(0L, SeekOrigin.Begin);
- stream.CopyTo(deflateStream);
- }
- catch
- {
- compressedStream.Position = 0L;
- }
+ stream.Seek(0L, SeekOrigin.Begin);
+ stream.CopyTo(deflateStream);
+ }
+ catch
+ {
+ compressedStream.Position = 0L;
+ }
- if (compressedStream.Position < compressedStream.Length)
- {
- compressedStream.SetLength(compressedStream.Position);
- }
- }
+ if (compressedStream.Position < compressedStream.Length)
+ {
+ compressedStream.SetLength(compressedStream.Position);
}
}
finally
@@ -647,7 +642,7 @@ private byte[] ReadCode(int index, int codeLength)
return _codesList[index];
}
- private RelocEntry[] GetRelocEntries(BinaryReader relocsReader, int relocEntriesCount)
+ private static RelocEntry[] GetRelocEntries(BinaryReader relocsReader, int relocEntriesCount)
{
RelocEntry[] relocEntries = new RelocEntry[relocEntriesCount];
@@ -663,7 +658,7 @@ private RelocEntry[] GetRelocEntries(BinaryReader relocsReader, int relocEntries
return relocEntries;
}
- private void PatchCode(Translator translator, Span code, RelocEntry[] relocEntries, out Counter callCounter)
+ private static void PatchCode(Translator translator, Span code, RelocEntry[] relocEntries, out Counter callCounter)
{
callCounter = null;
@@ -678,7 +673,10 @@ private void PatchCode(Translator translator, Span code, RelocEntry[] relo
if (translator.FunctionTable.IsValid(guestAddress))
{
- unsafe { imm = (IntPtr)Unsafe.AsPointer(ref translator.FunctionTable.GetValue(guestAddress)); }
+ unsafe
+ {
+ imm = (IntPtr)Unsafe.AsPointer(ref translator.FunctionTable.GetValue(guestAddress));
+ }
}
}
else if (symbol.Type == SymbolType.DelegateTable)
@@ -696,12 +694,12 @@ private void PatchCode(Translator translator, Span code, RelocEntry[] relo
}
else if (symbol == CountTableSymbol)
{
- if (callCounter == null)
+ callCounter ??= new Counter(translator.CountTable);
+
+ unsafe
{
- callCounter = new Counter(translator.CountTable);
+ imm = (IntPtr)Unsafe.AsPointer(ref callCounter.Value);
}
-
- unsafe { imm = (IntPtr)Unsafe.AsPointer(ref callCounter.Value); }
}
else if (symbol == DispatchStubSymbol)
{
@@ -717,7 +715,7 @@ private void PatchCode(Translator translator, Span code, RelocEntry[] relo
}
}
- private UnwindInfo ReadUnwindInfo(BinaryReader unwindInfosReader)
+ private static UnwindInfo ReadUnwindInfo(BinaryReader unwindInfosReader)
{
int pushEntriesLength = unwindInfosReader.ReadInt32();
@@ -738,7 +736,7 @@ private UnwindInfo ReadUnwindInfo(BinaryReader unwindInfosReader)
return new UnwindInfo(pushEntries, prologueSize);
}
- private TranslatedFunction FastTranslate(
+ private static TranslatedFunction FastTranslate(
byte[] code,
Counter callCounter,
ulong guestSize,
@@ -809,13 +807,13 @@ public void MakeAndSaveTranslations(Translator translator)
PtcStateChanged?.Invoke(PtcLoadingState.Start, _translateCount, _translateTotalCount);
- using AutoResetEvent progressReportEvent = new AutoResetEvent(false);
+ using AutoResetEvent progressReportEvent = new(false);
- Thread progressReportThread = new Thread(ReportProgress)
+ Thread progressReportThread = new(ReportProgress)
{
Name = "Ptc.ProgressReporter",
Priority = ThreadPriority.Lowest,
- IsBackground = true
+ IsBackground = true,
};
progressReportThread.Start(progressReportEvent);
@@ -845,12 +843,14 @@ void TranslateFuncs()
}
}
- List threads = new List();
+ List threads = new();
for (int i = 0; i < degreeOfParallelism; i++)
{
- Thread thread = new Thread(TranslateFuncs);
- thread.IsBackground = true;
+ Thread thread = new(TranslateFuncs)
+ {
+ IsBackground = true,
+ };
threads.Add(thread);
}
@@ -871,14 +871,16 @@ void TranslateFuncs()
Logger.Info?.Print(LogClass.Ptc, $"{_translateCount} of {_translateTotalCount} functions translated | Thread count: {degreeOfParallelism} in {sw.Elapsed.TotalSeconds} s");
- Thread preSaveThread = new Thread(PreSave);
- preSaveThread.IsBackground = true;
+ Thread preSaveThread = new(PreSave)
+ {
+ IsBackground = true,
+ };
preSaveThread.Start();
}
private void ReportProgress(object state)
{
- const int refreshRate = 50; // ms.
+ const int RefreshRate = 50; // ms.
AutoResetEvent endEvent = (AutoResetEvent)state;
@@ -894,7 +896,7 @@ private void ReportProgress(object state)
count = newCount;
}
}
- while (!endEvent.WaitOne(refreshRate));
+ while (!endEvent.WaitOne(RefreshRate));
}
public static Hash128 ComputeHash(IMemoryManager memory, ulong address, ulong guestSize)
@@ -910,15 +912,16 @@ public void WriteCompiledFunction(ulong address, ulong guestSize, Hash128 hash,
RelocInfo relocInfo = compiledFunc.RelocInfo;
UnwindInfo unwindInfo = compiledFunc.UnwindInfo;
- InfoEntry infoEntry = new InfoEntry();
-
- infoEntry.Address = address;
- infoEntry.GuestSize = guestSize;
- infoEntry.Hash = hash;
- infoEntry.HighCq = highCq;
- infoEntry.Stubbed = false;
- infoEntry.CodeLength = code.Length;
- infoEntry.RelocEntriesCount = relocInfo.Entries.Length;
+ InfoEntry infoEntry = new()
+ {
+ Address = address,
+ GuestSize = guestSize,
+ Hash = hash,
+ HighCq = highCq,
+ Stubbed = false,
+ CodeLength = code.Length,
+ RelocEntriesCount = relocInfo.Entries.Length,
+ };
SerializeStructure(_infosStream, infoEntry);
@@ -996,10 +999,12 @@ private static uint GetOSPlatform()
{
uint osPlatform = 0u;
+#pragma warning disable IDE0055 // Disable formatting
osPlatform |= (OperatingSystem.IsFreeBSD() ? 1u : 0u) << 0;
osPlatform |= (OperatingSystem.IsLinux() ? 1u : 0u) << 1;
osPlatform |= (OperatingSystem.IsMacOS() ? 1u : 0u) << 2;
osPlatform |= (OperatingSystem.IsWindows() ? 1u : 0u) << 3;
+#pragma warning restore IDE0055
return osPlatform;
}
@@ -1025,14 +1030,14 @@ public void SetHeaderHash()
{
Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1);
- HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf()));
+ HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]);
}
public bool IsHeaderValid()
{
Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1);
- return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash;
+ return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]) == HeaderHash;
}
}
@@ -1060,14 +1065,14 @@ public void SetHeaderHash()
{
Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1);
- HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf()));
+ HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]);
}
public bool IsHeaderValid()
{
Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1);
- return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash;
+ return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]) == HeaderHash;
}
}
diff --git a/src/ARMeilleure/Translation/PTC/PtcFormatter.cs b/src/ARMeilleure/Translation/PTC/PtcFormatter.cs
index 2f7a9c21f..60953dcd9 100644
--- a/src/ARMeilleure/Translation/PTC/PtcFormatter.cs
+++ b/src/ARMeilleure/Translation/PTC/PtcFormatter.cs
@@ -27,6 +27,26 @@ public static Dictionary DeserializeDictionary(Strea
return dictionary;
}
+ [MethodImpl(MethodImplOptions.AggressiveInlining)]
+ public static Dictionary DeserializeAndUpdateDictionary(Stream stream, Func valueFunc, Func updateFunc) where TKey : struct
+ {
+ Dictionary dictionary = new();
+
+ int count = DeserializeStructure(stream);
+
+ for (int i = 0; i < count; i++)
+ {
+ TKey key = DeserializeStructure(stream);
+ TValue value = valueFunc(stream);
+
+ (key, value) = updateFunc(key, value);
+
+ dictionary.Add(key, value);
+ }
+
+ return dictionary;
+ }
+
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static List DeserializeList(Stream stream) where T : struct
{
@@ -47,7 +67,7 @@ public static List DeserializeList(Stream stream) where T : struct
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static T DeserializeStructure(Stream stream) where T : struct
{
- T structure = default(T);
+ T structure = default;
Span spanT = MemoryMarshal.CreateSpan(ref structure, 1);
int bytesCount = stream.Read(MemoryMarshal.AsBytes(spanT));
@@ -176,4 +196,4 @@ public static void WriteTo(this List list, Stream stream) where T : stru
}
#endregion
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs b/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs
index 526cf91fb..587be7939 100644
--- a/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs
+++ b/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs
@@ -4,6 +4,6 @@ public enum PtcLoadingState
{
Start,
Loading,
- Loaded
+ Loaded,
}
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/Translation/PTC/PtcProfiler.cs b/src/ARMeilleure/Translation/PTC/PtcProfiler.cs
index 391e29c76..0fe78edab 100644
--- a/src/ARMeilleure/Translation/PTC/PtcProfiler.cs
+++ b/src/ARMeilleure/Translation/PTC/PtcProfiler.cs
@@ -9,11 +9,13 @@
using System.Diagnostics;
using System.IO;
using System.IO.Compression;
+using System.Linq;
using System.Runtime.CompilerServices;
using System.Runtime.InteropServices;
using System.Threading;
-
+using System.Timers;
using static ARMeilleure.Translation.PTC.PtcFormatter;
+using Timer = System.Timers.Timer;
namespace ARMeilleure.Translation.PTC
{
@@ -21,7 +23,11 @@ class PtcProfiler
{
private const string OuterHeaderMagicString = "Pohd\0\0\0\0";
- private const uint InternalVersion = 1866; //! Not to be incremented manually for each change to the ARMeilleure project.
+ private const uint InternalVersion = 5518; //! Not to be incremented manually for each change to the ARMeilleure project.
+
+ private static readonly uint[] _migrateInternalVersions = {
+ 1866,
+ };
private const int SaveInterval = 30; // Seconds.
@@ -29,7 +35,7 @@ class PtcProfiler
private readonly Ptc _ptc;
- private readonly System.Timers.Timer _timer;
+ private readonly Timer _timer;
private readonly ulong _outerHeaderMagic;
@@ -46,13 +52,13 @@ class PtcProfiler
public bool Enabled { get; private set; }
public ulong StaticCodeStart { get; set; }
- public ulong StaticCodeSize { get; set; }
+ public ulong StaticCodeSize { get; set; }
public PtcProfiler(Ptc ptc)
{
_ptc = ptc;
- _timer = new System.Timers.Timer((double)SaveInterval * 1000d);
+ _timer = new Timer(SaveInterval * 1000d);
_timer.Elapsed += PreSave;
_outerHeaderMagic = BinaryPrimitives.ReadUInt64LittleEndian(EncodingCache.UTF8NoBOM.GetBytes(OuterHeaderMagicString).AsSpan());
@@ -129,8 +135,8 @@ public void PreLoad()
string fileNameActual = $"{_ptc.CachePathActual}.info";
string fileNameBackup = $"{_ptc.CachePathBackup}.info";
- FileInfo fileInfoActual = new FileInfo(fileNameActual);
- FileInfo fileInfoBackup = new FileInfo(fileNameBackup);
+ FileInfo fileInfoActual = new(fileNameActual);
+ FileInfo fileInfoBackup = new(fileNameBackup);
if (fileInfoActual.Exists && fileInfoActual.Length != 0L)
{
@@ -169,7 +175,7 @@ private bool Load(string fileName, bool isBackup)
return false;
}
- if (outerHeader.InfoFileVersion != InternalVersion)
+ if (outerHeader.InfoFileVersion != InternalVersion && !_migrateInternalVersions.Contains(outerHeader.InfoFileVersion))
{
InvalidateCompressedStream(compressedStream);
@@ -183,42 +189,52 @@ private bool Load(string fileName, bool isBackup)
return false;
}
- using (MemoryStream stream = MemoryStreamManager.Shared.GetStream())
+ using MemoryStream stream = MemoryStreamManager.Shared.GetStream();
+ Debug.Assert(stream.Seek(0L, SeekOrigin.Begin) == 0L && stream.Length == 0L);
+
+ try
+ {
+ deflateStream.CopyTo(stream);
+ }
+ catch
{
- Debug.Assert(stream.Seek(0L, SeekOrigin.Begin) == 0L && stream.Length == 0L);
+ InvalidateCompressedStream(compressedStream);
- try
- {
- deflateStream.CopyTo(stream);
- }
- catch
- {
- InvalidateCompressedStream(compressedStream);
+ return false;
+ }
- return false;
- }
+ Debug.Assert(stream.Position == stream.Length);
- Debug.Assert(stream.Position == stream.Length);
+ stream.Seek(0L, SeekOrigin.Begin);
- stream.Seek(0L, SeekOrigin.Begin);
+ Hash128 expectedHash = DeserializeStructure(stream);
- Hash128 expectedHash = DeserializeStructure(stream);
+ Hash128 actualHash = XXHash128.ComputeHash(GetReadOnlySpan(stream));
- Hash128 actualHash = XXHash128.ComputeHash(GetReadOnlySpan(stream));
+ if (actualHash != expectedHash)
+ {
+ InvalidateCompressedStream(compressedStream);
- if (actualHash != expectedHash)
- {
- InvalidateCompressedStream(compressedStream);
+ return false;
+ }
+ switch (outerHeader.InfoFileVersion)
+ {
+ case InternalVersion:
+ ProfiledFuncs = Deserialize(stream);
+ break;
+ case 1866:
+ ProfiledFuncs = Deserialize(stream, (address, profile) => (address + 0x500000UL, profile));
+ break;
+ default:
+ Logger.Error?.Print(LogClass.Ptc, $"No migration path for {nameof(outerHeader.InfoFileVersion)} '{outerHeader.InfoFileVersion}'. Discarding cache.");
+ InvalidateCompressedStream(compressedStream);
return false;
- }
-
- ProfiledFuncs = Deserialize(stream);
+ }
- Debug.Assert(stream.Position == stream.Length);
+ Debug.Assert(stream.Position == stream.Length);
- _lastHash = actualHash;
- }
+ _lastHash = actualHash;
}
long fileSize = new FileInfo(fileName).Length;
@@ -228,29 +244,34 @@ private bool Load(string fileName, bool isBackup)
return true;
}
- private static Dictionary Deserialize(Stream stream)
+ private static Dictionary Deserialize(Stream stream, Func migrateEntryFunc = null)
{
- return DeserializeDictionary(stream, (stream) => DeserializeStructure(stream));
+ if (migrateEntryFunc != null)
+ {
+ return DeserializeAndUpdateDictionary(stream, DeserializeStructure, migrateEntryFunc);
+ }
+
+ return DeserializeDictionary(stream, DeserializeStructure);
}
- private ReadOnlySpan GetReadOnlySpan(MemoryStream memoryStream)
+ private static ReadOnlySpan GetReadOnlySpan(MemoryStream memoryStream)
{
return new(memoryStream.GetBuffer(), (int)memoryStream.Position, (int)memoryStream.Length - (int)memoryStream.Position);
}
- private void InvalidateCompressedStream(FileStream compressedStream)
+ private static void InvalidateCompressedStream(FileStream compressedStream)
{
compressedStream.SetLength(0L);
}
- private void PreSave(object source, System.Timers.ElapsedEventArgs e)
+ private void PreSave(object source, ElapsedEventArgs e)
{
_waitEvent.Reset();
string fileNameActual = $"{_ptc.CachePathActual}.info";
string fileNameBackup = $"{_ptc.CachePathBackup}.info";
- FileInfo fileInfoActual = new FileInfo(fileNameActual);
+ FileInfo fileInfoActual = new(fileNameActual);
if (fileInfoActual.Exists && fileInfoActual.Length != 0L)
{
@@ -266,12 +287,13 @@ private void Save(string fileName)
{
int profiledFuncsCount;
- OuterHeader outerHeader = new OuterHeader();
-
- outerHeader.Magic = _outerHeaderMagic;
+ OuterHeader outerHeader = new()
+ {
+ Magic = _outerHeaderMagic,
- outerHeader.InfoFileVersion = InternalVersion;
- outerHeader.Endianness = Ptc.GetEndianness();
+ InfoFileVersion = InternalVersion,
+ Endianness = Ptc.GetEndianness(),
+ };
outerHeader.SetHeaderHash();
@@ -279,7 +301,7 @@ private void Save(string fileName)
{
Debug.Assert(stream.Seek(0L, SeekOrigin.Begin) == 0L && stream.Length == 0L);
- stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin);
+ stream.Seek(Unsafe.SizeOf(), SeekOrigin.Begin);
lock (_lock)
{
@@ -290,7 +312,7 @@ private void Save(string fileName)
Debug.Assert(stream.Position == stream.Length);
- stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin);
+ stream.Seek(Unsafe.SizeOf(), SeekOrigin.Begin);
Hash128 hash = XXHash128.ComputeHash(GetReadOnlySpan(stream));
stream.Seek(0L, SeekOrigin.Begin);
@@ -301,28 +323,26 @@ private void Save(string fileName)
return;
}
- using (FileStream compressedStream = new(fileName, FileMode.OpenOrCreate))
- using (DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true))
+ using FileStream compressedStream = new(fileName, FileMode.OpenOrCreate);
+ using DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true);
+ try
{
- try
- {
- SerializeStructure(compressedStream, outerHeader);
+ SerializeStructure(compressedStream, outerHeader);
- stream.WriteTo(deflateStream);
+ stream.WriteTo(deflateStream);
- _lastHash = hash;
- }
- catch
- {
- compressedStream.Position = 0L;
+ _lastHash = hash;
+ }
+ catch
+ {
+ compressedStream.Position = 0L;
- _lastHash = default;
- }
+ _lastHash = default;
+ }
- if (compressedStream.Position < compressedStream.Length)
- {
- compressedStream.SetLength(compressedStream.Position);
- }
+ if (compressedStream.Position < compressedStream.Length)
+ {
+ compressedStream.SetLength(compressedStream.Position);
}
}
@@ -334,9 +354,9 @@ private void Save(string fileName)
}
}
- private void Serialize(Stream stream, Dictionary profiledFuncs)
+ private static void Serialize(Stream stream, Dictionary profiledFuncs)
{
- SerializeDictionary(stream, profiledFuncs, (stream, structure) => SerializeStructure(stream, structure));
+ SerializeDictionary(stream, profiledFuncs, SerializeStructure);
}
[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 29*/)]
@@ -354,14 +374,14 @@ public void SetHeaderHash()
{
Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1);
- HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf()));
+ HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]);
}
public bool IsHeaderValid()
{
Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1);
- return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash;
+ return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf