Digital Design Lab

EE 214 - Autumn Semester 2021 - Indian Institute of Technology Bombay

This repository contains all the structural/behavioural modelled VHDL design files created using Quartus for all the projects done in this course.

The hardware used for this course was Krypton Development Board with Intel (Formerly Altera) MAX V CPLD, provided by WEL, IIT Bombay.

Name		Name	Last commit message	Last commit date
Latest commit History 39 Commits
2 to 4 Decoder Enable - Behav		2 to 4 Decoder Enable - Behav
2 to 4 Decoder Enable - Struct		2 to 4 Decoder Enable - Struct
3 to 8 Decoder - Behav		3 to 8 Decoder - Behav
4 bit 4x1 Multiplexer - Struct		4 bit 4x1 Multiplexer - Struct
4 bit 4x1 Multiplexor - Behav		4 bit 4x1 Multiplexor - Behav
4 x 3bit Multiplier - Struct		4 x 3bit Multiplier - Struct
8 Bit Adder - Struct		8 Bit Adder - Struct
ALU - Behav - Tue		ALU - Behav - Tue
Covid String Detector		Covid String Detector
Covid With LCD		Covid With LCD
Endsem		Endsem
Even Number Detector - Combinational		Even Number Detector - Combinational
Even Sequence Generator		Even Sequence Generator
Four Adder Subtracter - Struct		Four Adder Subtracter - Struct
Krypton String Detector		Krypton String Detector
Krypton With LED		Krypton With LED
Note Counter Without Priority Bits		Note Counter Without Priority Bits
Note Counter		Note Counter
Scrabble - Behav		Scrabble - Behav
Sequence Generator		Sequence Generator
Serial Adder		Serial Adder
Serial Comparator		Serial Comparator
Shifter		Shifter
Vowel Detector - Behav		Vowel Detector - Behav
README.md		README.md