From 7363e5945c93604ef0cca222cd9ca67029cf4d8c Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Mon, 4 Apr 2022 04:45:55 +0000 Subject: [PATCH] Sort imported instruction/register files before processing. (#57) If not done builds are not reproducible. --- LLVMImporter.py | 4 +- rizin/librz/asm/arch/hexagon/hexagon_disas.c | 796 +++++++++---------- rizin/librz/asm/arch/hexagon/hexagon_insn.h | 98 ++- 3 files changed, 447 insertions(+), 451 deletions(-) diff --git a/LLVMImporter.py b/LLVMImporter.py index 17c3a09b..ac9bf314 100755 --- a/LLVMImporter.py +++ b/LLVMImporter.py @@ -192,7 +192,7 @@ def update_hex_arch(self): "SysRegs64", ] reg_dir = "./import/registers/" if not self.test_mode else "../import/registers/" - for filename in os.listdir(reg_dir): + for filename in sorted(os.listdir(reg_dir)): if filename.split(".")[-1] != "json": continue with open(reg_dir + filename) as f: @@ -211,7 +211,7 @@ def update_hex_arch(self): instr_count = 0 insn_dir = "./import/instructions/" if not self.test_mode else "../import/instructions/" - for filename in os.listdir(insn_dir): + for filename in sorted(os.listdir(insn_dir)): if filename.split(".")[-1] != "json": continue instn_name = filename.replace(".json", "") diff --git a/rizin/librz/asm/arch/hexagon/hexagon_disas.c b/rizin/librz/asm/arch/hexagon/hexagon_disas.c index 97f10416..4ac3a109 100644 --- a/rizin/librz/asm/arch/hexagon/hexagon_disas.c +++ b/rizin/librz/asm/arch/hexagon/hexagon_disas.c @@ -3,7 +3,7 @@ // LLVM commit: 96e220e6886868d6663d966ecc396befffc355e7 // LLVM commit date: 2022-01-05 11:01:52 +0000 (ISO 8601 format) -// Date of code generation: 2022-04-02 10:55:22-04:00 +// Date of code generation: 2022-04-03 12:37:38-04:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: @@ -67353,39 +67353,47 @@ void hexagon_disasm_0x5(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff3fff) == 0x56c01000) { - // 0101011011000000PP01000000000000 | ickill - hi->instruction = HEX_INS_IMPORTED_ICKILL; + if ((hi_u32 & 0xffe03fe0) == 0x55a00000) { + // 01010101101sssssPP000000000ddddd | Rd = icdatar(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_ICDATAR_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 0; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "ickill"); + sprintf(hi->mnem_infix, "%s = icdatar(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0x56c00800) { - // 01010110110sssssPP00100000000000 | icinvidx(Rs) - hi->instruction = HEX_INS_IMPORTED_ICINVIDX_RS; + if ((hi_u32 & 0xffe03fe0) == 0x55e00000) { + // 01010101111sssssPP000000000ddddd | Rd = ictagr(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_ICTAGR_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; + hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "icinvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = ictagr(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -67410,85 +67418,77 @@ void hexagon_disasm_0x5(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff3fff) == 0x57e00000) { - // 0101011111100000PP00000000000000 | rte - hi->instruction = HEX_INS_IMPORTED_RTE; + if ((hi_u32 & 0xffe03fff) == 0x56c00800) { + // 01010110110sssssPP00100000000000 | icinvidx(Rs) + hi->instruction = HEX_INS_IMPORTED_ICINVIDX_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 0; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "rte"); + sprintf(hi->mnem_infix, "icinvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe020ff) == 0x55c00000) { - // 01010101110sssssPP0ttttt00000000 | ictagw(Rs,Rt) - hi->instruction = HEX_INS_IMPORTED_ICTAGW_RS_RT; + if ((hi_u32 & 0xffff3fff) == 0x56c01000) { + // 0101011011000000PP01000000000000 | ickill + hi->instruction = HEX_INS_IMPORTED_ICKILL; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->op_count = 0; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "ictagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "ickill"); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fe0) == 0x55a00000) { - // 01010101101sssssPP000000000ddddd | Rd = icdatar(Rs) - hi->instruction = HEX_INS_IMPORTED_RD_ICDATAR_RS; + if ((hi_u32 & 0xffe020ff) == 0x55c00000) { + // 01010101110sssssPP0ttttt00000000 | ictagw(Rs,Rt) + hi->instruction = HEX_INS_IMPORTED_ICTAGW_RS_RT; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 - hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = icdatar(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "ictagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fe0) == 0x55e00000) { - // 01010101111sssssPP000000000ddddd | Rd = ictagr(Rs) - hi->instruction = HEX_INS_IMPORTED_RD_ICTAGR_RS; + if ((hi_u32 & 0xffff3fff) == 0x57e00000) { + // 0101011111100000PP00000000000000 | rte + hi->instruction = HEX_INS_IMPORTED_RTE; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 - hi->ops[0].attr |= HEX_OP_REG_OUT; - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->op_count = 0; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = ictagr(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "rte"); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -68938,83 +68938,9 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0x64400020) { - // 01100100010sssssPP00000000100000 | resume(Rs) - hi->instruction = HEX_INS_IMPORTED_RESUME_RS; - hi->opcode = hi_u32; - hi->parse_bits = ((hi_u32)&0xc000) >> 14; - hi->pred = HEX_NOPRED; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - // Set RzAnalysisOp values - hi->ana_op.addr = hi->addr; - hi->ana_op.id = hi->instruction; - hi->ana_op.size = 4; - hi->ana_op.cond = RZ_TYPE_COND_AL; - hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "resume(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); - sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); - return; - } - if ((hi_u32 & 0xffff3fff) == 0x6c200080) { - // 0110110000100000PP00000010000000 | k0unlock - hi->instruction = HEX_INS_IMPORTED_K0UNLOCK; - hi->opcode = hi_u32; - hi->parse_bits = ((hi_u32)&0xc000) >> 14; - hi->pred = HEX_NOPRED; - hi->op_count = 0; - // Set RzAnalysisOp values - hi->ana_op.addr = hi->addr; - hi->ana_op.id = hi->instruction; - hi->ana_op.size = 4; - hi->ana_op.cond = RZ_TYPE_COND_AL; - hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "k0unlock"); - sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); - return; - } - if ((hi_u32 & 0xffe03fff) == 0x64600000) { - // 01100100011sssssPP00000000000000 | stop(Rs) - hi->instruction = HEX_INS_IMPORTED_STOP_RS; - hi->opcode = hi_u32; - hi->parse_bits = ((hi_u32)&0xc000) >> 14; - hi->pred = HEX_NOPRED; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - // Set RzAnalysisOp values - hi->ana_op.addr = hi->addr; - hi->ana_op.id = hi->instruction; - hi->ana_op.size = 4; - hi->ana_op.cond = RZ_TYPE_COND_AL; - hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "stop(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); - sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); - return; - } - if ((hi_u32 & 0xffe03fff) == 0x64000060) { - // 01100100000sssssPP00000001100000 | ciad(Rs) - hi->instruction = HEX_INS_IMPORTED_CIAD_RS; - hi->opcode = hi_u32; - hi->parse_bits = ((hi_u32)&0xc000) >> 14; - hi->pred = HEX_NOPRED; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - // Set RzAnalysisOp values - hi->ana_op.addr = hi->addr; - hi->ana_op.id = hi->instruction; - hi->ana_op.size = 4; - hi->ana_op.cond = RZ_TYPE_COND_AL; - hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "ciad(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); - sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); - return; - } - if ((hi_u32 & 0xffe03fe0) == 0x66000000) { - // 01100110000sssssPP000000000ddddd | Rd = getimask(Rs) - hi->instruction = HEX_INS_IMPORTED_RD_GETIMASK_RS; + if ((hi_u32 & 0xff803fe0) == 0x6e800000) { + // 011011101sssssssPP000000000ddddd | Rd = Ss + hi->instruction = HEX_INS_IMPORTED_RD_SS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; @@ -69023,55 +68949,14 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 hi->ops[0].attr |= HEX_OP_REG_OUT; hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - // Set RzAnalysisOp values - hi->ana_op.addr = hi->addr; - hi->ana_op.id = hi->instruction; - hi->ana_op.size = 4; - hi->ana_op.cond = RZ_TYPE_COND_AL; - hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = getimask(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); - sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); - return; - } - if ((hi_u32 & 0xffe03fff) == 0x64000000) { - // 01100100000sssssPP00000000000000 | swi(Rs) - hi->instruction = HEX_INS_IMPORTED_SWI_RS; - hi->opcode = hi_u32; - hi->parse_bits = ((hi_u32)&0xc000) >> 14; - hi->pred = HEX_NOPRED; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - // Set RzAnalysisOp values - hi->ana_op.addr = hi->addr; - hi->ana_op.id = hi->instruction; - hi->ana_op.size = 4; - hi->ana_op.cond = RZ_TYPE_COND_AL; - hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "swi(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); - sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); - return; - } - if ((hi_u32 & 0xffe020ff) == 0x6c000000) { - // 01101100000sssssPP0ttttt00000000 | tlbw(Rss,Rt) - hi->instruction = HEX_INS_IMPORTED_TLBW_RSS_RT; - hi->opcode = hi_u32; - hi->parse_bits = ((hi_u32)&0xc000) >> 14; - hi->pred = HEX_NOPRED; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].op.reg = (((hi_u32)&0x7f0000) >> 16); // Ss32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "tlbw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = %s", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_sys_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -69100,26 +68985,9 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff3fff) == 0x6c200060) { - // 0110110000100000PP00000001100000 | k0lock - hi->instruction = HEX_INS_IMPORTED_K0LOCK; - hi->opcode = hi_u32; - hi->parse_bits = ((hi_u32)&0xc000) >> 14; - hi->pred = HEX_NOPRED; - hi->op_count = 0; - // Set RzAnalysisOp values - hi->ana_op.addr = hi->addr; - hi->ana_op.id = hi->instruction; - hi->ana_op.size = 4; - hi->ana_op.cond = RZ_TYPE_COND_AL; - hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "k0lock"); - sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); - return; - } - if ((hi_u32 & 0xffe03fe0) == 0x66600000) { - // 01100110011sssssPP000000000ddddd | Rd = iassignr(Rs) - hi->instruction = HEX_INS_IMPORTED_RD_IASSIGNR_RS; + if ((hi_u32 & 0xffe03fe0) == 0x66000000) { + // 01100110000sssssPP000000000ddddd | Rd = getimask(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_GETIMASK_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; @@ -69135,37 +69003,35 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = iassignr(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = getimask(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xff803fe0) == 0x6f000000) { - // 011011110sssssssPP000000000ddddd | Rdd = Sss - hi->instruction = HEX_INS_IMPORTED_RDD_SSS; + if ((hi_u32 & 0xffe03fe0) == 0x66600000) { + // 01100110011sssssPP000000000ddddd | Rd = iassignr(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_IASSIGNR_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 hi->ops[0].attr |= HEX_OP_REG_OUT; - hi->ops[0].attr |= HEX_OP_REG_PAIR; hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x7f0000) >> 16); // Sss32 - hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = %s", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_sys_regs64(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = iassignr(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xff803fe0) == 0x6e800000) { - // 011011101sssssssPP000000000ddddd | Rd = Ss - hi->instruction = HEX_INS_IMPORTED_RD_SS; + if ((hi_u32 & 0xffe03fe0) == 0x6ce00000) { + // 01101100111sssssPP000000000ddddd | Rd = tlboc(Rss) + hi->instruction = HEX_INS_IMPORTED_RD_TLBOC_RSS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; @@ -69174,14 +69040,15 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 hi->ops[0].attr |= HEX_OP_REG_OUT; hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x7f0000) >> 16); // Ss32 + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = %s", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_sys_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = tlboc(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_double_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -69207,60 +69074,72 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0x64000040) { - // 01100100000sssssPP00000001000000 | iassignw(Rs) - hi->instruction = HEX_INS_IMPORTED_IASSIGNW_RS; + if ((hi_u32 & 0xff803fe0) == 0x6f000000) { + // 011011110sssssssPP000000000ddddd | Rdd = Sss + hi->instruction = HEX_INS_IMPORTED_RDD_SSS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; + hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7f0000) >> 16); // Sss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "iassignw(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = %s", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_sys_regs64(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0x64600040) { - // 01100100011sssssPP00000001000000 | nmi(Rs) - hi->instruction = HEX_INS_IMPORTED_NMI_RS; + if ((hi_u32 & 0xffe03fe0) == 0x6c400000) { + // 01101100010sssssPP000000000ddddd | Rdd = tlbr(Rs) + hi->instruction = HEX_INS_IMPORTED_RDD_TLBR_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; + hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "nmi(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = tlbr(%s)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0x6ca00000) { - // 01101100101sssssPP00000000000000 | tlbinvasid(Rs) - hi->instruction = HEX_INS_IMPORTED_TLBINVASID_RS; + if ((hi_u32 & 0xffe03f80) == 0x67000000) { + // 01100111000sssssPP0000000ddddddd | Sd = Rs + hi->instruction = HEX_INS_IMPORTED_SD_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; + hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x7f) >> 0); // Sd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "tlbinvasid(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = %s", hex_get_sys_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -69288,24 +69167,22 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03cff) == 0x64800000) { - // 01100100100sssssPP0000tt00000000 | setimask(Pt,Rs) - hi->instruction = HEX_INS_IMPORTED_SETIMASK_PT_RS; + if ((hi_u32 & 0xffe03fff) == 0x64000060) { + // 01100100000sssssPP00000001100000 | ciad(Rs) + hi->instruction = HEX_INS_IMPORTED_CIAD_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; + hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "setimask(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "ciad(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -69329,91 +69206,88 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff3fff) == 0x6c200020) { - // 0110110000100000PP00000000100000 | tlblock - hi->instruction = HEX_INS_IMPORTED_TLBLOCK; + if ((hi_u32 & 0xffe03fff) == 0x65200000) { + // 01100101001xxxxxPP00000000000000 | crswap(Rx,sgp1) + hi->instruction = HEX_INS_IMPORTED_CRSWAP_RX_SGP1; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 0; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "tlblock"); + sprintf(hi->mnem_infix, "crswap(%s,SGP1)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0x65200000) { - // 01100101001xxxxxPP00000000000000 | crswap(Rx,sgp1) - hi->instruction = HEX_INS_IMPORTED_CRSWAP_RX_SGP1; + if ((hi_u32 & 0xffe03fff) == 0x6d800000) { + // 01101101100xxxxxPP00000000000000 | crswap(Rxx,sgp1:0) + hi->instruction = HEX_INS_IMPORTED_CRSWAP_RXX_SGP1_0; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rxx32 hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "crswap(%s,SGP1)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "crswap(%s,SGP1:0)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fe0) == 0x6c400000) { - // 01101100010sssssPP000000000ddddd | Rdd = tlbr(Rs) - hi->instruction = HEX_INS_IMPORTED_RDD_TLBR_RS; + if ((hi_u32 & 0xffe03fff) == 0x64000020) { + // 01100100000sssssPP00000000100000 | cswi(Rs) + hi->instruction = HEX_INS_IMPORTED_CSWI_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; + hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 - hi->ops[0].attr |= HEX_OP_REG_OUT; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = tlbr(%s)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "CSwi(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03f80) == 0x67000000) { - // 01100111000sssssPP0000000ddddddd | Sd = Rs - hi->instruction = HEX_INS_IMPORTED_SD_RS; + if ((hi_u32 & 0xffe03fff) == 0x64000040) { + // 01100100000sssssPP00000001000000 | iassignw(Rs) + hi->instruction = HEX_INS_IMPORTED_IASSIGNW_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; + hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x7f) >> 0); // Sd32 - hi->ops[0].attr |= HEX_OP_REG_OUT; - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = %s", hex_get_sys_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "iassignw(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff3fff) == 0x6c200040) { - // 0110110000100000PP00000001000000 | tlbunlock - hi->instruction = HEX_INS_IMPORTED_TLBUNLOCK; + if ((hi_u32 & 0xffff3fff) == 0x6c200060) { + // 0110110000100000PP00000001100000 | k0lock + hi->instruction = HEX_INS_IMPORTED_K0LOCK; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; @@ -69424,57 +69298,68 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "tlbunlock"); + sprintf(hi->mnem_infix, "k0lock"); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fe0) == 0x6ce00000) { - // 01101100111sssssPP000000000ddddd | Rd = tlboc(Rss) - hi->instruction = HEX_INS_IMPORTED_RD_TLBOC_RSS; + if ((hi_u32 & 0xffff3fff) == 0x6c200080) { + // 0110110000100000PP00000010000000 | k0unlock + hi->instruction = HEX_INS_IMPORTED_K0UNLOCK; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.cond = RZ_TYPE_COND_AL; + hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "k0unlock"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64600040) { + // 01100100011sssssPP00000001000000 | nmi(Rs) + hi->instruction = HEX_INS_IMPORTED_NMI_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 - hi->ops[0].attr |= HEX_OP_REG_OUT; - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 - hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = tlboc(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_double_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "nmi(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0x6d800000) { - // 01101101100xxxxxPP00000000000000 | crswap(Rxx,sgp1:0) - hi->instruction = HEX_INS_IMPORTED_CRSWAP_RXX_SGP1_0; + if ((hi_u32 & 0xffe03fff) == 0x64400020) { + // 01100100010sssssPP00000000100000 | resume(Rs) + hi->instruction = HEX_INS_IMPORTED_RESUME_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rxx32 - hi->ops[0].attr |= HEX_OP_REG_OUT; - hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "crswap(%s,SGP1:0)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "resume(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03cff) == 0x64800020) { - // 01100100100sssssPP0000tt00100000 | setprio(Pt,Rs) - hi->instruction = HEX_INS_IMPORTED_SETPRIO_PT_RS; + if ((hi_u32 & 0xffe03cff) == 0x64800000) { + // 01100100100sssssPP0000tt00000000 | setimask(Pt,Rs) + hi->instruction = HEX_INS_IMPORTED_SETIMASK_PT_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; @@ -69489,26 +69374,28 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "setprio(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "setimask(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0x64000020) { - // 01100100000sssssPP00000000100000 | cswi(Rs) - hi->instruction = HEX_INS_IMPORTED_CSWI_RS; + if ((hi_u32 & 0xffe03cff) == 0x64800020) { + // 01100100100sssssPP0000tt00100000 | setprio(Pt,Rs) + hi->instruction = HEX_INS_IMPORTED_SETPRIO_PT_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; + hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "CSwi(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "setprio(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -69550,6 +69437,119 @@ void hexagon_disasm_0x6(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } + if ((hi_u32 & 0xffe03fff) == 0x64600000) { + // 01100100011sssssPP00000000000000 | stop(Rs) + hi->instruction = HEX_INS_IMPORTED_STOP_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.cond = RZ_TYPE_COND_AL; + hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "stop(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64000000) { + // 01100100000sssssPP00000000000000 | swi(Rs) + hi->instruction = HEX_INS_IMPORTED_SWI_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.cond = RZ_TYPE_COND_AL; + hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "swi(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x6ca00000) { + // 01101100101sssssPP00000000000000 | tlbinvasid(Rs) + hi->instruction = HEX_INS_IMPORTED_TLBINVASID_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.cond = RZ_TYPE_COND_AL; + hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "tlbinvasid(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x6c200020) { + // 0110110000100000PP00000000100000 | tlblock + hi->instruction = HEX_INS_IMPORTED_TLBLOCK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.cond = RZ_TYPE_COND_AL; + hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "tlblock"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x6c200040) { + // 0110110000100000PP00000001000000 | tlbunlock + hi->instruction = HEX_INS_IMPORTED_TLBUNLOCK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.cond = RZ_TYPE_COND_AL; + hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "tlbunlock"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0x6c000000) { + // 01101100000sssssPP0ttttt00000000 | tlbw(Rss,Rt) + hi->instruction = HEX_INS_IMPORTED_TLBW_RSS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.cond = RZ_TYPE_COND_AL; + hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "tlbw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); + return; + } } void hexagon_disasm_0x7(HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { @@ -85268,118 +85268,107 @@ void hexagon_disasm_0xa(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0xa2200000) { - // 10100010001sssssPP00000000000000 | dccleanidx(Rs) - hi->instruction = HEX_INS_IMPORTED_DCCLEANIDX_RS; + if ((hi_u32 & 0xffe03ffc) == 0xa0e02000) { + // 10100000111sssssPP100000000000dd | Pd = l2locka(Rs) + hi->instruction = HEX_INS_IMPORTED_PD_L2LOCKA_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; + hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - // Set RzAnalysisOp values - hi->ana_op.addr = hi->addr; - hi->ana_op.id = hi->instruction; - hi->ana_op.size = 4; - hi->ana_op.cond = RZ_TYPE_COND_AL; - hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "dccleanidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); - sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); - return; - } - if ((hi_u32 & 0xffff3fff) == 0xa8200000) { - // 1010100000100000PP00000000000000 | l2kill - hi->instruction = HEX_INS_IMPORTED_L2KILL; - hi->opcode = hi_u32; - hi->parse_bits = ((hi_u32)&0xc000) >> 14; - hi->pred = HEX_NOPRED; - hi->op_count = 0; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2kill"); + sprintf(hi->mnem_infix, "%s = l2locka(%s)", hex_get_pred_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0xa2600000) { - // 10100010011sssssPP00000000000000 | dccleaninvidx(Rs) - hi->instruction = HEX_INS_IMPORTED_DCCLEANINVIDX_RS; + if ((hi_u32 & 0xffe03fe0) == 0xa4200000) { + // 10100100001sssssPP000000000ddddd | Rd = dctagr(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_DCTAGR_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; + hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "dccleaninvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "%s = dctagr(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff3fff) == 0xa8201800) { - // 1010100000100000PP01100000000000 | l2gcleaninv - hi->instruction = HEX_INS_IMPORTED_L2GCLEANINV; + if ((hi_u32 & 0xffe03fe0) == 0xa4600000) { + // 10100100011sssssPP000000000ddddd | Rd = l2tagr(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_L2TAGR_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 0; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2gcleaninv"); + sprintf(hi->mnem_infix, "%s = l2tagr(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe020ff) == 0xa4400000) { - // 10100100010sssssPP0ttttt00000000 | l2tagw(Rs,Rt) - hi->instruction = HEX_INS_IMPORTED_L2TAGW_RS_RT; + if ((hi_u32 & 0xffe03fff) == 0xa2200000) { + // 10100010001sssssPP00000000000000 | dccleanidx(Rs) + hi->instruction = HEX_INS_IMPORTED_DCCLEANIDX_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; + hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2tagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "dccleanidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fe0) == 0xa4200000) { - // 10100100001sssssPP000000000ddddd | Rd = dctagr(Rs) - hi->instruction = HEX_INS_IMPORTED_RD_DCTAGR_RS; + if ((hi_u32 & 0xffe03fff) == 0xa2600000) { + // 10100010011sssssPP00000000000000 | dccleaninvidx(Rs) + hi->instruction = HEX_INS_IMPORTED_DCCLEANINVIDX_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; + hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 - hi->ops[0].attr |= HEX_OP_REG_OUT; - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = dctagr(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "dccleaninvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -85402,9 +85391,9 @@ void hexagon_disasm_0xa(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff3fff) == 0xa8200800) { - // 1010100000100000PP00100000000000 | l2gunlock - hi->instruction = HEX_INS_IMPORTED_L2GUNLOCK; + if ((hi_u32 & 0xffff3fff) == 0xa2000000) { + // 1010001000000000PP00000000000000 | dckill + hi->instruction = HEX_INS_IMPORTED_DCKILL; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; @@ -85415,72 +85404,66 @@ void hexagon_disasm_0xa(HexState *state, const ut32 hi_u32, HexInsn *hi, const u hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2gunlock"); + sprintf(hi->mnem_infix, "dckill"); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03ffc) == 0xa0e02000) { - // 10100000111sssssPP100000000000dd | Pd = l2locka(Rs) - hi->instruction = HEX_INS_IMPORTED_PD_L2LOCKA_RS; + if ((hi_u32 & 0xffe020ff) == 0xa4000000) { + // 10100100000sssssPP0ttttt00000000 | dctagw(Rs,Rt) + hi->instruction = HEX_INS_IMPORTED_DCTAGW_RS_RT; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 - hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = l2locka(%s)", hex_get_pred_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "dctagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fe0) == 0xa4600000) { - // 10100100011sssssPP000000000ddddd | Rd = l2tagr(Rs) - hi->instruction = HEX_INS_IMPORTED_RD_L2TAGR_RS; + if ((hi_u32 & 0xffe03fff) == 0xa6200000) { + // 10100110001sssssPP00000000000000 | l2cleanidx(Rs) + hi->instruction = HEX_INS_IMPORTED_L2CLEANIDX_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; + hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 - hi->ops[0].attr |= HEX_OP_REG_OUT; - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "%s = l2tagr(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "l2cleanidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe020ff) == 0xa4000000) { - // 10100100000sssssPP0ttttt00000000 | dctagw(Rs,Rt) - hi->instruction = HEX_INS_IMPORTED_DCTAGW_RS_RT; + if ((hi_u32 & 0xffe03fff) == 0xa8600000) { + // 10101000011sssssPP00000000000000 | l2cleaninvidx(Rs) + hi->instruction = HEX_INS_IMPORTED_L2CLEANINVIDX_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 2; + hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "dctagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "l2cleaninvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } @@ -85501,45 +85484,46 @@ void hexagon_disasm_0xa(HexState *state, const ut32 hi_u32, HexInsn *hi, const u sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff3fff) == 0xa2000000) { - // 1010001000000000PP00000000000000 | dckill - hi->instruction = HEX_INS_IMPORTED_DCKILL; + if ((hi_u32 & 0xffff20ff) == 0xa6a00000) { + // 1010011010100000PP0ttttt00000000 | l2gclean(Rtt) + hi->instruction = HEX_INS_IMPORTED_L2GCLEAN_RTT; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 0; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[0].attr |= HEX_OP_REG_PAIR; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "dckill"); + sprintf(hi->mnem_infix, "l2gclean(%s)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0xa6400000) { - // 10100110010sssssPP00000000000000 | l2invidx(Rs) - hi->instruction = HEX_INS_IMPORTED_L2INVIDX_RS; + if ((hi_u32 & 0xffff3fff) == 0xa8201800) { + // 1010100000100000PP01100000000000 | l2gcleaninv + hi->instruction = HEX_INS_IMPORTED_L2GCLEANINV; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->op_count = 0; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2invidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "l2gcleaninv"); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff20ff) == 0xa6a00000) { - // 1010011010100000PP0ttttt00000000 | l2gclean(Rtt) - hi->instruction = HEX_INS_IMPORTED_L2GCLEAN_RTT; + if ((hi_u32 & 0xffff20ff) == 0xa6c00000) { + // 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt) + hi->instruction = HEX_INS_IMPORTED_L2GCLEANINV_RTT; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; @@ -85553,32 +85537,30 @@ void hexagon_disasm_0xa(HexState *state, const ut32 hi_u32, HexInsn *hi, const u hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2gclean(%s)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "l2gcleaninv(%s)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0xa8600000) { - // 10101000011sssssPP00000000000000 | l2cleaninvidx(Rs) - hi->instruction = HEX_INS_IMPORTED_L2CLEANINVIDX_RS; + if ((hi_u32 & 0xffff3fff) == 0xa8200800) { + // 1010100000100000PP00100000000000 | l2gunlock + hi->instruction = HEX_INS_IMPORTED_L2GUNLOCK; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->op_count = 0; // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2cleaninvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "l2gunlock"); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0xa6600000) { - // 10100110011sssssPP00000000000000 | l2unlocka(Rs) - hi->instruction = HEX_INS_IMPORTED_L2UNLOCKA_RS; + if ((hi_u32 & 0xffe03fff) == 0xa6400000) { + // 10100110010sssssPP00000000000000 | l2invidx(Rs) + hi->instruction = HEX_INS_IMPORTED_L2INVIDX_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; @@ -85591,46 +85573,64 @@ void hexagon_disasm_0xa(HexState *state, const ut32 hi_u32, HexInsn *hi, const u hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2unlocka(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "l2invidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffe03fff) == 0xa6200000) { - // 10100110001sssssPP00000000000000 | l2cleanidx(Rs) - hi->instruction = HEX_INS_IMPORTED_L2CLEANIDX_RS; + if ((hi_u32 & 0xffff3fff) == 0xa8200000) { + // 1010100000100000PP00000000000000 | l2kill + hi->instruction = HEX_INS_IMPORTED_L2KILL; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; - hi->op_count = 1; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.cond = RZ_TYPE_COND_AL; + hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2kill"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0xa4400000) { + // 10100100010sssssPP0ttttt00000000 | l2tagw(Rs,Rt) + hi->instruction = HEX_INS_IMPORTED_L2TAGW_RS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; hi->ops[0].type = HEX_OP_TYPE_REG; hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2cleanidx(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "l2tagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias), hex_get_int_regs(hi->ops[1].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } - if ((hi_u32 & 0xffff20ff) == 0xa6c00000) { - // 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt) - hi->instruction = HEX_INS_IMPORTED_L2GCLEANINV_RTT; + if ((hi_u32 & 0xffe03fff) == 0xa6600000) { + // 10100110011sssssPP00000000000000 | l2unlocka(Rs) + hi->instruction = HEX_INS_IMPORTED_L2UNLOCKA_RS; hi->opcode = hi_u32; hi->parse_bits = ((hi_u32)&0xc000) >> 14; hi->pred = HEX_NOPRED; hi->op_count = 1; hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 - hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 // Set RzAnalysisOp values hi->ana_op.addr = hi->addr; hi->ana_op.id = hi->instruction; hi->ana_op.size = 4; hi->ana_op.cond = RZ_TYPE_COND_AL; hi->ana_op.type = hi->ana_op.prefix == RZ_ANALYSIS_OP_PREFIX_HWLOOP_END ? RZ_ANALYSIS_OP_TYPE_CJMP : RZ_ANALYSIS_OP_TYPE_NULL; - sprintf(hi->mnem_infix, "l2gcleaninv(%s)", hex_get_double_regs(hi->ops[0].op.reg, print_reg_alias)); + sprintf(hi->mnem_infix, "l2unlocka(%s)", hex_get_int_regs(hi->ops[0].op.reg, print_reg_alias)); sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix); return; } diff --git a/rizin/librz/asm/arch/hexagon/hexagon_insn.h b/rizin/librz/asm/arch/hexagon/hexagon_insn.h index 321d7a5d..03d3d344 100644 --- a/rizin/librz/asm/arch/hexagon/hexagon_insn.h +++ b/rizin/librz/asm/arch/hexagon/hexagon_insn.h @@ -3,17 +3,14 @@ // LLVM commit: 96e220e6886868d6663d966ecc396befffc355e7 // LLVM commit date: 2022-01-05 11:01:52 +0000 (ISO 8601 format) -// Date of code generation: 2022-01-24 07:53:55-05:00 +// Date of code generation: 2022-04-03 12:37:38-04:00 //======================================== // The following code is generated. // Do not edit. Repository of code generator: // https://github.com/rizinorg/rz-hexagon - #ifndef HEXAGON_INSN_H #define HEXAGON_INSN_H - -enum HEX_INS { - HEX_INS_INVALID_DECODE = 0, +enum HEX_INS { HEX_INS_INVALID_DECODE = 0, HEX_INS_A2_ABS, HEX_INS_A2_ABSP, HEX_INS_A2_ABSSAT, @@ -2276,63 +2273,63 @@ enum HEX_INS { HEX_INS_DEP_A2_ADDSAT, HEX_INS_DEP_A2_SUBSAT, HEX_INS_DEP_S2_PACKHL, - HEX_INS_IMPORTED_DCCLEANIDX_RS, - HEX_INS_IMPORTED_RESUME_RS, - HEX_INS_IMPORTED_L2KILL, - HEX_INS_IMPORTED_K0UNLOCK, - HEX_INS_IMPORTED_STOP_RS, - HEX_INS_IMPORTED_CIAD_RS, - HEX_INS_IMPORTED_ICKILL, - HEX_INS_IMPORTED_RD_GETIMASK_RS, - HEX_INS_IMPORTED_DCCLEANINVIDX_RS, - HEX_INS_IMPORTED_SWI_RS, - HEX_INS_IMPORTED_TLBW_RSS_RT, - HEX_INS_IMPORTED_L2GCLEANINV, + HEX_INS_IMPORTED_PD_L2LOCKA_RS, + HEX_INS_IMPORTED_RD_SS, HEX_INS_IMPORTED_RD_CTLBW_RSS_RT, - HEX_INS_IMPORTED_ICINVIDX_RS, - HEX_INS_IMPORTED_K0LOCK, - HEX_INS_IMPORTED_L2TAGW_RS_RT, - HEX_INS_IMPORTED_ICDATAW_RS_RT, - HEX_INS_IMPORTED_RTE, HEX_INS_IMPORTED_RD_DCTAGR_RS, + HEX_INS_IMPORTED_RD_GETIMASK_RS, HEX_INS_IMPORTED_RD_IASSIGNR_RS, - HEX_INS_IMPORTED_RDD_SSS, - HEX_INS_IMPORTED_DCINVIDX_RS, - HEX_INS_IMPORTED_L2GUNLOCK, - HEX_INS_IMPORTED_RD_SS, - HEX_INS_IMPORTED_ICTAGW_RS_RT, - HEX_INS_IMPORTED_PD_L2LOCKA_RS, - HEX_INS_IMPORTED_RD_TLBP_RS, + HEX_INS_IMPORTED_RD_ICDATAR_RS, + HEX_INS_IMPORTED_RD_ICTAGR_RS, HEX_INS_IMPORTED_RD_L2TAGR_RS, - HEX_INS_IMPORTED_IASSIGNW_RS, - HEX_INS_IMPORTED_NMI_RS, - HEX_INS_IMPORTED_TLBINVASID_RS, + HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT, + HEX_INS_IMPORTED_RD_TLBOC_RSS, + HEX_INS_IMPORTED_RD_TLBP_RS, + HEX_INS_IMPORTED_RDD_SSS, + HEX_INS_IMPORTED_RDD_TLBR_RS, + HEX_INS_IMPORTED_SD_RS, HEX_INS_IMPORTED_SDD_RSS, - HEX_INS_IMPORTED_DCTAGW_RS_RT, - HEX_INS_IMPORTED_L2GCLEAN, - HEX_INS_IMPORTED_DCKILL, - HEX_INS_IMPORTED_L2INVIDX_RS, - HEX_INS_IMPORTED_SETIMASK_PT_RS, + HEX_INS_IMPORTED_CIAD_RS, HEX_INS_IMPORTED_CRSWAP_RX_SGP0, - HEX_INS_IMPORTED_TLBLOCK, HEX_INS_IMPORTED_CRSWAP_RX_SGP1, - HEX_INS_IMPORTED_L2GCLEAN_RTT, - HEX_INS_IMPORTED_RDD_TLBR_RS, - HEX_INS_IMPORTED_L2CLEANINVIDX_RS, - HEX_INS_IMPORTED_L2UNLOCKA_RS, - HEX_INS_IMPORTED_SD_RS, - HEX_INS_IMPORTED_TLBUNLOCK, - HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT, - HEX_INS_IMPORTED_RD_TLBOC_RSS, HEX_INS_IMPORTED_CRSWAP_RXX_SGP1_0, - HEX_INS_IMPORTED_SETPRIO_PT_RS, HEX_INS_IMPORTED_CSWI_RS, - HEX_INS_IMPORTED_SIAD_RS, - HEX_INS_IMPORTED_RD_ICDATAR_RS, + HEX_INS_IMPORTED_DCCLEANIDX_RS, + HEX_INS_IMPORTED_DCCLEANINVIDX_RS, + HEX_INS_IMPORTED_DCINVIDX_RS, + HEX_INS_IMPORTED_DCKILL, + HEX_INS_IMPORTED_DCTAGW_RS_RT, + HEX_INS_IMPORTED_IASSIGNW_RS, + HEX_INS_IMPORTED_ICDATAW_RS_RT, + HEX_INS_IMPORTED_ICINVIDX_RS, + HEX_INS_IMPORTED_ICKILL, + HEX_INS_IMPORTED_ICTAGW_RS_RT, + HEX_INS_IMPORTED_K0LOCK, + HEX_INS_IMPORTED_K0UNLOCK, HEX_INS_IMPORTED_L2CLEANIDX_RS, - HEX_INS_IMPORTED_RD_ICTAGR_RS, + HEX_INS_IMPORTED_L2CLEANINVIDX_RS, + HEX_INS_IMPORTED_L2GCLEAN, + HEX_INS_IMPORTED_L2GCLEAN_RTT, + HEX_INS_IMPORTED_L2GCLEANINV, HEX_INS_IMPORTED_L2GCLEANINV_RTT, + HEX_INS_IMPORTED_L2GUNLOCK, + HEX_INS_IMPORTED_L2INVIDX_RS, + HEX_INS_IMPORTED_L2KILL, + HEX_INS_IMPORTED_L2TAGW_RS_RT, + HEX_INS_IMPORTED_L2UNLOCKA_RS, + HEX_INS_IMPORTED_NMI_RS, + HEX_INS_IMPORTED_RESUME_RS, + HEX_INS_IMPORTED_RTE, + HEX_INS_IMPORTED_SETIMASK_PT_RS, + HEX_INS_IMPORTED_SETPRIO_PT_RS, + HEX_INS_IMPORTED_SIAD_RS, HEX_INS_IMPORTED_START_RS, + HEX_INS_IMPORTED_STOP_RS, + HEX_INS_IMPORTED_SWI_RS, + HEX_INS_IMPORTED_TLBINVASID_RS, + HEX_INS_IMPORTED_TLBLOCK, + HEX_INS_IMPORTED_TLBUNLOCK, + HEX_INS_IMPORTED_TLBW_RSS_RT, HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDRX, HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_ADDRX, HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDRX, @@ -3696,5 +3693,4 @@ enum HEX_INS { HEX_INS_X2_AUTOJOIN_SA1_SETI_UNDOCUMENTED_SA2_TFRSI, HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_UNDOCUMENTED_SA2_TFRSI, }; - #endif \ No newline at end of file