Clarification on the behaviour of spike in debug mode and in normal mode for multicore scenario needed

[bantierr]

Hi,

I need some help to understand the differences that can arise between spike in debug mode (-d option, not the rv mode) and in normal mode when running multi-core systems.
I just stumbled across a scenario where the MINSTRET CSR has a different value when running spike in debug mode and in normal mode.
I am using 2 cores, and the difference arise when a core receives a software interrupt. The 2 core are synchronized (double checked using commit log).

The scenario is:

• core 0 goes into low power mode (and store a byte to an address to signal to core 1 it is WFI)
• core 1 wakes up core 0 (once the flag is there) using an software interrupt
• core 0 starts executing again
• core 0 reads MISNTRET

I was wondering if this behavior could be normal due to the multi-core scenario ?

(also, I am aware some behavioral changes are to expected, as mentioned in #936, but I would have assumed the number of instructions would be identical)

Please, tell me if you need a concrete example or if the explanation is not precise enough.

Thank you for your help,
Best,
Quentin