From 019cd2fa7ac3294e95773a323a4dc0892ee21eeb Mon Sep 17 00:00:00 2001 From: linzhida Date: Mon, 9 Dec 2024 17:14:47 +0800 Subject: [PATCH] Fix read value of CSR mip. The read value of mip should only depend on the two bits, VSEIP and VSTIP of hvip. This PR fix the read value of CSR mip when Sscofpmf extension enabled. After implementing the Sscofpmf extension, hvip.LCOFIP became writable. This caused an issue where the entire value of hvip was OR-ed when reading mip. I revise the mip read logic to make it depend only on the hvip.VSEIP and hvip.VSTIP bits. Co-authored-by: Zhaoyang You --- riscv/csrs.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 0e2e3e12d..2952b9095 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -781,7 +781,7 @@ mip_csr_t::mip_csr_t(processor_t* const proc, const reg_t addr): } reg_t mip_csr_t::read() const noexcept { - return val | state->hvip->basic_csr_t::read(); + return val | (state->hvip->basic_csr_t::read() & (MIP_VSEIP | MIP_VSTIP)); } void mip_csr_t::backdoor_write_with_mask(const reg_t mask, const reg_t val) noexcept {