Invalid PLL2 configuration in R_CGC_ClocksCfg FSP5.7.0

[andross092]

Please check line 598 in r_cgc.c

the code

r_cgc_pll_cfg(&p_clock_cfg->pll2_cfg, CGC_CLOCK_PLL2, pll2_hz, pllccr);
uses the variable pllccr filled for PLL configuration.
It should be pll2ccr
Thanks for support

[renesas-austin-hansen]

Hi @andross092, which version of FSP are you using? I was not able to find this issue in recent versions.

[andross092]

I'm using FSP 5.7.0,
anyway it is in the master branch

fsp/ra/fsp/src/r_cgc/r_cgc.c

Line 598 in 21e946b

r_cgc_pll_cfg(&p_clock_cfg->pll2_cfg, CGC_CLOCK_PLL2, pll2_hz, pllccr);

as you can see here
https://github.com/renesas/fsp/blob/21e946ba20a3a25737ad7d8808596a4771d0671a/ra/fsp/src/r_cgc/r_cgc.c#L507C2-L514C6

pll2ccr is redeemed, but then it is not used in the actual r_cgc_pll_cfg for PLL2

[renesas-austin-hansen]

Ah sorry, line numbers are a bit offset in our development system and I got mixed up with a similar function. We will investigate.